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kbob/icebreaker.pcf

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icebreaker.pcf
# 12 MHz clock
set_io -nowarn CLK 35
# RS232
set_io -nowarn RX 6
set_io -nowarn TX 9
# LEDs and Button
set_io -nowarn BTN_N 10
set_io -nowarn LEDR_N 11
set_io -nowarn LEDG_N 37
# RGB LED Driver
set_io -nowarn LED_RED_N 39
set_io -nowarn LED_GRN_N 40
set_io -nowarn LED_BLU_N 41
# SPI Flash
set_io -nowarn FLASH_SCK 15
set_io -nowarn FLASH_SSB 16
set_io -nowarn FLASH_IO0 14
set_io -nowarn FLASH_IO1 17
set_io -nowarn FLASH_IO2 12
set_io -nowarn FLASH_IO3 13
# PMOD 1A
set_io -nowarn P1A1 4
set_io -nowarn P1A2 2
set_io -nowarn P1A3 47
set_io -nowarn P1A4 45
set_io -nowarn P1A7 3
set_io -nowarn P1A8 48
set_io -nowarn P1A9 46
set_io -nowarn P1A10 44
# PMOD 1B
set_io -nowarn P1B1 43
set_io -nowarn P1B2 38
set_io -nowarn P1B3 34
set_io -nowarn P1B4 31
set_io -nowarn P1B7 42
set_io -nowarn P1B8 36
set_io -nowarn P1B9 32
set_io -nowarn P1B10 28
# PMOD 2
set_io -nowarn P2_1 27
set_io -nowarn P2_2 25
set_io -nowarn P2_3 21
set_io -nowarn P2_4 19
set_io -nowarn P2_7 26
set_io -nowarn P2_8 23
set_io -nowarn P2_9 20
set_io -nowarn P2_10 18
# LEDs and Buttons (PMOD 2)
set_io -nowarn LED1 26
set_io -nowarn LED2 27
set_io -nowarn LED3 25
set_io -nowarn LED4 23
set_io -nowarn LED5 21
set_io -nowarn BTN1 20
set_io -nowarn BTN2 19
set_io -nowarn BTN3 18
Raw
top.json
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"src": "top.v:42|/usr/local/bin/../share/yosys/ice40/arith_map.v:43"
}
},
"$auto$alumacc.cc:474:replace_alu$53.C": {
"hide_name": 1,
"bits": [ 238, 239, 130, 146, 149, 152, 155, 158, 161, 164, 100, 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, 133, 136, 139, 142 ],
"attributes": {
"src": "top.v:46|/usr/local/bin/../share/yosys/ice40/arith_map.v:43"
}
},
"$auto$alumacc.cc:474:replace_alu$56.C": {
"hide_name": 1,
"bits": [ 240, 241, 199, 215, 218, 221, 224, 227, 230, 233, 169, 171, 174, 177, 180, 183, 186, 189, 192, 195, 198, 202, 205, 208, 211 ],
"attributes": {
"src": "top.v:48|/usr/local/bin/../share/yosys/ice40/arith_map.v:43"
}
},
"BTN_N": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:7"
}
},
"CLK": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:6"
}
},
"LED1": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:8"
}
},
"LED2": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"src": "top.v:9"
}
},
"LED3": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"src": "top.v:10"
}
},
"LED4": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"src": "top.v:11"
}
},
"LED5": {
"hide_name": 0,
"bits": [ 7 ],
"attributes": {
"src": "top.v:12"
}
},
"P1A1": {
"hide_name": 0,
"bits": [ 8 ],
"attributes": {
"src": "top.v:13"
}
},
"P1A2": {
"hide_name": 0,
"bits": [ 9 ],
"attributes": {
"src": "top.v:14"
}
},
"P1A3": {
"hide_name": 0,
"bits": [ 10 ],
"attributes": {
"src": "top.v:15"
}
},
"P1A4": {
"hide_name": 0,
"bits": [ 7 ],
"attributes": {
"src": "top.v:16"
}
},
"counter30": {
"hide_name": 0,
"bits": [ 13, 23, 75, 78, 81, 84, 87, 90, 93, 96, 30, 34, 37, 40, 43, 46, 49, 52, 55, 58, 62, 65, 68, 71, 8 ],
"attributes": {
"src": "top.v:37"
}
},
"counter30p": {
"hide_name": 0,
"bits": [ 17, 27, 213, 216, 219, 222, 225, 228, 231, 234, 168, 172, 175, 178, 181, 184, 187, 190, 193, 196, 200, 203, 206, 209, 22 ],
"attributes": {
"src": "top.v:37"
}
},
"counter60": {
"hide_name": 0,
"bits": [ 15, 25, 144, 147, 150, 153, 156, 159, 162, 165, 99, 103, 106, 109, 112, 115, 118, 121, 124, 127, 131, 134, 137, 140, 21 ],
"attributes": {
"src": "top.v:37"
}
},
"err": {
"hide_name": 0,
"bits": [ 7 ],
"attributes": {
"src": "top.v:38"
}
},
"pll_clk30": {
"hide_name": 0,
"bits": [ 10 ],
"attributes": {
"src": "top.v:19"
}
},
"pll_clk60": {
"hide_name": 0,
"bits": [ 9 ],
"attributes": {
"src": "top.v:19"
}
},
"pll_locked": {
"hide_name": 0,
"bits": [ 11 ],
"attributes": {
"src": "top.v:19"
}
},
"prev": {
"hide_name": 0,
"bits": [ 19 ],
"attributes": {
"src": "top.v:38"
}
}
}
}
}
}
Raw
top.v
`default_nettype none
`define W 24
module top (
input CLK,
input BTN_N,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output P1A1,
output P1A2,
output P1A3,
output P1A4
);
wire pll_clk60, pll_clk30, pll_locked;
SB_PLL40_2F_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT_PORTB("GENCLK_HALF"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b1001111), // DIVF = 79
.DIVQ(3'b100), // DIVQ = 4
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll (
.PACKAGEPIN(CLK),
.PLLOUTGLOBALA(pll_clk60),
.PLLOUTGLOBALB(pll_clk30),
.LOCK(pll_locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.LATCHINPUTVALUE(1'b0));
reg [`W:0] counter60, counter30p, counter30n, counter30;
reg prev, err;
always @(posedge pll_clk30)
if (pll_locked)
counter30 <= counter30 + 1;
always @(posedge pll_clk60)
if (pll_locked) begin
counter60 <= counter60 + 1;
if (pll_clk30) begin
counter30p <= counter30p + 1;
err <= prev;
prev <= 1;
end
else begin
counter30n <= counter30n + 1;
err <= ~prev;
prev <= 0;
end
end
assign LED1 = counter30[`W] & BTN_N;
assign LED2 = counter60[`W] & BTN_N;
assign LED3 = counter30p[`W] & BTN_N;
assign LED4 = counter30p[`W] & BTN_N;
assign LED5 = err;
assign P1A1 = counter30[`W];
assign P1A2 = pll_clk60;
assign P1A3 = pll_clk30;
assign P1A4 = err;
endmodule
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