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@kbob
Created January 7, 2019 07:14
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`default_nettype none
module blinky (CLK, LED1);
input wire CLK;
output wire LED1;
parameter WIDTH = 24;
parameter CLK_HZ = 12_000_000;
reg [WIDTH-1:0] counter;
reg [7:0] led1;
wire [WIDTH-1:0] wrap = (CLK_HZ >> 8) - 1;
always @(posedge CLK)
if (counter == wrap) begin
counter <= 0;
led1 <= led1 + 1;
end
else
counter <= counter + 1;
assign LED1 = led1 * led1 > counter[15:0];
endmodule
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