Created
September 4, 2021 01:58
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IO_LOC "input_a" 14; | |
IO_LOC "input_b" 15; | |
IO_LOC "and_result" 16; |
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module example_and_gate ( | |
input_a, | |
input_b, | |
and_result); | |
input input_a; | |
input input_b; | |
output and_result; | |
wire and_temp; | |
assign and_temp = input_a | input_b; | |
assign and_result = and_temp; | |
endmodule | |
//And gate example from https://www.nandland.com/verilog/tutorials/tutorial-introduction-to-verilog-for-beginners.html | |
//it appears that the tango nano and this editor want the | for AND the & appears to be an or statement (?) | |
//LeRoy Miller Learning stuff Sep 2, 2021 |
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