DCM FPGA

clk_gen.v

//////////////////////////////////////////////////////////////////////////////*/


module matrix_clkgen (
  CLKIN,
	RST,
	CLKFX
	);

  input		CLKIN;
	input		RST;
	output	CLKFX;			//CLKFX => BUFG => "CLKFX" output
  
  wire  [2:0] STATUS;
  wire	CLKGEN_LOCKED;	  		//Connected to spread spectrum locked signal
  wire  RST_DCM;
  
  assign RST_DCM = RST | (STATUS[2] & ~CLKGEN_LOCKED);
  
	DCM_CLKGEN    #(
		.CLKIN_PERIOD (20.000),
		.SPREAD_SPECTRUM ("CENTER_HIGH_SPREAD"),
 		.CLKFX_MD_MAX("4.1"),
 		.CLKFX_MULTIPLY	(4),
 		.CLKFX_DIVIDE	(1) )	
	dcm_clk (
		.CLKIN   	(CLKIN),
		.FREEZEDCM (1'b0),
		.PROGDATA	(1'b0),
		.PROGEN 	(1'b0),
		.PROGCLK	(1'b0), 
		.RST     	(RST_DCM),
		.CLKFX   	(CLKFX_DCM),
		.LOCKED  	(CLKGEN_LOCKED),
		.STATUS(STATUS)
		);
   


	BUFG 	clkfx_bufg 	(.I(CLKFX_DCM),  .O(CLKFX) ) ;

endmodule