keefo/image_blink_sincircle.vhdl

## gistfile1.txt
# clash (for make/vhdl/Image/Image.manifest)
# clash (for make/vhdl/Image/Image.manifest)
Loading dependencies took 2.047838812s
Applied 287 transformations
Normalisation took 0.364243634s
Netlist generation took 0.012578591s
Testbench generation took 0.000280213s
Total compilation took 2.428932468s
# vivado (for make/logo.synth.dcp)

****** Vivado v2016.2 (64-bit)
  **** SW Build 1577090 on Thu Jun  2 16:32:35 MDT 2016
  **** IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-749] XILINX_TCLSTORE_USERAREA is set to '/run/user/1006/extra-dir-56252307181665/2016.2/XilinxTclStore'.
source /home/rupert/myrtlepkgs/pkgs/fpga/logo/make/logo.synth.tcl
# source "logo.project.tcl"
## create_project -in_memory -part xc7a200tsbg484-1
## set_property default_lib work [current_project]
## set_property target_language VHDL [current_project]
## read_vhdl -library work /home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/output_serialiser.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out_clocking.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixels_to_vga.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga_0.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_state2d.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_types.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpack_vga.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpackvga_types.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpackvga_unpackvga.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpackvga_unpackvga1.vhdl
## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/common/tmds_encoder.vhdl
## read_vhdl -library work vhdl/Image/image.vhdl
## read_vhdl -library work vhdl/Image/image_blink.vhdl
## read_vhdl -library work vhdl/Image/image_blink3.vhdl
## read_vhdl -library work vhdl/Image/image_blink_sincircle.vhdl
## read_vhdl -library work vhdl/Image/image_blink_w.vhdl
## read_vhdl -library work vhdl/Image/image_types.vhdl
## read_xdc "/home/rupert/myrtlepkgs/pkgs/fpga/logo/./NexysVideo_Master.xdc"
# set_param synth.vivado.isSynthRun true
# set_param synth.elaboration.rodinMoreOptions "rt::set_parameter synRetiming true"
# synth_design -top top -part xc7a200tsbg484-1
Command: synth_design -top top -part xc7a200tsbg484-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 10469
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1027.230 ; gain = 142.137 ; free physical = 24090 ; free virtual = 29659
---------------------------------------------------------------------------------
WARNING: [Synth 8-1565] actual for formal port blank is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:92]
WARNING: [Synth 8-1565] actual for formal port blank is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:99]
WARNING: [Synth 8-1565] actual for formal port blank is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:106]
WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:116]
WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:123]
WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:130]
WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:137]
WARNING: [Synth 8-1565] actual for formal port rst is neither a static name nor a globally static expression [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:80]
INFO: [Synth 8-638] synthesizing module 'top' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:21]
INFO: [Synth 8-113] binding component instance 'clock_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:52]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string
	Parameter CLKFBOUT_MULT bound to: 12 - type: integer
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float
	Parameter CLKOUT0_DIVIDE bound to: 24 - type: integer
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT2_DIVIDE bound to: 16 - type: integer
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
	Parameter CLK_FEEDBACK bound to: CLKFBOUT - type: string
	Parameter COMPENSATION bound to: SYSTEM_SYNCHRONOUS - type: string
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
	Parameter REF_JITTER bound to: 0.100000 - type: float
	Parameter RESET_ON_LOSS_OF_LOCK bound to: 0 - type: bool
INFO: [Synth 8-113] binding component instance 'pll_inst' to cell 'PLL_BASE' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:61]
INFO: [Synth 8-113] binding component instance 'clock50_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:83]
INFO: [Synth 8-113] binding component instance 'clock200_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:88]
INFO: [Synth 8-113] binding component instance 'clock75_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:93]
INFO: [Synth 8-638] synthesizing module 'pixels_to_vga' [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixels_to_vga.vhdl:22]
INFO: [Synth 8-638] synthesizing module 'pixelstovga_pixelstovga' [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga.vhdl:20]
INFO: [Synth 8-638] synthesizing module 'pixelstovga_state2d' [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_state2d.vhdl:17]
INFO: [Synth 8-256] done synthesizing module 'pixelstovga_state2d' (1#1) [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_state2d.vhdl:17]
INFO: [Synth 8-256] done synthesizing module 'pixelstovga_pixelstovga' (2#1) [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga.vhdl:20]
INFO: [Synth 8-256] done synthesizing module 'pixels_to_vga' (3#1) [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixels_to_vga.vhdl:22]
INFO: [Synth 8-638] synthesizing module 'image' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image.vhdl:23]
INFO: [Synth 8-638] synthesizing module 'image_blink' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink.vhdl:19]
INFO: [Synth 8-638] synthesizing module 'image_blink_sincircle' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:16]
ERROR: [Synth 8-690] width mismatch in assignment; target has 64 bits, source has 128 bits [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:25]
ERROR: [Synth 8-285] failed synthesizing module 'image_blink_sincircle' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:16]
ERROR: [Synth 8-285] failed synthesizing module 'image_blink' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink.vhdl:19]
ERROR: [Synth 8-285] failed synthesizing module 'image' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image.vhdl:23]
ERROR: [Synth 8-285] failed synthesizing module 'top' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:21]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.668 ; gain = 181.574 ; free physical = 24049 ; free virtual = 29618
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
17 Infos, 8 Warnings, 0 Critical Warnings and 6 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Mar 29 13:57:06 2017...
Error when running Shake build system:
* make/logo.bit
* make/logo.route.dcp
* make/logo.synth.dcp
user error (Development.Shake.cmd, system command failed
Command: vivado -mode batch -source /home/rupert/myrtlepkgs/pkgs/fpga/logo/make/logo.synth.tcl
Current directory: /home/rupert/myrtlepkgs/pkgs/fpga/logo/make
Exit code: 1
Stderr:
ERROR: [Synth 8-690] width mismatch in assignment; target has 64 bits, source has 128 bits [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:25]
ERROR: [Synth 8-285] failed synthesizing module 'image_blink_sincircle' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:16]
ERROR: [Synth 8-285] failed synthesizing module 'image_blink' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink.vhdl:19]
ERROR: [Synth 8-285] failed synthesizing module 'image' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image.vhdl:23]
ERROR: [Synth 8-285] failed synthesizing module 'top' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:21]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
)

## image_blink_sincircle.vhdl
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.image_types.all;

entity image_blink_sincircle is
  port(x      : in signed(63 downto 0);
       y      : in signed(63 downto 0);
       result : out image_types.pixel);
end;

architecture structural of image_blink_sincircle is
  signal case_scrut     : boolean;
  signal wild_app_arg   : signed(63 downto 0);
  signal wild_app_arg_0 : signed(63 downto 0);
  signal wild_app_arg_1 : signed(63 downto 0);
  signal wild           : signed(63 downto 0);
begin
  case_scrut <= tagToEnum(wild);

  wild_app_arg <= x * x;

  wild_app_arg_0 <= y * y;

  wild_app_arg_1 <= wild_app_arg + wild_app_arg_0;

  wild <= to_signed(1,64) when wild_app_arg_1 < to_signed(900,64) else to_signed(0,64);

  result <= (pixel_sel0 => to_unsigned(0,8)
            ,pixel_sel1 => to_unsigned(0,8)
            ,pixel_sel2 => to_unsigned(0,8)) when case_scrut else
            (pixel_sel0 => to_unsigned(255,8)
            ,pixel_sel1 => to_unsigned(255,8)
            ,pixel_sel2 => to_unsigned(255,8));
end;
	# clash (for make/vhdl/Image/Image.manifest)
	# clash (for make/vhdl/Image/Image.manifest)
	Loading dependencies took 2.047838812s
	Applied 287 transformations
	Normalisation took 0.364243634s
	Netlist generation took 0.012578591s
	Testbench generation took 0.000280213s
	Total compilation took 2.428932468s
	# vivado (for make/logo.synth.dcp)

	****** Vivado v2016.2 (64-bit)
	**** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
	**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
	** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

	INFO: [Common 17-749] XILINX_TCLSTORE_USERAREA is set to '/run/user/1006/extra-dir-56252307181665/2016.2/XilinxTclStore'.
	source /home/rupert/myrtlepkgs/pkgs/fpga/logo/make/logo.synth.tcl
	# source "logo.project.tcl"
	## create_project -in_memory -part xc7a200tsbg484-1
	## set_property default_lib work [current_project]
	## set_property target_language VHDL [current_project]
	## read_vhdl -library work /home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/output_serialiser.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out_clocking.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixels_to_vga.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga_0.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_state2d.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_types.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpack_vga.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpackvga_types.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpackvga_unpackvga.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/DVIDOutput/vhdl/UnpackVGA/unpackvga_unpackvga1.vhdl
	## read_vhdl -library work /nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/common/tmds_encoder.vhdl
	## read_vhdl -library work vhdl/Image/image.vhdl
	## read_vhdl -library work vhdl/Image/image_blink.vhdl
	## read_vhdl -library work vhdl/Image/image_blink3.vhdl
	## read_vhdl -library work vhdl/Image/image_blink_sincircle.vhdl
	## read_vhdl -library work vhdl/Image/image_blink_w.vhdl
	## read_vhdl -library work vhdl/Image/image_types.vhdl
	## read_xdc "/home/rupert/myrtlepkgs/pkgs/fpga/logo/./NexysVideo_Master.xdc"
	# set_param synth.vivado.isSynthRun true
	# set_param synth.elaboration.rodinMoreOptions "rt::set_parameter synRetiming true"
	# synth_design -top top -part xc7a200tsbg484-1
	Command: synth_design -top top -part xc7a200tsbg484-1
	Starting synth_design
	Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
	INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
	INFO: Launching helper process for spawning children vivado processes
	INFO: Helper process launched with PID 10469
	---------------------------------------------------------------------------------
	Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1027.230 ; gain = 142.137 ; free physical = 24090 ; free virtual = 29659
	---------------------------------------------------------------------------------
	WARNING: [Synth 8-1565] actual for formal port blank is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:92]
	WARNING: [Synth 8-1565] actual for formal port blank is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:99]
	WARNING: [Synth 8-1565] actual for formal port blank is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:106]
	WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:116]
	WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:123]
	WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:130]
	WARNING: [Synth 8-1565] actual for formal port reset is neither a static name nor a globally static expression [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/vhdl/DVID/vivado/dvid_out.vhdl:137]
	WARNING: [Synth 8-1565] actual for formal port rst is neither a static name nor a globally static expression [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:80]
	INFO: [Synth 8-638] synthesizing module 'top' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:21]
	INFO: [Synth 8-113] binding component instance 'clock_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:52]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string
	Parameter CLKFBOUT_MULT bound to: 12 - type: integer
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float
	Parameter CLKOUT0_DIVIDE bound to: 24 - type: integer
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT2_DIVIDE bound to: 16 - type: integer
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
	Parameter CLK_FEEDBACK bound to: CLKFBOUT - type: string
	Parameter COMPENSATION bound to: SYSTEM_SYNCHRONOUS - type: string
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
	Parameter REF_JITTER bound to: 0.100000 - type: float
	Parameter RESET_ON_LOSS_OF_LOCK bound to: 0 - type: bool
	INFO: [Synth 8-113] binding component instance 'pll_inst' to cell 'PLL_BASE' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:61]
	INFO: [Synth 8-113] binding component instance 'clock50_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:83]
	INFO: [Synth 8-113] binding component instance 'clock200_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:88]
	INFO: [Synth 8-113] binding component instance 'clock75_buffer' to cell 'BUFG' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:93]
	INFO: [Synth 8-638] synthesizing module 'pixels_to_vga' [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixels_to_vga.vhdl:22]
	INFO: [Synth 8-638] synthesizing module 'pixelstovga_pixelstovga' [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga.vhdl:20]
	INFO: [Synth 8-638] synthesizing module 'pixelstovga_state2d' [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_state2d.vhdl:17]
	INFO: [Synth 8-256] done synthesizing module 'pixelstovga_state2d' (1#1) [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_state2d.vhdl:17]
	INFO: [Synth 8-256] done synthesizing module 'pixelstovga_pixelstovga' (2#1) [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixelstovga_pixelstovga.vhdl:20]
	INFO: [Synth 8-256] done synthesizing module 'pixels_to_vga' (3#1) [/nix/store/vxvzpdzdghzajdjfnkysxf6k5342a51n-video-io-0.2.0.0/share/x86_64-linux-ghc-8.0.1.20161117/video-io-0.2.0.0/dist/PixelsToVGA/vhdl/PixelsToVGA/pixels_to_vga.vhdl:22]
	INFO: [Synth 8-638] synthesizing module 'image' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image.vhdl:23]
	INFO: [Synth 8-638] synthesizing module 'image_blink' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink.vhdl:19]
	INFO: [Synth 8-638] synthesizing module 'image_blink_sincircle' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:16]
	ERROR: [Synth 8-690] width mismatch in assignment; target has 64 bits, source has 128 bits [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:25]
	ERROR: [Synth 8-285] failed synthesizing module 'image_blink_sincircle' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:16]
	ERROR: [Synth 8-285] failed synthesizing module 'image_blink' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink.vhdl:19]
	ERROR: [Synth 8-285] failed synthesizing module 'image' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image.vhdl:23]
	ERROR: [Synth 8-285] failed synthesizing module 'top' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:21]
	---------------------------------------------------------------------------------
	Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.668 ; gain = 181.574 ; free physical = 24049 ; free virtual = 29618
	---------------------------------------------------------------------------------
	RTL Elaboration failed
	INFO: [Common 17-83] Releasing license: Synthesis
	17 Infos, 8 Warnings, 0 Critical Warnings and 6 Errors encountered.
	synth_design failed
	ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
	INFO: [Common 17-206] Exiting Vivado at Wed Mar 29 13:57:06 2017...
	Error when running Shake build system:
	* make/logo.bit
	* make/logo.route.dcp
	* make/logo.synth.dcp
	user error (Development.Shake.cmd, system command failed
	Command: vivado -mode batch -source /home/rupert/myrtlepkgs/pkgs/fpga/logo/make/logo.synth.tcl
	Current directory: /home/rupert/myrtlepkgs/pkgs/fpga/logo/make
	Exit code: 1
	Stderr:
	ERROR: [Synth 8-690] width mismatch in assignment; target has 64 bits, source has 128 bits [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:25]
	ERROR: [Synth 8-285] failed synthesizing module 'image_blink_sincircle' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink_sincircle.vhdl:16]
	ERROR: [Synth 8-285] failed synthesizing module 'image_blink' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image_blink.vhdl:19]
	ERROR: [Synth 8-285] failed synthesizing module 'image' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/make/vhdl/Image/image.vhdl:23]
	ERROR: [Synth 8-285] failed synthesizing module 'top' [/home/rupert/myrtlepkgs/pkgs/fpga/logo/src/top.vhdl:21]
	ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
	)
	-- Automatically generated VHDL-93
	library IEEE;
	use IEEE.STD_LOGIC_1164.ALL;
	use IEEE.NUMERIC_STD.ALL;
	use IEEE.MATH_REAL.ALL;
	use std.textio.all;
	use work.all;
	use work.image_types.all;

	entity image_blink_sincircle is
	port(x : in signed(63 downto 0);
	y : in signed(63 downto 0);
	result : out image_types.pixel);
	end;

	architecture structural of image_blink_sincircle is
	signal case_scrut : boolean;
	signal wild_app_arg : signed(63 downto 0);
	signal wild_app_arg_0 : signed(63 downto 0);
	signal wild_app_arg_1 : signed(63 downto 0);
	signal wild : signed(63 downto 0);
	begin
	case_scrut <= tagToEnum(wild);

	wild_app_arg <= x * x;

	wild_app_arg_0 <= y * y;

	wild_app_arg_1 <= wild_app_arg + wild_app_arg_0;

	wild <= to_signed(1,64) when wild_app_arg_1 < to_signed(900,64) else to_signed(0,64);

	result <= (pixel_sel0 => to_unsigned(0,8)
	,pixel_sel1 => to_unsigned(0,8)
	,pixel_sel2 => to_unsigned(0,8)) when case_scrut else
	(pixel_sel0 => to_unsigned(255,8)
	,pixel_sel1 => to_unsigned(255,8)
	,pixel_sel2 => to_unsigned(255,8));
	end;