SICP - A Simulator for Digital Circuits

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<!--Xholon Workbook http://www.primordion.com/Xholon/gwt/ MIT License, Copyright (C) Ken Webb, Fri Apr 11 2014 09:51:00 GMT-0400 (EDT)-->
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<Notes><![CDATA[
Xholon
------
Title: SICP - A Simulator for Digital Circuits
Description: 
Url: http://www.primordion.com/Xholon/gwt/
InternalName: 10419442
Keywords: 

My Notes
--------

This Xholon Workbook explores the `Simulator for Digital Circuits` model
described in section 3.3.4 of Abelson and Sussman's
`Structure and Interpretation of Computer Programs, second edition` book[1].
The book provides Scheme[8] code for one possible implementation of the model.
I've jotted down a few ideas in my journal, but I'm not yet sure which of
several Xholon-based approaches I'll proceed with.

The book is freely available online in several formats, including PDF[3], HTML5, and SVG.
This workbook includes one or more of the SVG images created by Andres Raba[4].

Goal:
 - write as little code as possible
 - how much can I do with structure only?

A Petri Net approach
--------------------
One promising approach is to implement the circuits as Petri Nets,
a mechanism that Xholon already supports.
Petri Net places represent the wires, which carry a signal with a value of 0 or 1.
Petri Net transitions represent the primitive functions,
which act on the values in the wires.
The circuits themselves are just containers for the primitive functions.

References
----------
(1) http://en.wikipedia.org/wiki/Structure_and_Interpretation_of_Computer_Programs
(2) http://sicpebook.wordpress.com/
(3) http://sicpebook.files.wordpress.com/2012/11/sicp.pdf
(4) https://github.com/sarabander/sicp
(5) https://github.com/robertberry/SICP-Exercises
(6) https://github.com/zodiac/isicp
(7) http://sarabander.github.io/sicp/
(8) http://en.wikipedia.org/wiki/Scheme_%28programming_language%29

]]></Notes> 

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  <Wire roleName="b" token="1"/>
  <Wire roleName="s"/>
  <Wire roleName="c"/>
  
  <!-- Truth Table expected after several time steps when the circuit stabilizes
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  0 0    0 0
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  <HalfAdder>
    <Wire roleName="d"/>
    <Wire roleName="e"/>
    <OrGate kineticsType="KINETICS_LOGIC_OR"> <!-- KINETICS_LOGIC_OR 9 -->
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    <AndGate kineticsType="KINETICS_LOGIC_AND"> <!-- KINETICS_LOGIC_AND 8 -->
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        <InputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='a']"/>
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    <AnalysisCRN/>
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