SICP - A Simulator for Digital Circuits - Full Adder

fullAdder.gv

/*
Automatically generated by Xholon version 0.8.1, using org.primordion.ef.petrinet.Xholon2Graphviz4PetriNets.java
Fri Apr 11 11:57:06 GMT-400 2014 1397231826029
model: SICP - A Simulator for Digital Circuits - Full Adder
www.primordion.com/Xholon

To view this file, use Graphviz dot|fdp|neato|twopi|circo|sfdp from http://www.graphviz.org/
For example, to generate an SVG file:
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Alternatively try one of these:
  dot -Tsvg -O DigitalSystem_33_1397231826029.gv
  dot -Tsvg -O -Grankdir=LR DigitalSystem_33_1397231826029.gv
  fdp -Tsvg -O DigitalSystem_33_1397231826029.gv
  neato -Tsvg -O DigitalSystem_33_1397231826029.gv
  circo -Tsvg -O DigitalSystem_33_1397231826029.gv
Or use one of: -Tgif -Tjpg -Tpdf -Tpng -Txdot -Txlib
See also: http://hughesbennett.net/Graphviz
See also: http://graphviz-dev.appspot.com/
See also: http://www.webgraphviz.com/
See also: http://rise4fun.com/agl/
*/
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  [shape=ellipse]
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  [fillcolor="#ffff00"]
  [shape=ellipse]
 37 [label="s"]
  [fillcolor="#ffff00"]
  [shape=ellipse]
 38 [label="c"]
  [fillcolor="#ffff00"]
  [shape=ellipse]
 subgraph cluster39 { label="FullAdder"
  40 [label="q"]
   [fillcolor="#ffff00"]
   [shape=ellipse]
  41 [label="kq"]
   [fillcolor="#ffff00"]
   [shape=ellipse]
  42 [label="ab"]
   [fillcolor="#ffff00"]
   [shape=ellipse]
  subgraph cluster43 { label="HalfAdder"
   44 [label="d"]
    [fillcolor="#ffff00"]
    [shape=ellipse]
   45 [label="e"]
    [fillcolor="#ffff00"]
    [shape=ellipse]
   46 [label="OrGate"]
    [fillcolor="#00ffff"]
    [shape=box]
    46 -> 44;
   52 [label="AndGate"]
    [fillcolor="#00ffff"]
    [shape=box]
   58 [label="AndGate"]
    [fillcolor="#00ffff"]
    [shape=box]
    44 -> 58;
    45 -> 58;
   64 [label="Inverter"]
    [fillcolor="#00ffff"]
    [shape=box]
    64 -> 45;
  }
  subgraph cluster69 { label="HalfAdder"
   70 [label="d"]
    [fillcolor="#ffff00"]
    [shape=ellipse]
   71 [label="e"]
    [fillcolor="#ffff00"]
    [shape=ellipse]
   72 [label="OrGate"]
    [fillcolor="#00ffff"]
    [shape=box]
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   78 [label="AndGate"]
    [fillcolor="#00ffff"]
    [shape=box]
   84 [label="AndGate"]
    [fillcolor="#00ffff"]
    [shape=box]
    70 -> 84;
    71 -> 84;
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    [fillcolor="#00ffff"]
    [shape=box]
    90 -> 71;
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  95 [label="OrGate"]
   [fillcolor="#00ffff"]
   [shape=box]
   41 -> 95;
   42 -> 95;
   52 -> 42; 58 -> 40; 42 -> 64; 40 -> 72; 40 -> 78; 78 -> 41; 41 -> 90;
 }
  35 -> 46; 36 -> 46; 35 -> 52; 36 -> 52; 34 -> 72; 34 -> 78; 84 -> 37; 95 -> 38;
}

xholonWorkbook.xml

<?xml version="1.0" encoding="UTF-8"?>
<!--Xholon Workbook http://www.primordion.com/Xholon/gwt/ MIT License, Copyright (C) Ken Webb, Fri Apr 11 2014 12:44:05 GMT-0400 (EDT)-->
<XholonWorkbook>

<Notes><![CDATA[
Xholon
------
Title: SICP - A Simulator for Digital Circuits - Full Adder
Description: 
Url: http://www.primordion.com/Xholon/gwt/
InternalName: 10483194
Keywords: 

My Notes
--------

This Xholon Workbook extends the earlier workbook:
https://gist.github.com/kenwebb/10419442

The SVG image on this page was generated using Xholon2Graphviz4PetriNets,
and the dot program on my Linux desktop.
I'm saving the Graphviz dot (.gv) file as a separate file in the gist.

In addition to the references included in gist 10419442,
I've also taken ideas from Figure 109 in the book New Mathematics by L. C. Pascoe.
The Full Adder Truth Table is from p. 157 of Pascoe.

]]></Notes> 

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  <Wire superClass="PlacePN"/>
  
  <PrimitiveFunctionBox superClass="TransitionPN">
    <Inverter/>
    <AndGate/>
    <OrGate/>
  </PrimitiveFunctionBox>
  
  <!-- containers -->
  <Circuit>
    <HalfAdder/>
    <FullAdder/>
  </Circuit>
  
  
</_-.XholonClass>

<xholonClassDetails>
  
</xholonClassDetails>

<DigitalSystem>
  
  <!-- these wires are external to the Full Adder -->
  <Wire roleName="k" token="1"/>
  <Wire roleName="a" token="1"/>
  <Wire roleName="b" token="1"/>
  <Wire roleName="s"/>
  <Wire roleName="c"/>
  
  <!-- Truth Table expected after several time steps when the circuit stabilizes
  inputs   outputs
  a b k    Total  c s    Tested
  0 0 0     0     0 0    OK
  0 0 1     1     0 1    OK
  0 1 0     1     0 1    OK
  1 0 0     1     0 1    OK
  0 1 1    10     1 0    OK
  1 0 1    10     1 0    OK
  1 1 0    10     1 0    OK
  1 1 1    11     1 1    OK
  -->
  
  <FullAdder>
    <!-- these wires are internal to the Full Adder -->
    <Wire roleName="q"/>
    <Wire roleName="kq"/>
    <Wire roleName="ab"/>
    
    <HalfAdder>
      <!-- these wires are internal to this Half Adder -->
      <Wire roleName="d"/>
      <Wire roleName="e"/>
      
      <OrGate kineticsType="KINETICS_LOGIC_OR">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='a']"/>
          <InputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='b']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='d']"/>
        </OutputArcs>
      </OrGate>
      <AndGate kineticsType="KINETICS_LOGIC_AND">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='a']"/>
          <InputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='b']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='ab']"/>
        </OutputArcs>
      </AndGate>
      <AndGate kineticsType="KINETICS_LOGIC_AND">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='d']"/>
          <InputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='e']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='q']"/>
        </OutputArcs>
      </AndGate>
      <Inverter kineticsType="KINETICS_LOGIC_NOT">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='ab']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='e']"/>
        </OutputArcs>
      </Inverter>
    </HalfAdder>
    
    <HalfAdder>
      <!-- these wires are internal to this Half Adder -->
      <Wire roleName="d"/>
      <Wire roleName="e"/>
      
      <OrGate kineticsType="KINETICS_LOGIC_OR">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='k']"/>
          <InputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='q']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='d']"/>
        </OutputArcs>
      </OrGate>
      <AndGate kineticsType="KINETICS_LOGIC_AND">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='k']"/>
          <InputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='q']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='kq']"/>
        </OutputArcs>
      </AndGate>
      <AndGate kineticsType="KINETICS_LOGIC_AND">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='d']"/>
          <InputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='e']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='s']"/>
        </OutputArcs>
      </AndGate>
      <Inverter kineticsType="KINETICS_LOGIC_NOT">
        <InputArcs>
          <InputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='kq']"/>
        </InputArcs>
        <OutputArcs>
          <OutputArc weight="1" connector="ancestor::HalfAdder/Wire[@roleName='e']"/>
        </OutputArcs>
      </Inverter>
    </HalfAdder>
    
    <OrGate kineticsType="KINETICS_LOGIC_OR">
      <InputArcs>
        <InputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='kq']"/>
        <InputArc weight="1" connector="ancestor::FullAdder/Wire[@roleName='ab']"/>
      </InputArcs>
      <OutputArcs>
        <OutputArc weight="1" connector="ancestor::DigitalSystem/Wire[@roleName='c']"/>
      </OutputArcs>
    </OrGate>
  </FullAdder>
  
  <PetriNet roleName="sicpDigitalCircuit02">
    <QueueTransitions connector="ancestor::DigitalSystem"/>
    <AnalysisPetriNet/>
    <AnalysisCRN/>
    <AnalysisCat/>
  </PetriNet>
</DigitalSystem>

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]]></Blockbehavior>

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