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#include "stm32f030x8.h"
/*
SPI functions (interrupt driven)
*/
/*
#define BUFF_SIZE 32
volatile uint8_t I2C1_Buffer_Tx[BUFF_SIZE], I2C1_Buffer_Rx[BUFF_SIZE];
volatile uint32_t I2C1_Tx1_Counter = 0, I2C1_Rx1_Counter = 0;
*/
/* Function declarations */
PROCESS(CLK49_5)
begin
if rising_edge(CLK49_5)then
RAMADDR2GR<=bin_to_gray(std_logic_vector(to_unsigned(RAMADDR2,9)));
-------------dual clock sync-------------------------
RAMADDR1GR_sync0<=RAMADDR1GR;
RAMADDR1GR_sync1<=RAMADDR1GR_sync0;
VGAFLAG(1)<=VGAFLAG(0);
VGAFLAG(2)<=VGAFLAG(1);
@keshakot
keshakot / vga.vhdl
Last active April 13, 2020 06:43
VHDL module for generating VGA sync signals and color output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga is
port(
CLK: in std_logic;
R_OUT,G_OUT,B_OUT: OUT std_logic_vector(7 downto 0);
R_IN,G_IN,B_IN: IN std_logic_vector(7 downto 0);