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Tessel + Bus Blaster + OpenOCD

Setup

  1. Install OpenOCD. You need version >= 0.8.0.
  1. Save the openocd script below as tessel-busblaster.cfg.

  2. Plug the JTAG cable into the Bus Blaster's adapter board and the Tessel. Pin one is towards the USB port; the cable goes over the center of the board.

  3. Run

arm-none-eabi-gdb out/Release/tessel-firmware.elf -ex 'target remote | openocd -c "gdb_port pipe;" -f ../jtag/tessel-busblaster.cfg'

(adjust paths as appropriate) to launch gdb.

GDB commands

Basics

  • c - continue
  • ctrl-c - stop
  • p expr - print the value of the C expression expr
  • bt - stack backtrace
  • s - step instruction, goes into calls
  • n - next instruction, skips over calls
  • fin - run until return from function
  • break function - break at the beginning of a function (can also pass file.c:line)
  • delete 1 - delete the first breakpoint
  • tbreak - break only once

Hardware

  • mon reset - Reset Tessel and all on-chip peripherals (like the reset button)
  • mon soft_reset_halt - Reset the CPU only

Other notes

  • Make sure your .elf file matches the firmware on the Tessel. Otherwise the position information will be wrong and calls will crash.

  • LPC1800 SPIFI Flash is functional from OpenOCD, but I don't recommend using it. Flash Tessel with the bootloader (make arm-deploy) before running GDB.

  • The ROM confuses JTAG on reset. If you c and then ctrl-c, it recovers. To debug the very beginning of execution, use

    mon soft_reset_halt
    tbreak main
    c
    
###### Bus Blaster
interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0c08 0x0f1b
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
adapter_khz 1000
reset_config srst_only
###### LPC1830
set _CHIPNAME lpc1830
set _ENDIAN little
set _M3_JTAG_TAPID 0x4ba00477
jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
set _TARGETNAME $_CHIPNAME.m3
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config srst
###### Flash configuration
#A large working area greatly reduces flash write times
set _WORKAREASIZE 0x8000
$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
#Configure the flash bank; 0x14000000 is the base address for
#lpc43xx/lpc18xx family micros.
#flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3
###### Debug commands
$_TARGETNAME configure -event gdb-attach {
echo "Halting target"
halt
}
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