Created
February 14, 2021 20:51
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DPS5015 Vals
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>>>> adc1 | |
ADC1 settings | |
Parsing error: | |
SR : 0x00000000 [0x40012400] | |
Parsing error: | |
CR1 : 0x00000000 [0x40012404] | |
Parsing error: | |
CR2 : 0x00000000 [0x40012408] | |
Parsing error: | |
SMPR1 : 0x00000000 [0x4001240c] | |
Parsing error: | |
SMPR2 : 0x00000000 [0x40012410] | |
Parsing error: | |
JOFR1 : 0x00000000 [0x40012414] | |
Parsing error: | |
JOFR2 : 0x00000000 [0x40012418] | |
Parsing error: | |
JOFR3 : 0x00000000 [0x4001241c] | |
Parsing error: | |
JOFR4 : 0x00000000 [0x40012420] | |
Parsing error: | |
HTR : 0x00000000 [0x40012424] | |
Parsing error: | |
LTR : 0x00000000 [0x40012428] | |
Parsing error: | |
SQR1 : 0x00000000 [0x4001242c] | |
Parsing error: | |
SQR2 : 0x00000000 [0x40012430] | |
Parsing error: | |
SQR3 : 0x00000000 [0x40012434] | |
Parsing error: | |
JSQR : 0x00000000 [0x40012438] | |
Parsing error: | |
JDR1 : 0x00000000 [0x4001243c] | |
Parsing error: | |
JDR2 : 0x00000000 [0x40012440] | |
Parsing error: | |
JDR3 : 0x00000000 [0x40012444] | |
Parsing error: | |
JDR4 : 0x00000000 [0x40012448] | |
Parsing error: | |
DR : 0x00000000 [0x4001244c] | |
>>>> afio | |
AFIO settings | |
Parsing error: | |
EVCR : 0x00000000 [0x40010000] | |
Parsing error: | |
MAPR : 0x00000000 [0x40010004] | |
Parsing error: | |
EXTICR1 : 0x00000000 [0x40010008] | |
Parsing error: | |
EXTICR2 : 0x00000000 [0x4001000c] | |
Parsing error: | |
EXTICR3 : 0x00000000 [0x40010010] | |
Parsing error: | |
EXTICR4 : 0x00000000 [0x40010014] | |
Parsing error: | |
MAPR2 : 0x00000000 [0x40010018] | |
>>>> dac | |
DAC settings | |
Parsing error: | |
CR : 0x00000000 [0x40007400] | |
Parsing error: | |
SWTRIGR : 0x00000000 [0x40007404] | |
Parsing error: | |
DHR12R1 : 0x00000000 [0x40007408] | |
Parsing error: | |
DHR12L1 : 0x00000000 [0x4000740c] | |
Parsing error: | |
DHR8R1 : 0x00000000 [0x40007410] | |
Parsing error: | |
DHR12R2 : 0x00000000 [0x40007414] | |
Parsing error: | |
DHR12L2 : 0x00000000 [0x40007418] | |
Parsing error: | |
DHR8R2 : 0x00000000 [0x4000741c] | |
Parsing error: | |
DHR12RD : 0x00000000 [0x40007420] | |
Parsing error: | |
DHR12LD : 0x00000000 [0x40007424] | |
Parsing error: | |
DHR8RD : 0x00000000 [0x40007428] | |
Parsing error: | |
DOR1 : 0x00000000 [0x4000742c] | |
Parsing error: | |
DOR2 : 0x00000000 [0x40007430] | |
Parsing error: | |
SR : 0x00000000 [0x40007434] | |
>>>> dma | |
DMA settings | |
Parsing error: | |
ISR : 0x00000000 [0x40020000] | |
Parsing error: | |
IFCR : 0x00000000 [0x40020004] | |
Parsing error: | |
CCR1 : 0x00000000 [0x40020008] | |
Parsing error: | |
CNDTR : 0x00000000 [0x40020084] | |
Parsing error: | |
CPAR1 : 0x00000000 [0x40020010] | |
Parsing error: Previous state query failed, trying to reconnect | |
jtag status contains invalid mode value - communication failure | |
Polling target stm32f1x.cpu failed, trying to reexamine | |
Examination failed, GDB will be halted. Polling again in 6300ms | |
CMAR1 : 0x00000000 [0x40020014] | |
Parsing error: | |
CCR2 : 0x00000000 [0x4002001c] | |
Parsing error: | |
CNDTR : 0x00000000 [0x40020084] | |
Parsing error: | |
CPAR2 : 0x00000000 [0x40020024] | |
Parsing error: | |
CMAR2 : 0x00000000 [0x40020028] | |
Parsing error: | |
CCR3 : 0x00000000 [0x40020030] | |
Parsing error: | |
CNDTR : 0x00000000 [0x40020084] | |
Parsing error: | |
CPAR3 : 0x00000000 [0x40020038] | |
Parsing error: | |
CMAR3 : 0x00000000 [0x4002003c] | |
Parsing error: | |
CCR4 : 0x00000000 [0x40020044] | |
Parsing error: | |
CNDTR : 0x00000000 [0x40020084] | |
Parsing error: | |
CPAR4 : 0x00000000 [0x4002004c] | |
Parsing error: | |
CMAR4 : 0x00000000 [0x40020050] | |
Parsing error: | |
CCR5 : 0x00000000 [0x40020058] | |
Parsing error: | |
CNDTR : 0x00000000 [0x40020084] | |
Parsing error: | |
CPAR5 : 0x00000000 [0x40020060] | |
Parsing error: | |
CMAR5 : 0x00000000 [0x40020064] | |
Parsing error: | |
CCR6 : 0x00000000 [0x4002006c] | |
Parsing error: | |
CNDTR : 0x00000000 [0x40020084] | |
Parsing error: | |
CPAR6 : 0x00000000 [0x40020074] | |
Parsing error: | |
CMAR6 : 0x00000000 [0x40020078] | |
Parsing error: | |
CCR7 : 0x00000000 [0x40020080] | |
Parsing error: | |
CNDTR : 0x00000000 [0x40020084] | |
Parsing error: | |
CPAR7 : 0x00000000 [0x40020088] | |
>>>> exti | |
EXTI settings | |
Parsing error: | |
IMR : 0x00000000 [0x40010400] | |
Parsing error: | |
EMR : 0x00000000 [0x40010404] | |
Parsing error: | |
RTSR : 0x00000000 [0x40010408] | |
Parsing error: | |
FTSR : 0x00000000 [0x4001040c] | |
Parsing error: | |
SWIER : 0x00000000 [0x40010410] | |
Parsing error: | |
PR : 0x00000000 [0x40010414] | |
>>>> gpio | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
// PA0 I 0 An U7 | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PA1 I 0 An M2 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PA2 I 0 An SEL button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO2); | |
// PA3 I 0 An M1 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO3); | |
// PA4 I 0 An DAC1_OUT TL594.2 (1IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PA5 I 0 An DAC2_OUT TL594.15 (2IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PA6 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PA7 I 0 An ADC1_IN7 R30-U2.7:V_OUT-B (measures Vout) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PA8 I 0 An TFT.7 (not used by TFT) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO8); | |
// PA9 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO9); | |
// PA10 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO10); | |
// PA11 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO11); | |
// PA12 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO12); | |
// PA13 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO13); | |
// PA14 I 0 An SWDCLK | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO14); | |
// PA15 I 0 An R41-TL594.16 (2IN+) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO15); | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
// PB0 I 0 An ADC1_IN8 R7/R2-R14-D4 (measures Vin) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PB1 I 0 An ADC1_IN9 R33-U2.1:V_OUT-A (measures Iout) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PB2 I 0 An | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO2); | |
// PB3 I 0 An R11-R17-R25-U2.5 (V_inB+) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO3); | |
// PB4 I 0 An PWR button | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PB5 I 0 An Rotary press | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PB6 I 0 An NC? | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PB7 I 0 An TIM4_CH2 | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PB8 I 0 An Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO8); | |
// PB9 I 0 An Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO9); | |
// PB10 I 0 An | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO10); | |
// PB11 I 0 An nPwrEnable R29-TFT.2 (TFT_VCC) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO11); | |
// PB12 I 0 An SPI2_NSS TFT_RESET | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO12); | |
// PB13 I 0 An SPI2_SCK | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO13); | |
// PB14 I 0 An SPI2_MISO TFT_A0 | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO14); | |
// PB15 I 0 An SPI2_MOSI | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO15); | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
// PC0 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PC1 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PC2 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO2); | |
// PC3 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO3); | |
// PC4 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PC5 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PC6 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PC7 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PC8 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO8); | |
// PC9 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO9); | |
// PC10 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO10); | |
// PC11 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO11); | |
// PC12 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO12); | |
// PC13 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO13); | |
// PC14 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO14); | |
// PC15 I 0 An | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO15); | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
Parsing error: | |
// PD0 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PD1 I 0 An U7 | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PD2 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO2); | |
// PD3 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO3); | |
// PD4 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PD5 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PD6 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PD7 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PD8 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO8); | |
// PD9 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO9); | |
// PD10 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO10); | |
// PD11 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO11); | |
// PD12 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO12); | |
// PD13 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO13); | |
// PD14 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO14); | |
// PD15 I 0 An | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO15); | |
>>>> gpioa | |
GPIOA settings | |
Parsing error: | |
CRL : 0x00000000 [0x40010800] | |
Parsing error: | |
CRH : 0x00000000 [0x40010804] | |
Parsing error: | |
IDR : 0x00000000 [0x40010808] | |
Parsing error: | |
ODR : 0x00000000 [0x4001080c] | |
Parsing error: | |
BSRR : 0x00000000 [0x40010810] | |
Parsing error: | |
BRR : 0x00000000 [0x40010814] | |
Parsing error: | |
LCKR : 0x00000000 [0x40010818] | |
>>>> gpiob | |
GPIOB settings | |
Parsing error: | |
CRL : 0x00000000 [0x40010c00] | |
Parsing error: | |
CRH : 0x00000000 [0x40010c04] | |
Parsing error: | |
IDR : 0x00000000 [0x40010c08] | |
Parsing error: | |
ODR : 0x00000000 [0x40010c0c] | |
Parsing error: | |
BSRR : 0x00000000 [0x40010c10] | |
Parsing error: | |
BRR : 0x00000000 [0x40010c14] | |
Parsing error: | |
LCKR : 0x00000000 [0x40010c18] | |
>>>> gpioc | |
GPIOC settings | |
Parsing error: | |
CRL : 0x00000000 [0x40011000] | |
Parsing error: | |
CRH : 0x00000000 [0x40011004] | |
Parsing error: | |
IDR : 0x00000000 [0x40011008] | |
Parsing error: | |
ODR : 0x00000000 [0x4001100c] | |
Parsing error: Previous state query failed, trying to reconnect | |
jtag status contains invalid mode value - communication failure | |
Polling target stm32f1x.cpu failed, trying to reexamine | |
Examination failed, GDB will be halted. Polling again in 6300ms | |
BSRR : 0x00000000 [0x40011010] | |
Parsing error: | |
BRR : 0x00000000 [0x40011014] | |
Parsing error: | |
LCKR : 0x00000000 [0x40011018] | |
>>>> gpiod | |
GPIOD settings | |
Parsing error: | |
CRL : 0x00000000 [0x40011400] | |
Parsing error: | |
CRH : 0x00000000 [0x40011404] | |
Parsing error: | |
IDR : 0x00000000 [0x40011408] | |
Parsing error: | |
ODR : 0x00000000 [0x4001140c] | |
Parsing error: | |
BSRR : 0x00000000 [0x40011410] | |
Parsing error: | |
BRR : 0x00000000 [0x40011414] | |
Parsing error: | |
LCKR : 0x00000000 [0x40011418] | |
>>>> rcc | |
RCC settings | |
Parsing error: | |
CR : 0x00000000 [0x40021000] | |
Parsing error: | |
CFGR : 0x00000000 [0x40021004] | |
Parsing error: | |
CIR : 0x00000000 [0x40021008] | |
Parsing error: | |
APB2RSTR : 0x00000000 [0x4002100c] | |
Parsing error: | |
APB1RSTR : 0x00000000 [0x40021010] | |
Parsing error: | |
AHBENR : 0x00000000 [0x40021014] | |
Parsing error: | |
APB2ENR : 0x00000000 [0x40021018] | |
Parsing error: | |
APB1ENR : 0x00000000 [0x4002101c] | |
Parsing error: | |
BDCR : 0x00000000 [0x40021020] | |
Parsing error: | |
CSR : 0x00000000 [0x40021024] | |
Parsing error: | |
CFGR2 : 0x00000000 [0x4002102c] | |
>>>> spi1 | |
SPI1 settings | |
Parsing error: | |
CR2 : 0x00000000 [0x40013000] | |
Parsing error: | |
CR1 : 0x00000000 [0x40013004] | |
Parsing error: | |
SR : 0x00000000 [0x40013008] | |
Parsing error: | |
DR : 0x00000000 [0x4001300c] | |
Parsing error: | |
CRCPR : 0x00000000 [0x40013010] | |
Parsing error: | |
RXCRCR : 0x00000000 [0x40013014] | |
Parsing error: | |
TXCRCR : 0x00000000 [0x40013018] | |
>>>> spi2 | |
SPI2 settings | |
Parsing error: | |
CR2 : 0x00000000 [0x40003800] | |
Parsing error: | |
CR1 : 0x00000000 [0x40003804] | |
Parsing error: | |
SR : 0x00000000 [0x40003808] | |
Parsing error: | |
DR : 0x00000000 [0x4000380c] | |
Parsing error: | |
CRCPR : 0x00000000 [0x40003810] | |
Parsing error: | |
RXCRCR : 0x00000000 [0x40003814] | |
Parsing error: | |
TXCRCR : 0x00000000 [0x40003818] | |
>>>> tim4 | |
TIM4 settings | |
Parsing error: | |
CR1 : 0x00000000 [0x40000800] | |
Parsing error: | |
CR2 : 0x00000000 [0x40000804] | |
Parsing error: | |
SMC : 0x00000000 [0x40000808] | |
Parsing error: | |
DIER : 0x00000000 [0x4000080c] | |
Parsing error: | |
SR : 0x00000000 [0x40000810] | |
Parsing error: | |
EGR : 0x00000000 [0x40000814] | |
Parsing error: | |
CCMR1 : 0x00000000 [0x40000818] | |
Parsing error: | |
CCMR2 : 0x00000000 [0x4000081c] | |
Parsing error: | |
CCER : 0x00000000 [0x40000820] | |
Parsing error: | |
CNT : 0x00000000 [0x40000824] | |
Parsing error: | |
PSC : 0x00000000 [0x40000828] | |
Parsing error: | |
ARR : 0x00000000 [0x4000082c] | |
Parsing error: | |
RCR : 0x00000000 [0x40000830] | |
Parsing error: | |
CCR1 : 0x00000000 [0x40000834] | |
Parsing error: | |
CCR2 : 0x00000000 [0x40000838] | |
Parsing error: | |
CCR3 : 0x00000000 [0x4000083c] | |
Parsing error: | |
CCR4 : 0x00000000 [0x40000840] | |
Parsing error: | |
BDTR : 0x00000000 [0x40000844] | |
Parsing error: | |
DCR : 0x00000000 [0x40000848] | |
Parsing error: | |
DMAR : 0x00000000 [0x4000084c] | |
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>>>> adc1 | |
ADC1 settings | |
SR : 0x00000012 [0x40012400] | |
CR1 : 0x00000000 [0x40012404] | |
CR2 : 0x009e0001 [0x40012408] | |
SMPR1 : 0x00000000 [0x4001240c] | |
SMPR2 : 0x36c00000 [0x40012410] | |
JOFR1 : 0x00000000 [0x40012414] | |
JOFR2 : 0x00000000 [0x40012418] | |
JOFR3 : 0x00000000 [0x4001241c] | |
JOFR4 : 0x00000000 [0x40012420] | |
HTR : 0x00000fff [0x40012424] | |
LTR : 0x00000000 [0x40012428] | |
SQR1 : 0x00000000 [0x4001242c] | |
SQR2 : 0x00000000 [0x40012430] | |
SQR3 : 0x00000008 [0x40012434] | |
JSQR : 0x00000000 [0x40012438] | |
JDR1 : 0x00000000 [0x4001243c] | |
JDR2 : 0x00000000 [0x40012440] | |
JDR3 : 0x00000000 [0x40012444] | |
JDR4 : 0x00000000 [0x40012448] | |
DR : 0x000005a7 [0x4001244c] | |
>>>> afio | |
AFIO settings | |
EVCR : 0x00000000 [0x40010000] | |
MAPR : 0x02008000 [0x40010004] | |
EXTICR1 : 0x00000000 [0x40010008] | |
EXTICR2 : 0x00000011 [0x4001000c] | |
EXTICR3 : 0x00000011 [0x40010010] | |
EXTICR4 : 0x00000000 [0x40010014] | |
MAPR2 : 0x00000000 [0x40010018] | |
>>>> dac | |
DAC settings | |
CR : 0x00030003 [0x40007400] | |
SWTRIGR : 0x00000000 [0x40007404] | |
DHR12R1 : 0x000002fa [0x40007408] | |
DHR12L1 : 0x00002fa0 [0x4000740c] | |
DHR8R1 : 0x0000002f [0x40007410] | |
DHR12R2 : 0x00000309 [0x40007414] | |
DHR12L2 : 0x00003090 [0x40007418] | |
DHR8R2 : 0x00000030 [0x4000741c] | |
DHR12RD : 0x030902fa [0x40007420] | |
DHR12LD : 0x30902fa0 [0x40007424] | |
DHR8RD : 0x0000302f [0x40007428] | |
DOR1 : 0x000002fa [0x4000742c] | |
DOR2 : 0x00000309 [0x40007430] | |
SR : 0x00000000 [0x40007434] | |
>>>> dma | |
DMA settings | |
ISR : 0x00000000 [0x40020000] | |
IFCR : 0x00000000 [0x40020004] | |
CCR1 : 0x00000000 [0x40020008] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR1 : 0x00000000 [0x40020010] | |
CMAR1 : 0x00000000 [0x40020014] | |
CCR2 : 0x00000000 [0x4002001c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR2 : 0x00000000 [0x40020024] | |
CMAR2 : 0x00000000 [0x40020028] | |
CCR3 : 0x00000000 [0x40020030] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR3 : 0x00000000 [0x40020038] | |
CMAR3 : 0x00000000 [0x4002003c] | |
CCR4 : 0x00000000 [0x40020044] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR4 : 0x00000000 [0x4002004c] | |
CMAR4 : 0x00000000 [0x40020050] | |
CCR5 : 0x00000000 [0x40020058] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR5 : 0x00000000 [0x40020060] | |
CMAR5 : 0x00000000 [0x40020064] | |
CCR6 : 0x00000000 [0x4002006c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR6 : 0x00000000 [0x40020074] | |
CMAR6 : 0x00000000 [0x40020078] | |
CCR7 : 0x00000000 [0x40020080] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR7 : 0x00000000 [0x40020088] | |
>>>> exti | |
EXTI settings | |
IMR : 0x0000033e [0x40010400] | |
EMR : 0x00000000 [0x40010404] | |
RTSR : 0x00000300 [0x40010408] | |
FTSR : 0x0000033e [0x4001040c] | |
SWIER : 0x00000000 [0x40010410] | |
PR : 0x00000000 [0x40010414] | |
>>>> gpio | |
// PA0 O 1 OD (50 Mhz) U7 | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO0); | |
// PA1 I 1 PuPd M2 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO1); | |
gpio_set(GPIOA, GPIO1); | |
// PA2 I 1 PuPd SEL button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO2); | |
gpio_set(GPIOA, GPIO2); | |
// PA3 I 1 PuPd M1 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO3); | |
gpio_set(GPIOA, GPIO3); | |
// PA4 I 0 An DAC1_OUT TL594.2 (1IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PA5 I 0 An DAC2_OUT TL594.15 (2IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PA6 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PA7 I 0 An ADC1_IN7 R30-U2.7:V_OUT-B (measures Vout) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PA8 O 1 PP (50 Mhz) TFT.7 (not used by TFT) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); | |
// PA9 O 0 AF-PP (50 Mhz) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO9); | |
// PA10 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO10); | |
gpio_clear(GPIOA, GPIO10); | |
// PA11 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PA12 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PA13 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO13); | |
gpio_clear(GPIOA, GPIO13); | |
// PA14 I 1 PuPd SWDCLK | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); | |
gpio_set(GPIOA, GPIO14); | |
// PA15 O 1 OD (50 Mhz) R41-TL594.16 (2IN+) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO15); | |
// PB0 I 0 An ADC1_IN8 R7/R2-R14-D4 (measures Vin) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PB1 I 0 An ADC1_IN9 R33-U2.1:V_OUT-A (measures Iout) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PB2 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PB3 O 1 OD (50 Mhz) R11-R17-R25-U2.5 (V_inB+) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO3); | |
// PB4 I 1 PuPd PWR button | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO4); | |
gpio_set(GPIOB, GPIO4); | |
// PB5 I 1 PuPd Rotary press | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO5); | |
gpio_set(GPIOB, GPIO5); | |
// PB6 I 1 Flt NC? | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PB7 O 0 AF-PP (50 Mhz) TIM4_CH2 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7); | |
// PB8 I 0 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO8); | |
gpio_clear(GPIOB, GPIO8); | |
// PB9 I 0 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO9); | |
gpio_clear(GPIOB, GPIO9); | |
// PB10 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PB11 O 0 PP (50 Mhz) nPwrEnable R29-TFT.2 (TFT_VCC) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); | |
// PB12 O 1 PP (50 Mhz) SPI2_NSS TFT_RESET | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); | |
// PB13 O 1 AF-PP (50 Mhz) SPI2_SCK | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13); | |
// PB14 O 1 PP (50 Mhz) SPI2_MISO TFT_A0 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); | |
// PB15 O 1 AF-PP (50 Mhz) SPI2_MOSI | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO15); | |
// PC0 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PC1 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); | |
// PC2 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PC3 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PC4 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PC5 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PC6 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PC7 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PC8 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PC9 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PC10 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PC11 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PC12 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PC13 O 0 PP (50 Mhz) | |
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); | |
// PC14 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PC15 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
// PD0 I 1 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PD1 O 1 PP (50 Mhz) U7 | |
gpio_set_mode(GPIOD, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); | |
// PD2 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PD3 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PD4 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PD5 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PD6 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PD7 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PD8 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PD9 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PD10 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PD11 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PD12 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PD13 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO13); | |
// PD14 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PD15 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
>>>> gpioa | |
GPIOA settings | |
CRL : 0x00008887 [0x40010800] | |
CRH : 0x788448b3 [0x40010804] | |
IDR : 0x00005b0f [0x40010808] | |
ODR : 0x0000a14f [0x4001080c] | |
BSRR : 0x00000000 [0x40010810] | |
BRR : 0x00000000 [0x40010814] | |
LCKR : 0x00000000 [0x40010818] | |
>>>> gpiob | |
GPIOB settings | |
CRL : 0xb4887400 [0x40010c00] | |
CRH : 0xb3b33488 [0x40010c04] | |
IDR : 0x000074f4 [0x40010c08] | |
ODR : 0x0000f338 [0x40010c0c] | |
BSRR : 0x00000000 [0x40010c10] | |
BRR : 0x00000000 [0x40010c14] | |
LCKR : 0x00000000 [0x40010c18] | |
>>>> gpioc | |
GPIOC settings | |
CRL : 0x44444444 [0x40011000] | |
CRH : 0x44344444 [0x40011004] | |
IDR : 0x0000c000 [0x40011008] | |
ODR : 0x00000000 [0x4001100c] | |
BSRR : 0x00000000 [0x40011010] | |
BRR : 0x00000000 [0x40011014] | |
LCKR : 0x00000000 [0x40011018] | |
>>>> gpiod | |
GPIOD settings | |
CRL : 0x44444434 [0x40011400] | |
CRH : 0x44444444 [0x40011404] | |
IDR : 0x00000003 [0x40011408] | |
ODR : 0x00000002 [0x4001140c] | |
BSRR : 0x00000000 [0x40011410] | |
BRR : 0x00000000 [0x40011414] | |
LCKR : 0x00000000 [0x40011418] | |
>>>> rcc | |
RCC settings | |
CR : 0x03004883 [0x40021000] | |
CFGR : 0x0410000a [0x40021004] | |
CIR : 0x00000000 [0x40021008] | |
APB2RSTR : 0x00000000 [0x4002100c] | |
APB1RSTR : 0x00000000 [0x40021010] | |
AHBENR : 0x00000014 [0x40021014] | |
APB2ENR : 0x0000423d [0x40021018] | |
APB1ENR : 0x20004006 [0x4002101c] | |
BDCR : 0x00000000 [0x40021020] | |
CSR : 0x0c000000 [0x40021024] | |
CFGR2 : 0x00000000 [0x4002102c] | |
>>>> spi1 | |
SPI1 settings | |
CR2 : 0x00000000 [0x40013000] | |
CR1 : 0x00000000 [0x40013004] | |
SR : 0x00000000 [0x40013008] | |
DR : 0x00000000 [0x4001300c] | |
CRCPR : 0x00000000 [0x40013010] | |
RXCRCR : 0x00000000 [0x40013014] | |
TXCRCR : 0x00000000 [0x40013018] | |
>>>> spi2 | |
SPI2 settings | |
CR2 : 0x00000347 [0x40003800] | |
CR1 : 0x00000000 [0x40003804] | |
SR : 0x00000002 [0x40003808] | |
DR : 0x000000ff [0x4000380c] | |
CRCPR : 0x00000007 [0x40003810] | |
RXCRCR : 0x00000000 [0x40003814] | |
TXCRCR : 0x00000000 [0x40003818] | |
>>>> tim4 | |
TIM4 settings | |
CR1 : 0x00000081 [0x40000800] | |
CR2 : 0x00000000 [0x40000804] | |
SMC : 0x00000000 [0x40000808] | |
DIER : 0x00000000 [0x4000080c] | |
SR : 0x0000001f [0x40000810] | |
EGR : 0x00000000 [0x40000814] | |
CCMR1 : 0x00006800 [0x40000818] | |
CCMR2 : 0x00000000 [0x4000081c] | |
CCER : 0x00000010 [0x40000820] | |
CNT : 0x0000472d [0x40000824] | |
PSC : 0x00000000 [0x40000828] | |
ARR : 0x00005dbf [0x4000082c] | |
RCR : 0x00000000 [0x40000830] | |
CCR1 : 0x00000000 [0x40000834] | |
CCR2 : 0x00005dc0 [0x40000838] | |
CCR3 : 0x00000000 [0x4000083c] | |
CCR4 : 0x00000000 [0x40000840] | |
BDTR : 0x00000000 [0x40000844] | |
DCR : 0x00000000 [0x40000848] | |
DMAR : 0x00000081 [0x4000084c] | |
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>>>> adc1 | |
ADC1 settings | |
SR : 0x00000010 [0x40012400] | |
CR1 : 0x00000000 [0x40012404] | |
CR2 : 0x009e0001 [0x40012408] | |
SMPR1 : 0x00000000 [0x4001240c] | |
SMPR2 : 0x36c00000 [0x40012410] | |
JOFR1 : 0x00000000 [0x40012414] | |
JOFR2 : 0x00000000 [0x40012418] | |
JOFR3 : 0x00000000 [0x4001241c] | |
JOFR4 : 0x00000000 [0x40012420] | |
HTR : 0x00000fff [0x40012424] | |
LTR : 0x00000000 [0x40012428] | |
SQR1 : 0x00000000 [0x4001242c] | |
SQR2 : 0x00000000 [0x40012430] | |
SQR3 : 0x00000008 [0x40012434] | |
JSQR : 0x00000000 [0x40012438] | |
JDR1 : 0x00000000 [0x4001243c] | |
JDR2 : 0x00000000 [0x40012440] | |
JDR3 : 0x00000000 [0x40012444] | |
JDR4 : 0x00000000 [0x40012448] | |
DR : 0x000005a2 [0x4001244c] | |
>>>> afio | |
AFIO settings | |
EVCR : 0x00000000 [0x40010000] | |
MAPR : 0x02008000 [0x40010004] | |
EXTICR1 : 0x00000000 [0x40010008] | |
EXTICR2 : 0x00000011 [0x4001000c] | |
EXTICR3 : 0x00000011 [0x40010010] | |
EXTICR4 : 0x00000000 [0x40010014] | |
MAPR2 : 0x00000000 [0x40010018] | |
>>>> dac | |
DAC settings | |
CR : 0x00030003 [0x40007400] | |
SWTRIGR : 0x00000000 [0x40007404] | |
DHR12R1 : 0x00000000 [0x40007408] | |
DHR12L1 : 0x00000000 [0x4000740c] | |
DHR8R1 : 0x00000000 [0x40007410] | |
DHR12R2 : 0x00000000 [0x40007414] | |
DHR12L2 : 0x00000000 [0x40007418] | |
DHR8R2 : 0x00000000 [0x4000741c] | |
DHR12RD : 0x00000000 [0x40007420] | |
DHR12LD : 0x00000000 [0x40007424] | |
DHR8RD : 0x00000000 [0x40007428] | |
DOR1 : 0x00000000 [0x4000742c] | |
DOR2 : 0x00000000 [0x40007430] | |
SR : 0x00000000 [0x40007434] | |
>>>> dma | |
DMA settings | |
ISR : 0x00000000 [0x40020000] | |
IFCR : 0x00000000 [0x40020004] | |
CCR1 : 0x00000000 [0x40020008] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR1 : 0x00000000 [0x40020010] | |
CMAR1 : 0x00000000 [0x40020014] | |
CCR2 : 0x00000000 [0x4002001c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR2 : 0x00000000 [0x40020024] | |
CMAR2 : 0x00000000 [0x40020028] | |
CCR3 : 0x00000000 [0x40020030] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR3 : 0x00000000 [0x40020038] | |
CMAR3 : 0x00000000 [0x4002003c] | |
CCR4 : 0x00000000 [0x40020044] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR4 : 0x00000000 [0x4002004c] | |
CMAR4 : 0x00000000 [0x40020050] | |
CCR5 : 0x00000000 [0x40020058] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR5 : 0x00000000 [0x40020060] | |
CMAR5 : 0x00000000 [0x40020064] | |
CCR6 : 0x00000000 [0x4002006c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR6 : 0x00000000 [0x40020074] | |
CMAR6 : 0x00000000 [0x40020078] | |
CCR7 : 0x00000000 [0x40020080] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR7 : 0x00000000 [0x40020088] | |
>>>> exti | |
EXTI settings | |
IMR : 0x0000033e [0x40010400] | |
EMR : 0x00000000 [0x40010404] | |
RTSR : 0x00000300 [0x40010408] | |
FTSR : 0x0000033e [0x4001040c] | |
SWIER : 0x00000000 [0x40010410] | |
PR : 0x00000000 [0x40010414] | |
>>>> gpio | |
// PA0 O 1 OD (50 Mhz) U7 | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO0); | |
// PA1 I 1 PuPd M2 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO1); | |
gpio_set(GPIOA, GPIO1); | |
// PA2 I 1 PuPd SEL button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO2); | |
gpio_set(GPIOA, GPIO2); | |
// PA3 I 1 PuPd M1 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO3); | |
gpio_set(GPIOA, GPIO3); | |
// PA4 I 0 An DAC1_OUT TL594.2 (1IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PA5 I 0 An DAC2_OUT TL594.15 (2IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PA6 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PA7 I 0 An ADC1_IN7 R30-U2.7:V_OUT-B (measures Vout) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PA8 O 0 PP (50 Mhz) TFT.7 (not used by TFT) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); | |
// PA9 O 0 AF-PP (50 Mhz) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO9); | |
// PA10 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO10); | |
gpio_clear(GPIOA, GPIO10); | |
// PA11 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PA12 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PA13 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO13); | |
gpio_clear(GPIOA, GPIO13); | |
// PA14 I 1 PuPd SWDCLK | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); | |
gpio_set(GPIOA, GPIO14); | |
// PA15 O 1 OD (50 Mhz) R41-TL594.16 (2IN+) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO15); | |
// PB0 I 0 An ADC1_IN8 R7/R2-R14-D4 (measures Vin) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PB1 I 0 An ADC1_IN9 R33-U2.1:V_OUT-A (measures Iout) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PB2 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PB3 O 1 OD (50 Mhz) R11-R17-R25-U2.5 (V_inB+) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO3); | |
// PB4 I 1 PuPd PWR button | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO4); | |
gpio_set(GPIOB, GPIO4); | |
// PB5 I 1 PuPd Rotary press | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO5); | |
gpio_set(GPIOB, GPIO5); | |
// PB6 I 1 Flt NC? | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PB7 O 0 AF-PP (50 Mhz) TIM4_CH2 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7); | |
// PB8 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO8); | |
gpio_set(GPIOB, GPIO8); | |
// PB9 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO9); | |
gpio_set(GPIOB, GPIO9); | |
// PB10 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PB11 O 0 PP (50 Mhz) nPwrEnable R29-TFT.2 (TFT_VCC) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); | |
// PB12 O 1 PP (50 Mhz) SPI2_NSS TFT_RESET | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); | |
// PB13 O 1 AF-PP (50 Mhz) SPI2_SCK | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13); | |
// PB14 O 1 PP (50 Mhz) SPI2_MISO TFT_A0 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); | |
// PB15 O 1 AF-PP (50 Mhz) SPI2_MOSI | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO15); | |
// PC0 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PC1 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); | |
// PC2 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PC3 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PC4 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PC5 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PC6 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PC7 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PC8 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PC9 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PC10 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PC11 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PC12 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PC13 O 1 PP (50 Mhz) | |
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); | |
// PC14 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PC15 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
// PD0 I 1 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PD1 O 1 PP (50 Mhz) U7 | |
gpio_set_mode(GPIOD, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); | |
// PD2 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PD3 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PD4 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PD5 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PD6 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PD7 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PD8 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PD9 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PD10 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PD11 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PD12 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PD13 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO13); | |
// PD14 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PD15 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
>>>> gpioa | |
GPIOA settings | |
CRL : 0x00008887 [0x40010800] | |
CRH : 0x788448b3 [0x40010804] | |
IDR : 0x00005a0f [0x40010808] | |
ODR : 0x0000a04f [0x4001080c] | |
BSRR : 0x00000000 [0x40010810] | |
BRR : 0x00000000 [0x40010814] | |
LCKR : 0x00000000 [0x40010818] | |
>>>> gpiob | |
GPIOB settings | |
CRL : 0xb4887400 [0x40010c00] | |
CRH : 0xb3b33488 [0x40010c04] | |
IDR : 0x0000f7f4 [0x40010c08] | |
ODR : 0x0000f338 [0x40010c0c] | |
BSRR : 0x00000000 [0x40010c10] | |
BRR : 0x00000000 [0x40010c14] | |
LCKR : 0x00000000 [0x40010c18] | |
>>>> gpioc | |
GPIOC settings | |
CRL : 0x44444444 [0x40011000] | |
CRH : 0x44344444 [0x40011004] | |
IDR : 0x0000e000 [0x40011008] | |
ODR : 0x00002000 [0x4001100c] | |
BSRR : 0x00000000 [0x40011010] | |
BRR : 0x00000000 [0x40011014] | |
LCKR : 0x00000000 [0x40011018] | |
>>>> gpiod | |
GPIOD settings | |
CRL : 0x44444434 [0x40011400] | |
CRH : 0x44444444 [0x40011404] | |
IDR : 0x00000003 [0x40011408] | |
ODR : 0x00000002 [0x4001140c] | |
BSRR : 0x00000000 [0x40011410] | |
BRR : 0x00000000 [0x40011414] | |
LCKR : 0x00000000 [0x40011418] | |
>>>> rcc | |
RCC settings | |
CR : 0x03004883 [0x40021000] | |
CFGR : 0x0410000a [0x40021004] | |
CIR : 0x00000000 [0x40021008] | |
APB2RSTR : 0x00000000 [0x4002100c] | |
APB1RSTR : 0x00000000 [0x40021010] | |
AHBENR : 0x00000014 [0x40021014] | |
APB2ENR : 0x0000423d [0x40021018] | |
APB1ENR : 0x20004006 [0x4002101c] | |
BDCR : 0x00000000 [0x40021020] | |
CSR : 0x0c000000 [0x40021024] | |
CFGR2 : 0x00000000 [0x4002102c] | |
>>>> spi1 | |
SPI1 settings | |
CR2 : 0x00000000 [0x40013000] | |
CR1 : 0x00000000 [0x40013004] | |
SR : 0x00000000 [0x40013008] | |
DR : 0x00000000 [0x4001300c] | |
CRCPR : 0x00000000 [0x40013010] | |
RXCRCR : 0x00000000 [0x40013014] | |
TXCRCR : 0x00000000 [0x40013018] | |
>>>> spi2 | |
SPI2 settings | |
CR2 : 0x00000347 [0x40003800] | |
CR1 : 0x00000000 [0x40003804] | |
SR : 0x00000002 [0x40003808] | |
DR : 0x000000ff [0x4000380c] | |
CRCPR : 0x00000007 [0x40003810] | |
RXCRCR : 0x00000000 [0x40003814] | |
TXCRCR : 0x00000000 [0x40003818] | |
>>>> tim4 | |
TIM4 settings | |
CR1 : 0x00000081 [0x40000800] | |
CR2 : 0x00000000 [0x40000804] | |
SMC : 0x00000000 [0x40000808] | |
DIER : 0x00000000 [0x4000080c] | |
SR : 0x0000001f [0x40000810] | |
EGR : 0x00000000 [0x40000814] | |
CCMR1 : 0x00006800 [0x40000818] | |
CCMR2 : 0x00000000 [0x4000081c] | |
CCER : 0x00000010 [0x40000820] | |
CNT : 0x00004d51 [0x40000824] | |
PSC : 0x00000000 [0x40000828] | |
ARR : 0x00005dbf [0x4000082c] | |
RCR : 0x00000000 [0x40000830] | |
CCR1 : 0x00000000 [0x40000834] | |
CCR2 : 0x00005dc0 [0x40000838] | |
CCR3 : 0x00000000 [0x4000083c] | |
CCR4 : 0x00000000 [0x40000840] | |
BDTR : 0x00000000 [0x40000844] | |
DCR : 0x00000000 [0x40000848] | |
DMAR : 0x00000081 [0x4000084c] | |
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>>>> adc1 | |
ADC1 settings | |
SR : 0x00000010 [0x40012400] | |
CR1 : 0x00000000 [0x40012404] | |
CR2 : 0x009e0001 [0x40012408] | |
SMPR1 : 0x00000000 [0x4001240c] | |
SMPR2 : 0x36c00000 [0x40012410] | |
JOFR1 : 0x00000000 [0x40012414] | |
JOFR2 : 0x00000000 [0x40012418] | |
JOFR3 : 0x00000000 [0x4001241c] | |
JOFR4 : 0x00000000 [0x40012420] | |
HTR : 0x00000fff [0x40012424] | |
LTR : 0x00000000 [0x40012428] | |
SQR1 : 0x00000000 [0x4001242c] | |
SQR2 : 0x00000000 [0x40012430] | |
SQR3 : 0x00000008 [0x40012434] | |
JSQR : 0x00000000 [0x40012438] | |
JDR1 : 0x00000000 [0x4001243c] | |
JDR2 : 0x00000000 [0x40012440] | |
JDR3 : 0x00000000 [0x40012444] | |
JDR4 : 0x00000000 [0x40012448] | |
DR : 0x000005a5 [0x4001244c] | |
>>>> afio | |
AFIO settings | |
EVCR : 0x00000000 [0x40010000] | |
MAPR : 0x02008000 [0x40010004] | |
EXTICR1 : 0x00000000 [0x40010008] | |
EXTICR2 : 0x00000011 [0x4001000c] | |
EXTICR3 : 0x00000011 [0x40010010] | |
EXTICR4 : 0x00000000 [0x40010014] | |
MAPR2 : 0x00000000 [0x40010018] | |
>>>> dac | |
DAC settings | |
CR : 0x00030003 [0x40007400] | |
SWTRIGR : 0x00000000 [0x40007404] | |
DHR12R1 : 0x00000474 [0x40007408] | |
DHR12L1 : 0x00004740 [0x4000740c] | |
DHR8R1 : 0x00000047 [0x40007410] | |
DHR12R2 : 0x00000309 [0x40007414] | |
DHR12L2 : 0x00003090 [0x40007418] | |
DHR8R2 : 0x00000030 [0x4000741c] | |
DHR12RD : 0x03090474 [0x40007420] | |
DHR12LD : 0x30904740 [0x40007424] | |
DHR8RD : 0x00003047 [0x40007428] | |
DOR1 : 0x00000474 [0x4000742c] | |
DOR2 : 0x00000309 [0x40007430] | |
SR : 0x00000000 [0x40007434] | |
>>>> dma | |
DMA settings | |
ISR : 0x00000000 [0x40020000] | |
IFCR : 0x00000000 [0x40020004] | |
CCR1 : 0x00000000 [0x40020008] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR1 : 0x00000000 [0x40020010] | |
CMAR1 : 0x00000000 [0x40020014] | |
CCR2 : 0x00000000 [0x4002001c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR2 : 0x00000000 [0x40020024] | |
CMAR2 : 0x00000000 [0x40020028] | |
CCR3 : 0x00000000 [0x40020030] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR3 : 0x00000000 [0x40020038] | |
CMAR3 : 0x00000000 [0x4002003c] | |
CCR4 : 0x00000000 [0x40020044] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR4 : 0x00000000 [0x4002004c] | |
CMAR4 : 0x00000000 [0x40020050] | |
CCR5 : 0x00000000 [0x40020058] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR5 : 0x00000000 [0x40020060] | |
CMAR5 : 0x00000000 [0x40020064] | |
CCR6 : 0x00000000 [0x4002006c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR6 : 0x00000000 [0x40020074] | |
CMAR6 : 0x00000000 [0x40020078] | |
CCR7 : 0x00000000 [0x40020080] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR7 : 0x00000000 [0x40020088] | |
>>>> exti | |
EXTI settings | |
IMR : 0x0000033e [0x40010400] | |
EMR : 0x00000000 [0x40010404] | |
RTSR : 0x00000300 [0x40010408] | |
FTSR : 0x0000033e [0x4001040c] | |
SWIER : 0x00000000 [0x40010410] | |
PR : 0x00000000 [0x40010414] | |
>>>> gpio | |
// PA0 O 1 OD (50 Mhz) U7 | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO0); | |
// PA1 I 1 PuPd M2 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO1); | |
gpio_set(GPIOA, GPIO1); | |
// PA2 I 1 PuPd SEL button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO2); | |
gpio_set(GPIOA, GPIO2); | |
// PA3 I 1 PuPd M1 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO3); | |
gpio_set(GPIOA, GPIO3); | |
// PA4 I 0 An DAC1_OUT TL594.2 (1IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PA5 I 0 An DAC2_OUT TL594.15 (2IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PA6 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PA7 I 0 An ADC1_IN7 R30-U2.7:V_OUT-B (measures Vout) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PA8 O 0 PP (50 Mhz) TFT.7 (not used by TFT) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); | |
// PA9 O 0 AF-PP (50 Mhz) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO9); | |
// PA10 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO10); | |
gpio_clear(GPIOA, GPIO10); | |
// PA11 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PA12 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PA13 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO13); | |
gpio_clear(GPIOA, GPIO13); | |
// PA14 I 1 PuPd SWDCLK | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); | |
gpio_set(GPIOA, GPIO14); | |
// PA15 O 1 OD (50 Mhz) R41-TL594.16 (2IN+) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO15); | |
// PB0 I 0 An ADC1_IN8 R7/R2-R14-D4 (measures Vin) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PB1 I 0 An ADC1_IN9 R33-U2.1:V_OUT-A (measures Iout) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PB2 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PB3 O 1 OD (50 Mhz) R11-R17-R25-U2.5 (V_inB+) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO3); | |
// PB4 I 1 PuPd PWR button | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO4); | |
gpio_set(GPIOB, GPIO4); | |
// PB5 I 1 PuPd Rotary press | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO5); | |
gpio_set(GPIOB, GPIO5); | |
// PB6 I 1 Flt NC? | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PB7 O 0 AF-PP (50 Mhz) TIM4_CH2 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7); | |
// PB8 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO8); | |
gpio_set(GPIOB, GPIO8); | |
// PB9 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO9); | |
gpio_set(GPIOB, GPIO9); | |
// PB10 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PB11 O 0 PP (50 Mhz) nPwrEnable R29-TFT.2 (TFT_VCC) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); | |
// PB12 O 1 PP (50 Mhz) SPI2_NSS TFT_RESET | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); | |
// PB13 O 1 AF-PP (50 Mhz) SPI2_SCK | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13); | |
// PB14 O 1 PP (50 Mhz) SPI2_MISO TFT_A0 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); | |
// PB15 O 1 AF-PP (50 Mhz) SPI2_MOSI | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO15); | |
// PC0 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PC1 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); | |
// PC2 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PC3 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PC4 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PC5 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PC6 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PC7 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PC8 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PC9 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PC10 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PC11 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PC12 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PC13 O 0 PP (50 Mhz) | |
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); | |
// PC14 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PC15 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
// PD0 I 1 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PD1 O 1 PP (50 Mhz) U7 | |
gpio_set_mode(GPIOD, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); | |
// PD2 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PD3 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PD4 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PD5 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PD6 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PD7 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PD8 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PD9 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PD10 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PD11 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PD12 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PD13 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO13); | |
// PD14 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PD15 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
>>>> gpioa | |
GPIOA settings | |
CRL : 0x00008887 [0x40010800] | |
CRH : 0x788448b3 [0x40010804] | |
IDR : 0x00005a0f [0x40010808] | |
ODR : 0x0000a04f [0x4001080c] | |
BSRR : 0x00000000 [0x40010810] | |
BRR : 0x00000000 [0x40010814] | |
LCKR : 0x00000000 [0x40010818] | |
>>>> gpiob | |
GPIOB settings | |
CRL : 0xb4887400 [0x40010c00] | |
CRH : 0xb3b33488 [0x40010c04] | |
IDR : 0x000077f4 [0x40010c08] | |
ODR : 0x0000f338 [0x40010c0c] | |
BSRR : 0x00000000 [0x40010c10] | |
BRR : 0x00000000 [0x40010c14] | |
LCKR : 0x00000000 [0x40010c18] | |
>>>> gpioc | |
GPIOC settings | |
CRL : 0x44444444 [0x40011000] | |
CRH : 0x44344444 [0x40011004] | |
IDR : 0x0000c000 [0x40011008] | |
ODR : 0x00000000 [0x4001100c] | |
BSRR : 0x00000000 [0x40011010] | |
BRR : 0x00000000 [0x40011014] | |
LCKR : 0x00000000 [0x40011018] | |
>>>> gpiod | |
GPIOD settings | |
CRL : 0x44444434 [0x40011400] | |
CRH : 0x44444444 [0x40011404] | |
IDR : 0x00000003 [0x40011408] | |
ODR : 0x00000002 [0x4001140c] | |
BSRR : 0x00000000 [0x40011410] | |
BRR : 0x00000000 [0x40011414] | |
LCKR : 0x00000000 [0x40011418] | |
>>>> rcc | |
RCC settings | |
CR : 0x03004883 [0x40021000] | |
CFGR : 0x0410000a [0x40021004] | |
CIR : 0x00000000 [0x40021008] | |
APB2RSTR : 0x00000000 [0x4002100c] | |
APB1RSTR : 0x00000000 [0x40021010] | |
AHBENR : 0x00000014 [0x40021014] | |
APB2ENR : 0x0000423d [0x40021018] | |
APB1ENR : 0x20004006 [0x4002101c] | |
BDCR : 0x00000000 [0x40021020] | |
CSR : 0x0c000000 [0x40021024] | |
CFGR2 : 0x00000000 [0x4002102c] | |
>>>> spi1 | |
SPI1 settings | |
CR2 : 0x00000000 [0x40013000] | |
CR1 : 0x00000000 [0x40013004] | |
SR : 0x00000000 [0x40013008] | |
DR : 0x00000000 [0x4001300c] | |
CRCPR : 0x00000000 [0x40013010] | |
RXCRCR : 0x00000000 [0x40013014] | |
TXCRCR : 0x00000000 [0x40013018] | |
>>>> spi2 | |
SPI2 settings | |
CR2 : 0x00000347 [0x40003800] | |
CR1 : 0x00000000 [0x40003804] | |
SR : 0x00000003 [0x40003808] | |
DR : 0x000000ff [0x4000380c] | |
CRCPR : 0x00000007 [0x40003810] | |
RXCRCR : 0x00000000 [0x40003814] | |
TXCRCR : 0x00000000 [0x40003818] | |
>>>> tim4 | |
TIM4 settings | |
CR1 : 0x00000081 [0x40000800] | |
CR2 : 0x00000000 [0x40000804] | |
SMC : 0x00000000 [0x40000808] | |
DIER : 0x00000000 [0x4000080c] | |
SR : 0x0000001f [0x40000810] | |
EGR : 0x00000000 [0x40000814] | |
CCMR1 : 0x00006800 [0x40000818] | |
CCMR2 : 0x00000000 [0x4000081c] | |
CCER : 0x00000010 [0x40000820] | |
CNT : 0x000021b4 [0x40000824] | |
PSC : 0x00000000 [0x40000828] | |
ARR : 0x00005dbf [0x4000082c] | |
RCR : 0x00000000 [0x40000830] | |
CCR1 : 0x00000000 [0x40000834] | |
CCR2 : 0x00005dc0 [0x40000838] | |
CCR3 : 0x00000000 [0x4000083c] | |
CCR4 : 0x00000000 [0x40000840] | |
BDTR : 0x00000000 [0x40000844] | |
DCR : 0x00000000 [0x40000848] | |
DMAR : 0x00000081 [0x4000084c] | |
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>>>> adc1 | |
ADC1 settings | |
SR : 0x00000012 [0x40012400] | |
CR1 : 0x00000000 [0x40012404] | |
CR2 : 0x009e0001 [0x40012408] | |
SMPR1 : 0x00000000 [0x4001240c] | |
SMPR2 : 0x36c00000 [0x40012410] | |
JOFR1 : 0x00000000 [0x40012414] | |
JOFR2 : 0x00000000 [0x40012418] | |
JOFR3 : 0x00000000 [0x4001241c] | |
JOFR4 : 0x00000000 [0x40012420] | |
HTR : 0x00000fff [0x40012424] | |
LTR : 0x00000000 [0x40012428] | |
SQR1 : 0x00000000 [0x4001242c] | |
SQR2 : 0x00000000 [0x40012430] | |
SQR3 : 0x00000009 [0x40012434] | |
JSQR : 0x00000000 [0x40012438] | |
JDR1 : 0x00000000 [0x4001243c] | |
JDR2 : 0x00000000 [0x40012440] | |
JDR3 : 0x00000000 [0x40012444] | |
JDR4 : 0x00000000 [0x40012448] | |
DR : 0x00000010 [0x4001244c] | |
>>>> afio | |
AFIO settings | |
EVCR : 0x00000000 [0x40010000] | |
MAPR : 0x02008000 [0x40010004] | |
EXTICR1 : 0x00000000 [0x40010008] | |
EXTICR2 : 0x00000011 [0x4001000c] | |
EXTICR3 : 0x00000011 [0x40010010] | |
EXTICR4 : 0x00000000 [0x40010014] | |
MAPR2 : 0x00000000 [0x40010018] | |
>>>> dac | |
DAC settings | |
CR : 0x00030003 [0x40007400] | |
SWTRIGR : 0x00000000 [0x40007404] | |
DHR12R1 : 0x00000000 [0x40007408] | |
DHR12L1 : 0x00000000 [0x4000740c] | |
DHR8R1 : 0x00000000 [0x40007410] | |
DHR12R2 : 0x00000000 [0x40007414] | |
DHR12L2 : 0x00000000 [0x40007418] | |
DHR8R2 : 0x00000000 [0x4000741c] | |
DHR12RD : 0x00000000 [0x40007420] | |
DHR12LD : 0x00000000 [0x40007424] | |
DHR8RD : 0x00000000 [0x40007428] | |
DOR1 : 0x00000000 [0x4000742c] | |
DOR2 : 0x00000000 [0x40007430] | |
SR : 0x00000000 [0x40007434] | |
>>>> dma | |
DMA settings | |
ISR : 0x00000000 [0x40020000] | |
IFCR : 0x00000000 [0x40020004] | |
CCR1 : 0x00000000 [0x40020008] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR1 : 0x00000000 [0x40020010] | |
CMAR1 : 0x00000000 [0x40020014] | |
CCR2 : 0x00000000 [0x4002001c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR2 : 0x00000000 [0x40020024] | |
CMAR2 : 0x00000000 [0x40020028] | |
CCR3 : 0x00000000 [0x40020030] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR3 : 0x00000000 [0x40020038] | |
CMAR3 : 0x00000000 [0x4002003c] | |
CCR4 : 0x00000000 [0x40020044] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR4 : 0x00000000 [0x4002004c] | |
CMAR4 : 0x00000000 [0x40020050] | |
CCR5 : 0x00000000 [0x40020058] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR5 : 0x00000000 [0x40020060] | |
CMAR5 : 0x00000000 [0x40020064] | |
CCR6 : 0x00000000 [0x4002006c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR6 : 0x00000000 [0x40020074] | |
CMAR6 : 0x00000000 [0x40020078] | |
CCR7 : 0x00000000 [0x40020080] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR7 : 0x00000000 [0x40020088] | |
>>>> exti | |
EXTI settings | |
IMR : 0x0000033e [0x40010400] | |
EMR : 0x00000000 [0x40010404] | |
RTSR : 0x00000300 [0x40010408] | |
FTSR : 0x0000033e [0x4001040c] | |
SWIER : 0x00000000 [0x40010410] | |
PR : 0x00000000 [0x40010414] | |
>>>> gpio | |
// PA0 O 1 OD (50 Mhz) U7 | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO0); | |
// PA1 I 1 PuPd M2 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO1); | |
gpio_set(GPIOA, GPIO1); | |
// PA2 I 1 PuPd SEL button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO2); | |
gpio_set(GPIOA, GPIO2); | |
// PA3 I 1 PuPd M1 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO3); | |
gpio_set(GPIOA, GPIO3); | |
// PA4 I 0 An DAC1_OUT TL594.2 (1IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PA5 I 0 An DAC2_OUT TL594.15 (2IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PA6 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PA7 I 0 An ADC1_IN7 R30-U2.7:V_OUT-B (measures Vout) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PA8 O 1 PP (50 Mhz) TFT.7 (not used by TFT) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); | |
// PA9 O 0 AF-PP (50 Mhz) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO9); | |
// PA10 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO10); | |
gpio_clear(GPIOA, GPIO10); | |
// PA11 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PA12 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PA13 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO13); | |
gpio_clear(GPIOA, GPIO13); | |
// PA14 I 1 PuPd SWDCLK | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); | |
gpio_set(GPIOA, GPIO14); | |
// PA15 O 1 OD (50 Mhz) R41-TL594.16 (2IN+) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO15); | |
// PB0 I 0 An ADC1_IN8 R7/R2-R14-D4 (measures Vin) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PB1 I 0 An ADC1_IN9 R33-U2.1:V_OUT-A (measures Iout) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PB2 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PB3 O 1 OD (50 Mhz) R11-R17-R25-U2.5 (V_inB+) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO3); | |
// PB4 I 1 PuPd PWR button | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO4); | |
gpio_set(GPIOB, GPIO4); | |
// PB5 I 1 PuPd Rotary press | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO5); | |
gpio_set(GPIOB, GPIO5); | |
// PB6 I 1 Flt NC? | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PB7 O 0 AF-PP (50 Mhz) TIM4_CH2 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7); | |
// PB8 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO8); | |
gpio_set(GPIOB, GPIO8); | |
// PB9 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO9); | |
gpio_set(GPIOB, GPIO9); | |
// PB10 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PB11 O 0 PP (50 Mhz) nPwrEnable R29-TFT.2 (TFT_VCC) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); | |
// PB12 O 1 PP (50 Mhz) SPI2_NSS TFT_RESET | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); | |
// PB13 O 1 AF-PP (50 Mhz) SPI2_SCK | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13); | |
// PB14 O 1 PP (50 Mhz) SPI2_MISO TFT_A0 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); | |
// PB15 O 1 AF-PP (50 Mhz) SPI2_MOSI | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO15); | |
// PC0 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PC1 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); | |
// PC2 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PC3 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PC4 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PC5 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PC6 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PC7 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PC8 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PC9 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PC10 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PC11 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PC12 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PC13 O 1 PP (50 Mhz) | |
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); | |
// PC14 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PC15 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
// PD0 I 1 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PD1 O 1 PP (50 Mhz) U7 | |
gpio_set_mode(GPIOD, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); | |
// PD2 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PD3 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PD4 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PD5 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PD6 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PD7 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PD8 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PD9 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PD10 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PD11 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PD12 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PD13 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO13); | |
// PD14 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PD15 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
>>>> gpioa | |
GPIOA settings | |
CRL : 0x00008887 [0x40010800] | |
CRH : 0x788448b3 [0x40010804] | |
IDR : 0x00005b0f [0x40010808] | |
ODR : 0x0000a14f [0x4001080c] | |
BSRR : 0x00000000 [0x40010810] | |
BRR : 0x00000000 [0x40010814] | |
LCKR : 0x00000000 [0x40010818] | |
>>>> gpiob | |
GPIOB settings | |
CRL : 0xb4887400 [0x40010c00] | |
CRH : 0xb3b33488 [0x40010c04] | |
IDR : 0x000077f4 [0x40010c08] | |
ODR : 0x0000f338 [0x40010c0c] | |
BSRR : 0x00000000 [0x40010c10] | |
BRR : 0x00000000 [0x40010c14] | |
LCKR : 0x00000000 [0x40010c18] | |
>>>> gpioc | |
GPIOC settings | |
CRL : 0x44444444 [0x40011000] | |
CRH : 0x44344444 [0x40011004] | |
IDR : 0x0000e000 [0x40011008] | |
ODR : 0x00002000 [0x4001100c] | |
BSRR : 0x00000000 [0x40011010] | |
BRR : 0x00000000 [0x40011014] | |
LCKR : 0x00000000 [0x40011018] | |
>>>> gpiod | |
GPIOD settings | |
CRL : 0x44444434 [0x40011400] | |
CRH : 0x44444444 [0x40011404] | |
IDR : 0x00000003 [0x40011408] | |
ODR : 0x00000002 [0x4001140c] | |
BSRR : 0x00000000 [0x40011410] | |
BRR : 0x00000000 [0x40011414] | |
LCKR : 0x00000000 [0x40011418] | |
>>>> rcc | |
RCC settings | |
CR : 0x03004883 [0x40021000] | |
CFGR : 0x0410000a [0x40021004] | |
CIR : 0x00000000 [0x40021008] | |
APB2RSTR : 0x00000000 [0x4002100c] | |
APB1RSTR : 0x00000000 [0x40021010] | |
AHBENR : 0x00000014 [0x40021014] | |
APB2ENR : 0x0000423d [0x40021018] | |
APB1ENR : 0x20004006 [0x4002101c] | |
BDCR : 0x00000000 [0x40021020] | |
CSR : 0x0c000000 [0x40021024] | |
CFGR2 : 0x00000000 [0x4002102c] | |
>>>> spi1 | |
SPI1 settings | |
CR2 : 0x00000000 [0x40013000] | |
CR1 : 0x00000000 [0x40013004] | |
SR : 0x00000000 [0x40013008] | |
DR : 0x00000000 [0x4001300c] | |
CRCPR : 0x00000000 [0x40013010] | |
RXCRCR : 0x00000000 [0x40013014] | |
TXCRCR : 0x00000000 [0x40013018] | |
>>>> spi2 | |
SPI2 settings | |
CR2 : 0x00000347 [0x40003800] | |
CR1 : 0x00000000 [0x40003804] | |
SR : 0x00000002 [0x40003808] | |
DR : 0x000000ff [0x4000380c] | |
CRCPR : 0x00000007 [0x40003810] | |
RXCRCR : 0x00000000 [0x40003814] | |
TXCRCR : 0x00000000 [0x40003818] | |
>>>> tim4 | |
TIM4 settings | |
CR1 : 0x00000081 [0x40000800] | |
CR2 : 0x00000000 [0x40000804] | |
SMC : 0x00000000 [0x40000808] | |
DIER : 0x00000000 [0x4000080c] | |
SR : 0x0000001f [0x40000810] | |
EGR : 0x00000000 [0x40000814] | |
CCMR1 : 0x00006800 [0x40000818] | |
CCMR2 : 0x00000000 [0x4000081c] | |
CCER : 0x00000010 [0x40000820] | |
CNT : 0x00005c38 [0x40000824] | |
PSC : 0x00000000 [0x40000828] | |
ARR : 0x00005dbf [0x4000082c] | |
RCR : 0x00000000 [0x40000830] | |
CCR1 : 0x00000000 [0x40000834] | |
CCR2 : 0x00005dc0 [0x40000838] | |
CCR3 : 0x00000000 [0x4000083c] | |
CCR4 : 0x00000000 [0x40000840] | |
BDTR : 0x00000000 [0x40000844] | |
DCR : 0x00000000 [0x40000848] | |
DMAR : 0x00000081 [0x4000084c] | |
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>>>> adc1 | |
ADC1 settings | |
SR : 0x00000010 [0x40012400] | |
CR1 : 0x00000000 [0x40012404] | |
CR2 : 0x009e0001 [0x40012408] | |
SMPR1 : 0x00000000 [0x4001240c] | |
SMPR2 : 0x36c00000 [0x40012410] | |
JOFR1 : 0x00000000 [0x40012414] | |
JOFR2 : 0x00000000 [0x40012418] | |
JOFR3 : 0x00000000 [0x4001241c] | |
JOFR4 : 0x00000000 [0x40012420] | |
HTR : 0x00000fff [0x40012424] | |
LTR : 0x00000000 [0x40012428] | |
SQR1 : 0x00000000 [0x4001242c] | |
SQR2 : 0x00000000 [0x40012430] | |
SQR3 : 0x00000008 [0x40012434] | |
JSQR : 0x00000000 [0x40012438] | |
JDR1 : 0x00000000 [0x4001243c] | |
JDR2 : 0x00000000 [0x40012440] | |
JDR3 : 0x00000000 [0x40012444] | |
JDR4 : 0x00000000 [0x40012448] | |
DR : 0x000005a6 [0x4001244c] | |
>>>> afio | |
AFIO settings | |
EVCR : 0x00000000 [0x40010000] | |
MAPR : 0x02008000 [0x40010004] | |
EXTICR1 : 0x00000000 [0x40010008] | |
EXTICR2 : 0x00000011 [0x4001000c] | |
EXTICR3 : 0x00000011 [0x40010010] | |
EXTICR4 : 0x00000000 [0x40010014] | |
MAPR2 : 0x00000000 [0x40010018] | |
>>>> dac | |
DAC settings | |
CR : 0x00030003 [0x40007400] | |
SWTRIGR : 0x00000000 [0x40007404] | |
DHR12R1 : 0x00000180 [0x40007408] | |
DHR12L1 : 0x00001800 [0x4000740c] | |
DHR8R1 : 0x00000018 [0x40007410] | |
DHR12R2 : 0x00000309 [0x40007414] | |
DHR12L2 : 0x00003090 [0x40007418] | |
DHR8R2 : 0x00000030 [0x4000741c] | |
DHR12RD : 0x03090180 [0x40007420] | |
DHR12LD : 0x30901800 [0x40007424] | |
DHR8RD : 0x00003018 [0x40007428] | |
DOR1 : 0x00000180 [0x4000742c] | |
DOR2 : 0x00000309 [0x40007430] | |
SR : 0x00000000 [0x40007434] | |
>>>> dma | |
DMA settings | |
ISR : 0x00000000 [0x40020000] | |
IFCR : 0x00000000 [0x40020004] | |
CCR1 : 0x00000000 [0x40020008] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR1 : 0x00000000 [0x40020010] | |
CMAR1 : 0x00000000 [0x40020014] | |
CCR2 : 0x00000000 [0x4002001c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR2 : 0x00000000 [0x40020024] | |
CMAR2 : 0x00000000 [0x40020028] | |
CCR3 : 0x00000000 [0x40020030] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR3 : 0x00000000 [0x40020038] | |
CMAR3 : 0x00000000 [0x4002003c] | |
CCR4 : 0x00000000 [0x40020044] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR4 : 0x00000000 [0x4002004c] | |
CMAR4 : 0x00000000 [0x40020050] | |
CCR5 : 0x00000000 [0x40020058] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR5 : 0x00000000 [0x40020060] | |
CMAR5 : 0x00000000 [0x40020064] | |
CCR6 : 0x00000000 [0x4002006c] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR6 : 0x00000000 [0x40020074] | |
CMAR6 : 0x00000000 [0x40020078] | |
CCR7 : 0x00000000 [0x40020080] | |
CNDTR : 0x00000000 [0x40020084] | |
CPAR7 : 0x00000000 [0x40020088] | |
>>>> exti | |
EXTI settings | |
IMR : 0x0000033e [0x40010400] | |
EMR : 0x00000000 [0x40010404] | |
RTSR : 0x00000300 [0x40010408] | |
FTSR : 0x0000033e [0x4001040c] | |
SWIER : 0x00000000 [0x40010410] | |
PR : 0x00000000 [0x40010414] | |
>>>> gpio | |
// PA0 O 1 OD (50 Mhz) U7 | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO0); | |
// PA1 I 1 PuPd M2 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO1); | |
gpio_set(GPIOA, GPIO1); | |
// PA2 I 1 PuPd SEL button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO2); | |
gpio_set(GPIOA, GPIO2); | |
// PA3 I 1 PuPd M1 button | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO3); | |
gpio_set(GPIOA, GPIO3); | |
// PA4 I 0 An DAC1_OUT TL594.2 (1IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4); | |
// PA5 I 0 An DAC2_OUT TL594.15 (2IN-) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO5); | |
// PA6 I 0 An | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO6); | |
// PA7 I 0 An ADC1_IN7 R30-U2.7:V_OUT-B (measures Vout) | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO7); | |
// PA8 O 0 PP (50 Mhz) TFT.7 (not used by TFT) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); | |
// PA9 O 0 AF-PP (50 Mhz) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO9); | |
// PA10 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO10); | |
gpio_clear(GPIOA, GPIO10); | |
// PA11 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PA12 I 1 Flt | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PA13 I 0 PuPd | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO13); | |
gpio_clear(GPIOA, GPIO13); | |
// PA14 I 1 PuPd SWDCLK | |
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); | |
gpio_set(GPIOA, GPIO14); | |
// PA15 O 1 OD (50 Mhz) R41-TL594.16 (2IN+) | |
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO15); | |
// PB0 I 0 An ADC1_IN8 R7/R2-R14-D4 (measures Vin) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0); | |
// PB1 I 0 An ADC1_IN9 R33-U2.1:V_OUT-A (measures Iout) | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1); | |
// PB2 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PB3 O 1 OD (50 Mhz) R11-R17-R25-U2.5 (V_inB+) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO3); | |
// PB4 I 1 PuPd PWR button | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO4); | |
gpio_set(GPIOB, GPIO4); | |
// PB5 I 1 PuPd Rotary press | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO5); | |
gpio_set(GPIOB, GPIO5); | |
// PB6 I 1 Flt NC? | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PB7 O 0 AF-PP (50 Mhz) TIM4_CH2 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7); | |
// PB8 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO8); | |
gpio_set(GPIOB, GPIO8); | |
// PB9 I 1 PuPd Rotary enc | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO9); | |
gpio_set(GPIOB, GPIO9); | |
// PB10 I 1 Flt | |
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PB11 O 0 PP (50 Mhz) nPwrEnable R29-TFT.2 (TFT_VCC) | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); | |
// PB12 O 1 PP (50 Mhz) SPI2_NSS TFT_RESET | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); | |
// PB13 O 1 AF-PP (50 Mhz) SPI2_SCK | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13); | |
// PB14 O 1 PP (50 Mhz) SPI2_MISO TFT_A0 | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); | |
// PB15 O 1 AF-PP (50 Mhz) SPI2_MOSI | |
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO15); | |
// PC0 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PC1 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); | |
// PC2 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PC3 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PC4 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PC5 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PC6 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PC7 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PC8 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PC9 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PC10 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PC11 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PC12 I 0 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PC13 O 0 PP (50 Mhz) | |
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); | |
// PC14 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PC15 I 1 Flt | |
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
// PD0 I 1 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0); | |
// PD1 O 1 PP (50 Mhz) U7 | |
gpio_set_mode(GPIOD, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); | |
// PD2 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO2); | |
// PD3 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO3); | |
// PD4 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO4); | |
// PD5 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO5); | |
// PD6 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); | |
// PD7 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); | |
// PD8 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); | |
// PD9 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO9); | |
// PD10 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO10); | |
// PD11 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO11); | |
// PD12 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO12); | |
// PD13 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO13); | |
// PD14 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); | |
// PD15 I 0 Flt | |
gpio_set_mode(GPIOD, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO15); | |
>>>> gpioa | |
GPIOA settings | |
CRL : 0x00008887 [0x40010800] | |
CRH : 0x788448b3 [0x40010804] | |
IDR : 0x00005a0f [0x40010808] | |
ODR : 0x0000a04f [0x4001080c] | |
BSRR : 0x00000000 [0x40010810] | |
BRR : 0x00000000 [0x40010814] | |
LCKR : 0x00000000 [0x40010818] | |
>>>> gpiob | |
GPIOB settings | |
CRL : 0xb4887400 [0x40010c00] | |
CRH : 0xb3b33488 [0x40010c04] | |
IDR : 0x000077f4 [0x40010c08] | |
ODR : 0x0000f338 [0x40010c0c] | |
BSRR : 0x00000000 [0x40010c10] | |
BRR : 0x00000000 [0x40010c14] | |
LCKR : 0x00000000 [0x40010c18] | |
>>>> gpioc | |
GPIOC settings | |
CRL : 0x44444444 [0x40011000] | |
CRH : 0x44344444 [0x40011004] | |
IDR : 0x0000c000 [0x40011008] | |
ODR : 0x00000000 [0x4001100c] | |
BSRR : 0x00000000 [0x40011010] | |
BRR : 0x00000000 [0x40011014] | |
LCKR : 0x00000000 [0x40011018] | |
>>>> gpiod | |
GPIOD settings | |
CRL : 0x44444434 [0x40011400] | |
CRH : 0x44444444 [0x40011404] | |
IDR : 0x00000003 [0x40011408] | |
ODR : 0x00000002 [0x4001140c] | |
BSRR : 0x00000000 [0x40011410] | |
BRR : 0x00000000 [0x40011414] | |
LCKR : 0x00000000 [0x40011418] | |
>>>> rcc | |
RCC settings | |
CR : 0x03004883 [0x40021000] | |
CFGR : 0x0410000a [0x40021004] | |
CIR : 0x00000000 [0x40021008] | |
APB2RSTR : 0x00000000 [0x4002100c] | |
APB1RSTR : 0x00000000 [0x40021010] | |
AHBENR : 0x00000014 [0x40021014] | |
APB2ENR : 0x0000423d [0x40021018] | |
APB1ENR : 0x20004006 [0x4002101c] | |
BDCR : 0x00000000 [0x40021020] | |
CSR : 0x0c000000 [0x40021024] | |
CFGR2 : 0x00000000 [0x4002102c] | |
>>>> spi1 | |
SPI1 settings | |
CR2 : 0x00000000 [0x40013000] | |
CR1 : 0x00000000 [0x40013004] | |
SR : 0x00000000 [0x40013008] | |
DR : 0x00000000 [0x4001300c] | |
CRCPR : 0x00000000 [0x40013010] | |
RXCRCR : 0x00000000 [0x40013014] | |
TXCRCR : 0x00000000 [0x40013018] | |
>>>> spi2 | |
SPI2 settings | |
CR2 : 0x00000347 [0x40003800] | |
CR1 : 0x00000000 [0x40003804] | |
SR : 0x00000003 [0x40003808] | |
DR : 0x000000ff [0x4000380c] | |
CRCPR : 0x00000007 [0x40003810] | |
RXCRCR : 0x00000000 [0x40003814] | |
TXCRCR : 0x00000000 [0x40003818] | |
>>>> tim4 | |
TIM4 settings | |
CR1 : 0x00000081 [0x40000800] | |
CR2 : 0x00000000 [0x40000804] | |
SMC : 0x00000000 [0x40000808] | |
DIER : 0x00000000 [0x4000080c] | |
SR : 0x0000001f [0x40000810] | |
EGR : 0x00000000 [0x40000814] | |
CCMR1 : 0x00006800 [0x40000818] | |
CCMR2 : 0x00000000 [0x4000081c] | |
CCER : 0x00000010 [0x40000820] | |
CNT : 0x00004432 [0x40000824] | |
PSC : 0x00000000 [0x40000828] | |
ARR : 0x00005dbf [0x4000082c] | |
RCR : 0x00000000 [0x40000830] | |
CCR1 : 0x00000000 [0x40000834] | |
CCR2 : 0x00005dc0 [0x40000838] | |
CCR3 : 0x00000000 [0x4000083c] | |
CCR4 : 0x00000000 [0x40000840] | |
BDTR : 0x00000000 [0x40000844] | |
DCR : 0x00000000 [0x40000848] | |
DMAR : 0x00000081 [0x4000084c] | |
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