clock_tb.vhd

library IEEE;
use IEEE.std_logic_1164.all;

use work.types.all;

entity clock_tb is
    end clock_tb;

architecture behavioral of clock_tb is
    signal clk : std_logic;
    signal clock_in : clock_in_t;
    signal clock_out : clock_out_t;

    signal hour_h : std_logic_vector(1 downto 0);
    signal hour_l : std_logic_vector(4 downto 0);
    signal minute_h : std_logic_vector(2 downto 0);
    signal minute_l : std_logic_vector(4 downto 0);
    signal minute_ll : std_logic;
    signal dp : std_logic;

begin
    cl: clock port map (
                           clk => clk,
                           clock_in => clock_in,
                           clock_out => clock_out);

    process is
    begin
        clk <= '1';
        -- wait for 15.26 us;
        wait for 3.90625ms;
        clk <= '0';
        -- wait for 15.26 us;
        wait for 3.90625ms;
    end process;

    process is
    begin
        clock_in.set_b <= '0';
        clock_in.up_b <= '0';
        wait for 1200.5 sec;
        clock_in.set_b <= '1';
        wait for 10 ms;
        clock_in.set_b <= '0';
        for i in 0 to 25 loop
            wait for 1.5 sec;
            clock_in.up_b <= '1';
            wait for 10 ms;
            clock_in.up_b <= '0';
        end loop;

        wait for 1.5 sec;
        clock_in.set_b <= '1';
        wait for 10 ms;
        clock_in.set_b <= '0';

        for i in 0 to 80 loop
            wait for 1.5 sec;
            clock_in.up_b <= '1';
            wait for 10 ms;
            clock_in.up_b <= '0';
        end loop;

        wait for 1.5 sec;
        clock_in.set_b <= '1';
        wait for 10 ms;
        clock_in.set_b <= '0';

        wait;
    end process;

end architecture;