top.rpt

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3833 (git sha1 b0004911, clang 7.0.1-8+deb10u2 -fPIC -Os)


-- Executing script file `top.ys' --

1. Executing RTLIL frontend.
Input filename: top.il

2. Executing SYNTH_ICE40 pass.

2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\ICESTORM_RAM'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.2.1. Analyzing design hierarchy..
Top module:  \top
Used module:     \pin_clk100_0
Used module:     \pin_led_7
Used module:     \pin_led_6
Used module:     \pin_led_5
Used module:     \pin_led_4
Used module:     \pin_led_3
Used module:     \pin_led_2
Used module:     \pin_led_1
Used module:     \pin_led_0
Used module:     \cd_sync

2.2.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \pin_clk100_0
Used module:     \pin_led_7
Used module:     \pin_led_6
Used module:     \pin_led_5
Used module:     \pin_led_4
Used module:     \pin_led_3
Used module:     \pin_led_2
Used module:     \pin_led_1
Used module:     \pin_led_0
Used module:     \cd_sync
Removed 0 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1330$241 in module SB_DFFNES.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1274$234 in module SB_DFFNESS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1199$230 in module SB_DFFNER.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1143$223 in module SB_DFFNESR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1074$220 in module SB_DFFNS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1026$217 in module SB_DFFNSS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:957$214 in module SB_DFFNR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:909$211 in module SB_DFFNSR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:753$203 in module SB_DFFES.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:697$196 in module SB_DFFESS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:622$192 in module SB_DFFER.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:566$185 in module SB_DFFESR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:497$182 in module SB_DFFS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:449$179 in module SB_DFFSS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:380$176 in module SB_DFFR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:332$173 in module SB_DFFSR.
Marked 1 switch rules as full_case in process $group_2 in module cd_sync.
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 20 redundant assignments.
Promoted 33 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'.
  Set init value: \Q = 1'0
Found init rule in `\top.$group_0'.
  Set init value: \timer = 27'000000000000000000000000000
Found init rule in `\cd_sync.$group_2'.
  Set init value: \timer = 11'00000000000
Found init rule in `\cd_sync.$group_1'.
  Set init value: \ready = 1'0

2.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \S in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1330$241'.
Found async reset \R in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1199$230'.
Found async reset \S in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1074$220'.
Found async reset \R in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:957$214'.
Found async reset \S in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:753$203'.
Found async reset \R in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:622$192'.
Found async reset \S in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:497$182'.
Found async reset \R in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:380$176'.

2.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'.
Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1330$241'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'.
Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1274$234'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'.
Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1199$230'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'.
Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1143$223'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'.
Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1074$220'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'.
Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1026$217'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'.
Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:957$214'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'.
Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:909$211'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'.
Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:866$209'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'.
Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:830$207'.
Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'.
Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:753$203'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'.
Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:697$196'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'.
Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:622$192'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'.
Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:566$185'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'.
Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:497$182'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'.
Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:449$179'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'.
Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:380$176'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'.
Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:332$173'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'.
Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:289$171'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'.
Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:253$169'.
Creating decoders for process `\top.$group_8'.
Creating decoders for process `\top.$group_7'.
Creating decoders for process `\top.$group_6'.
Creating decoders for process `\top.$group_5'.
Creating decoders for process `\top.$group_4'.
Creating decoders for process `\top.$group_3'.
Creating decoders for process `\top.$group_2'.
Creating decoders for process `\top.$group_1'.
Creating decoders for process `\top.$group_0'.
     1/1: \timer$next
Creating decoders for process `\cd_sync.$group_4'.
Creating decoders for process `\cd_sync.$group_3'.
Creating decoders for process `\cd_sync.$group_2'.
     1/1: \timer$next
Creating decoders for process `\cd_sync.$group_1'.
     1/1: \ready$next
Creating decoders for process `\cd_sync.$group_0'.

2.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1330$241'.
  created $adff cell `$procdff$432' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1274$234'.
  created $dff cell `$procdff$433' with negative edge clock.
Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1199$230'.
  created $adff cell `$procdff$434' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1143$223'.
  created $dff cell `$procdff$435' with negative edge clock.
Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1074$220'.
  created $adff cell `$procdff$436' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1026$217'.
  created $dff cell `$procdff$437' with negative edge clock.
Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:957$214'.
  created $adff cell `$procdff$438' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:909$211'.
  created $dff cell `$procdff$439' with negative edge clock.
Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:866$209'.
  created $dff cell `$procdff$440' with negative edge clock.
Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:830$207'.
  created $dff cell `$procdff$441' with negative edge clock.
Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:753$203'.
  created $adff cell `$procdff$442' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:697$196'.
  created $dff cell `$procdff$443' with positive edge clock.
Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:622$192'.
  created $adff cell `$procdff$444' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:566$185'.
  created $dff cell `$procdff$445' with positive edge clock.
Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:497$182'.
  created $adff cell `$procdff$446' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:449$179'.
  created $dff cell `$procdff$447' with positive edge clock.
Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:380$176'.
  created $adff cell `$procdff$448' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:332$173'.
  created $dff cell `$procdff$449' with positive edge clock.
Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:289$171'.
  created $dff cell `$procdff$450' with positive edge clock.
Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:253$169'.
  created $dff cell `$procdff$451' with positive edge clock.
Creating register for signal `\top.\timer' using process `\top.$group_0'.
  created $dff cell `$procdff$452' with positive edge clock.
Creating register for signal `\cd_sync.\timer' using process `\cd_sync.$group_2'.
  created $dff cell `$procdff$453' with positive edge clock.
Creating register for signal `\cd_sync.\ready' using process `\cd_sync.$group_1'.
  created $dff cell `$procdff$454' with positive edge clock.

2.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'.
Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1330$241'.
Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1330$241'.
Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'.
Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1274$234'.
Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1274$234'.
Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'.
Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1199$230'.
Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1199$230'.
Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'.
Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1143$223'.
Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1143$223'.
Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'.
Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1074$220'.
Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'.
Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1026$217'.
Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1026$217'.
Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'.
Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:957$214'.
Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'.
Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:909$211'.
Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:909$211'.
Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'.
Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:866$209'.
Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:866$209'.
Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'.
Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:830$207'.
Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'.
Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:753$203'.
Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:753$203'.
Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'.
Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:697$196'.
Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:697$196'.
Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'.
Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:622$192'.
Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:622$192'.
Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'.
Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:566$185'.
Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:566$185'.
Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'.
Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:497$182'.
Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'.
Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:449$179'.
Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:449$179'.
Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'.
Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:380$176'.
Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'.
Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:332$173'.
Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:332$173'.
Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'.
Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:289$171'.
Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:289$171'.
Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'.
Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:253$169'.
Removing empty process `top.$group_8'.
Removing empty process `top.$group_7'.
Removing empty process `top.$group_6'.
Removing empty process `top.$group_5'.
Removing empty process `top.$group_4'.
Removing empty process `top.$group_3'.
Removing empty process `top.$group_2'.
Removing empty process `top.$group_1'.
Found and cleaned up 1 empty switch in `\top.$group_0'.
Removing empty process `top.$group_0'.
Removing empty process `cd_sync.$group_4'.
Removing empty process `cd_sync.$group_3'.
Found and cleaned up 1 empty switch in `\cd_sync.$group_2'.
Removing empty process `cd_sync.$group_2'.
Found and cleaned up 1 empty switch in `\cd_sync.$group_1'.
Removing empty process `cd_sync.$group_1'.
Removing empty process `cd_sync.$group_0'.
Cleaned up 21 empty switches.

2.4. Executing FLATTEN pass (flatten design).
Deleting now unused module pin_clk100_0.
Deleting now unused module pin_led_7.
Deleting now unused module pin_led_6.
Deleting now unused module pin_led_5.
Deleting now unused module pin_led_4.
Deleting now unused module pin_led_3.
Deleting now unused module pin_led_2.
Deleting now unused module pin_led_1.
Deleting now unused module pin_led_0.
Deleting now unused module cd_sync.
<suppressed ~10 debug messages>

2.5. Executing TRIBUF pass.

2.6. Executing DEMINOUT pass (demote inout ports to input or output).

2.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 11 unused wires.
<suppressed ~4 debug messages>

2.9. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

2.10. Executing OPT pass (performing simple optimizations).

2.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>

2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.10.6. Executing OPT_DFF pass (perform DFF optimizations).

2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

2.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.10.9. Rerunning OPT passes. (Maybe there is more to do..)

2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>

2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.10.13. Executing OPT_DFF pass (perform DFF optimizations).

2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.10.16. Finished OPT passes. (There is nothing left to do.)

2.11. Executing FSM pass (extract and optimize FSM).

2.11.1. Executing FSM_DETECT pass (finding FSMs in design).

2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.12. Executing OPT pass (performing simple optimizations).

2.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>

2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.12.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$452 ($dff) from module top (D = $1 [26:0], Q = \timer, rval = 27'000000000000000000000000000).
Adding EN signal on $flatten\cd_sync.$procdff$454 ($dff) from module top (D = 1'1, Q = \cd_sync.ready).
Adding EN signal on $flatten\cd_sync.$procdff$453 ($dff) from module top (D = $flatten\cd_sync.$5 [10:0], Q = \cd_sync.timer).

2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 3 unused wires.
<suppressed ~6 debug messages>

2.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.12.9. Rerunning OPT passes. (Maybe there is more to do..)

2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.12.13. Executing OPT_DFF pass (perform DFF optimizations).

2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.12.16. Finished OPT passes. (There is nothing left to do.)

2.13. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 28) from port Y of cell top.$3 ($add).
Removed top 1 bits (of 12) from port Y of cell top.$flatten\cd_sync.$7 ($add).
Removed top 1 bits (of 28) from wire top.$1.

2.14. Executing PEEPOPT pass (run peephole optimizers).

2.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

2.16. Executing SHARE pass (SAT-based resource sharing).

2.17. Executing TECHMAP pass (map to technology primitives).

2.17.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

2.17.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>

2.18. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.20. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $3 ($add).
  creating $macc model for $flatten\cd_sync.$7 ($add).
  creating $alu model for $macc $flatten\cd_sync.$7.
  creating $alu model for $macc $3.
  creating $alu cell for $3: $auto$alumacc.cc:485:replace_alu$459
  creating $alu cell for $flatten\cd_sync.$7: $auto$alumacc.cc:485:replace_alu$462
  created 2 $alu and 0 $macc cells.

2.21. Executing OPT pass (performing simple optimizations).

2.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.21.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.21.6. Executing OPT_DFF pass (perform DFF optimizations).

2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.21.9. Finished OPT passes. (There is nothing left to do.)

2.22. Executing MEMORY pass.

2.22.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

2.22.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

2.22.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.22.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.22.6. Executing MEMORY_COLLECT pass (generating $mem cells).

2.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).

2.25. Executing TECHMAP pass (map to technology primitives).

2.25.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
Successfully finished Verilog frontend.

2.25.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

2.26. Executing ICE40_BRAMINIT pass.

2.27. Executing OPT pass (performing simple optimizations).

2.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.27.3. Executing OPT_DFF pass (perform DFF optimizations).

2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.27.5. Finished fast OPT passes.

2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

2.29. Executing OPT pass (performing simple optimizations).

2.29.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.29.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.29.6. Executing OPT_DFF pass (perform DFF optimizations).

2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.29.9. Finished OPT passes. (There is nothing left to do.)

2.30. Executing ICE40_WRAPCARRY pass (wrap carries).

2.31. Executing TECHMAP pass (map to technology primitives).

2.31.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.31.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

2.31.3. Continuing TECHMAP pass.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=27\Y_WIDTH=27 for cells of type $alu.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~121 debug messages>

2.32. Executing OPT pass (performing simple optimizations).

2.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~99 debug messages>

2.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~27 debug messages>
Removed a total of 9 cells.

2.32.3. Executing OPT_DFF pass (perform DFF optimizations).

2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 32 unused cells and 37 unused wires.
<suppressed ~33 debug messages>

2.32.5. Finished fast OPT passes.

2.33. Executing ICE40_OPT pass (performing simple optimizations).

2.33.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$459.slice[0].carry: CO=\timer [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$462.slice[0].carry: CO=\cd_sync.timer [0]

2.33.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.33.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.33.4. Executing OPT_DFF pass (perform DFF optimizations).

2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.33.6. Rerunning OPT passes. (Removed registers in this run.)

2.33.7. Running ICE40 specific optimizations.

2.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.33.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.33.10. Executing OPT_DFF pass (perform DFF optimizations).

2.33.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.33.12. Finished OPT passes. (There is nothing left to do.)

2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

2.35. Executing TECHMAP pass (map to technology primitives).

2.35.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.35.2. Continuing TECHMAP pass.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~61 debug messages>

2.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping top.$auto$alumacc.cc:485:replace_alu$459.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$462.slice[0].carry ($lut).

2.38. Executing ICE40_OPT pass (performing simple optimizations).

2.38.1. Running ICE40 specific optimizations.

2.38.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~28 debug messages>

2.38.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~78 debug messages>
Removed a total of 26 cells.

2.38.4. Executing OPT_DFF pass (perform DFF optimizations).

2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 229 unused wires.
<suppressed ~1 debug messages>

2.38.6. Rerunning OPT passes. (Removed registers in this run.)

2.38.7. Running ICE40 specific optimizations.

2.38.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.38.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.38.10. Executing OPT_DFF pass (perform DFF optimizations).

2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.38.12. Finished OPT passes. (There is nothing left to do.)

2.39. Executing TECHMAP pass (map to technology primitives).

2.39.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

2.39.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

2.40. Executing ABC pass (technology mapping using ABC).

2.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 21 gates and 34 wires to a netlist network with 13 inputs and 5 outputs.

2.40.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + lutpack -S 1 
ABC: + dress 
ABC: Total number of equiv classes                =       4.
ABC: Participating nodes from both networks       =       6.
ABC: Participating nodes from the first network   =       3. (  33.33 % of nodes)
ABC: Participating nodes from the second network  =       3. (  33.33 % of nodes)
ABC: Node pairs (any polarity)                    =       3. (  33.33 % of names can be moved)
ABC: Node pairs (same polarity)                   =       3. (  33.33 % of names can be moved)
ABC: Total runtime =     0.00 sec
ABC: + write_blif <abc-temp-dir>/output.blif 

2.40.1.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:        8
ABC RESULTS:        internal signals:       16
ABC RESULTS:           input signals:       13
ABC RESULTS:          output signals:        5
Removing temp directory.

2.41. Executing ICE40_WRAPCARRY pass (wrap carries).

2.42. Executing TECHMAP pass (map to technology primitives).

2.42.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.42.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 2 unused cells and 30 unused wires.

2.43. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:       44
  1-LUT                3
  2-LUT               36
  3-LUT                3
  4-LUT                2

Eliminating LUTs.
Number of LUTs:       44
  1-LUT                3
  2-LUT               36
  3-LUT                3
  4-LUT                2

Combining LUTs.
Number of LUTs:       44
  1-LUT                3
  2-LUT               36
  3-LUT                3
  4-LUT                2

Eliminated 0 LUTs.
Combined 0 LUTs.
<suppressed ~98 debug messages>

2.44. Executing TECHMAP pass (map to technology primitives).

2.44.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.44.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut.
No more expansions possible.
<suppressed ~125 debug messages>
Removed 0 unused cells and 90 unused wires.

2.45. Executing AUTONAME pass.
Renamed 606 objects in module top (10 iterations).
<suppressed ~125 debug messages>

2.46. Executing HIERARCHY pass (managing design hierarchy).

2.46.1. Analyzing design hierarchy..
Top module:  \top

2.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

2.47. Printing statistics.

=== top ===

   Number of wires:                 51
   Number of wire bits:            161
   Number of public wires:          51
   Number of public wire bits:     161
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                126
     SB_CARRY                       34
     SB_DFFE                        12
     SB_DFFSR                       27
     SB_GB_IO                        1
     SB_IO                           8
     SB_LUT4                        44

2.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

3. Executing JSON backend.

End of script. Logfile hash: 7ec96456f8, CPU: user 0.62s system 0.03s, MEM: 55.86 MB peak
Yosys 0.9+3833 (git sha1 b0004911, clang 7.0.1-8+deb10u2 -fPIC -Os)
Time spent: 33% 10x read_verilog (0 sec), 14% 19x opt_clean (0 sec), ...

top.tim

Info: constrained 'led_0__io' to bel 'X33/Y6/io0'
Info: constrained 'led_1__io' to bel 'X33/Y4/io1'
Info: constrained 'led_2__io' to bel 'X33/Y4/io0'
Info: constrained 'led_3__io' to bel 'X33/Y5/io0'
Info: constrained 'led_4__io' to bel 'X33/Y2/io0'
Info: constrained 'led_5__io' to bel 'X33/Y3/io1'
Info: constrained 'led_6__io' to bel 'X33/Y1/io0'
Info: constrained 'led_7__io' to bel 'X33/Y2/io1'
Info: constrained 'clk100_0__io' to bel 'X16/Y0/io1'
Info: constraining clock net 'cd_sync_clk100_0__i' to 100.00 MHz

Info: Packing constants..
Info: Packing IOs..
Info: clk100_0__io feeds SB_IO pin_clk100_0.clk100_0_0, removing $nextpnr_iobuf clk100_0__io.
Info: led_0__io feeds SB_IO pin_led_0.led_0_0, removing $nextpnr_iobuf led_0__io.
Info: led_1__io feeds SB_IO pin_led_1.led_1_0, removing $nextpnr_iobuf led_1__io.
Info: led_2__io feeds SB_IO pin_led_2.led_2_0, removing $nextpnr_iobuf led_2__io.
Info: led_3__io feeds SB_IO pin_led_3.led_3_0, removing $nextpnr_iobuf led_3__io.
Info: led_4__io feeds SB_IO pin_led_4.led_4_0, removing $nextpnr_iobuf led_4__io.
Info: led_5__io feeds SB_IO pin_led_5.led_5_0, removing $nextpnr_iobuf led_5__io.
Info: led_6__io feeds SB_IO pin_led_6.led_6_0, removing $nextpnr_iobuf led_6__io.
Info: led_7__io feeds SB_IO pin_led_7.led_7_0, removing $nextpnr_iobuf led_7__io.
Info: Packing LUT-FFs..
Info:        6 LCs used as LUT4 only
Info:       38 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:        1 LCs used as DFF only
Info: Packing carries..
Info:        1 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: Packing PLLs..
Info: Promoting globals..
Info: promoting cd_sync.ready_SB_LUT4_I3_O [reset] (fanout 27)
Info: Constraining chains...
Info:        2 LCs used to legalise carry chains.
Info: Checksum: 0x2a7b1507

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x11444431

Info: Device utilisation:
Info: 	         ICESTORM_LC:    50/ 7680     0%
Info: 	        ICESTORM_RAM:     0/   32     0%
Info: 	               SB_IO:     9/  256     3%
Info: 	               SB_GB:     2/    8    25%
Info: 	        ICESTORM_PLL:     0/    2     0%
Info: 	         SB_WARMBOOT:     0/    1     0%

Info: Placed 10 cells based on constraints.
Info: Creating initial analytic placement for 14 cells, random placement wirelen = 527.
Info:     at initial placer iter 0, wirelen = 13
Info:     at initial placer iter 1, wirelen = 15
Info:     at initial placer iter 2, wirelen = 13
Info:     at initial placer iter 3, wirelen = 14
Info: Running main analytical placer.
Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 14, spread = 16, legal = 48; time = 0.00s
Info:     at iteration #1, type SB_GB: wirelen solved = 46, spread = 46, legal = 59; time = 0.00s
Info:     at iteration #1, type ALL: wirelen solved = 14, spread = 14, legal = 58; time = 0.00s
Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 14, spread = 14, legal = 51; time = 0.00s
Info:     at iteration #2, type SB_GB: wirelen solved = 49, spread = 49, legal = 51; time = 0.00s
Info:     at iteration #2, type ALL: wirelen solved = 14, spread = 32, legal = 51; time = 0.00s
Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 15, spread = 35, legal = 73; time = 0.00s
Info:     at iteration #3, type SB_GB: wirelen solved = 72, spread = 72, legal = 73; time = 0.00s
Info:     at iteration #3, type ALL: wirelen solved = 14, spread = 29, legal = 49; time = 0.00s
Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 15, spread = 32, legal = 59; time = 0.00s
Info:     at iteration #4, type SB_GB: wirelen solved = 58, spread = 58, legal = 59; time = 0.00s
Info:     at iteration #4, type ALL: wirelen solved = 14, spread = 32, legal = 49; time = 0.00s
Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 15, spread = 35, legal = 50; time = 0.00s
Info:     at iteration #5, type SB_GB: wirelen solved = 49, spread = 49, legal = 50; time = 0.00s
Info:     at iteration #5, type ALL: wirelen solved = 20, spread = 34, legal = 50; time = 0.00s
Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 18, spread = 51, legal = 52; time = 0.00s
Info:     at iteration #6, type SB_GB: wirelen solved = 51, spread = 51, legal = 52; time = 0.00s
Info:     at iteration #6, type ALL: wirelen solved = 21, spread = 35, legal = 50; time = 0.00s
Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 19, spread = 43, legal = 67; time = 0.00s
Info:     at iteration #7, type SB_GB: wirelen solved = 66, spread = 66, legal = 67; time = 0.00s
Info:     at iteration #7, type ALL: wirelen solved = 16, spread = 16, legal = 48; time = 0.00s
Info:     at iteration #8, type ICESTORM_LC: wirelen solved = 18, spread = 37, legal = 72; time = 0.00s
Info:     at iteration #8, type SB_GB: wirelen solved = 70, spread = 70, legal = 72; time = 0.00s
Info:     at iteration #8, type ALL: wirelen solved = 16, spread = 35, legal = 44; time = 0.00s
Info:     at iteration #9, type ICESTORM_LC: wirelen solved = 21, spread = 41, legal = 74; time = 0.00s
Info:     at iteration #9, type SB_GB: wirelen solved = 70, spread = 70, legal = 74; time = 0.00s
Info:     at iteration #9, type ALL: wirelen solved = 15, spread = 35, legal = 59; time = 0.00s
Info:     at iteration #10, type ICESTORM_LC: wirelen solved = 18, spread = 39, legal = 80; time = 0.00s
Info:     at iteration #10, type SB_GB: wirelen solved = 79, spread = 79, legal = 80; time = 0.00s
Info:     at iteration #10, type ALL: wirelen solved = 15, spread = 35, legal = 40; time = 0.00s
Info:     at iteration #11, type ICESTORM_LC: wirelen solved = 22, spread = 43, legal = 45; time = 0.00s
Info:     at iteration #11, type SB_GB: wirelen solved = 45, spread = 45, legal = 45; time = 0.00s
Info:     at iteration #11, type ALL: wirelen solved = 16, spread = 36, legal = 49; time = 0.00s
Info:     at iteration #12, type ICESTORM_LC: wirelen solved = 23, spread = 66, legal = 69; time = 0.00s
Info:     at iteration #12, type SB_GB: wirelen solved = 67, spread = 67, legal = 69; time = 0.00s
Info:     at iteration #12, type ALL: wirelen solved = 16, spread = 41, legal = 56; time = 0.00s
Info:     at iteration #13, type ICESTORM_LC: wirelen solved = 23, spread = 46, legal = 69; time = 0.00s
Info:     at iteration #13, type SB_GB: wirelen solved = 68, spread = 68, legal = 69; time = 0.00s
Info:     at iteration #13, type ALL: wirelen solved = 19, spread = 43, legal = 52; time = 0.00s
Info:     at iteration #14, type ICESTORM_LC: wirelen solved = 24, spread = 42, legal = 46; time = 0.00s
Info:     at iteration #14, type SB_GB: wirelen solved = 43, spread = 43, legal = 46; time = 0.00s
Info:     at iteration #14, type ALL: wirelen solved = 17, spread = 29, legal = 41; time = 0.00s
Info:     at iteration #15, type ICESTORM_LC: wirelen solved = 23, spread = 42, legal = 60; time = 0.00s
Info:     at iteration #15, type SB_GB: wirelen solved = 56, spread = 56, legal = 60; time = 0.00s
Info:     at iteration #15, type ALL: wirelen solved = 19, spread = 44, legal = 76; time = 0.00s
Info: HeAP Placer Time: 0.09s
Info:   of which solving equations: 0.05s
Info:   of which spreading cells: 0.01s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 5, wirelen = 40
Info:   at iteration #5: temp = 0.000000, timing cost = 3, wirelen = 35
Info:   at iteration #8: temp = 0.000000, timing cost = 3, wirelen = 32 
Info: SA placement time 0.02s

Info: Max frequency for clock 'cd_sync_clk100_0__i': 170.01 MHz (PASS at 100.00 MHz)

Info: Max delay posedge cd_sync_clk100_0__i -> <async>: 2.02 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [  4118,   7995) |************************************************************ 
Info: [  7995,  11872) |********************************+
Info: [ 11872,  15749) | 
Info: [ 15749,  19626) | 
Info: [ 19626,  23503) | 
Info: [ 23503,  27380) | 
Info: [ 27380,  31257) | 
Info: [ 31257,  35134) | 
Info: [ 35134,  39011) | 
Info: [ 39011,  42888) | 
Info: [ 42888,  46765) | 
Info: [ 46765,  50642) | 
Info: [ 50642,  54519) | 
Info: [ 54519,  58396) | 
Info: [ 58396,  62273) | 
Info: [ 62273,  66150) | 
Info: [ 66150,  70027) | 
Info: [ 70027,  73904) | 
Info: [ 73904,  77781) | 
Info: [ 77781,  81658) |******+
Info: Checksum: 0x8af8e0f1

Info: Routing..
Info: Setting up routing queue.
Info: Routing 157 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        157 |        0        127 |    0   127 |         0|       0.05       0.05|
Info: Routing complete.
Info: Router1 time 0.05s
Info: Checksum: 0xde8b3920

Info: Critical path report for clock 'cd_sync_clk100_0__i' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_25_LC.O
Info:  0.6  1.1    Net timer[0] budget 4.706000 ns (30,3) -> (31,3)
Info:                Sink $nextpnr_ICESTORM_LC_1.I1
Info:                Defined in:
Info:                  ./01_blinky.py:11
Info:  0.3  1.4  Source $nextpnr_ICESTORM_LC_1.COUT
Info:  0.0  1.4    Net $nextpnr_ICESTORM_LC_1$O budget 0.000000 ns (31,3) -> (31,3)
Info:                Sink timer_SB_CARRY_CI$CARRY.CIN
Info:  0.1  1.5  Source timer_SB_CARRY_CI$CARRY.COUT
Info:  0.0  1.5    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[2] budget 0.000000 ns (31,3) -> (31,3)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_2_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  1.6  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_2_LC.COUT
Info:  0.0  1.6    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[3] budget 0.000000 ns (31,3) -> (31,3)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_1_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  1.8  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_1_LC.COUT
Info:  0.0  1.8    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[4] budget 0.000000 ns (31,3) -> (31,3)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  1.9  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_LC.COUT
Info:  0.0  1.9    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[5] budget 0.000000 ns (31,3) -> (31,3)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_24_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  2.0  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_24_LC.COUT
Info:  0.0  2.0    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[6] budget 0.000000 ns (31,3) -> (31,3)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_23_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  2.1  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_23_LC.COUT
Info:  0.0  2.1    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[7] budget 0.000000 ns (31,3) -> (31,3)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_22_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  2.3  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_22_LC.COUT
Info:  0.2  2.5    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[8] budget 0.190000 ns (31,3) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_21_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  2.6  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_21_LC.COUT
Info:  0.0  2.6    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[9] budget 0.000000 ns (31,4) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_20_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  2.7  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_20_LC.COUT
Info:  0.0  2.7    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[10] budget 0.000000 ns (31,4) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_19_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  2.8  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_19_LC.COUT
Info:  0.0  2.8    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[11] budget 0.000000 ns (31,4) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_18_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  3.0  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_18_LC.COUT
Info:  0.0  3.0    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[12] budget 0.000000 ns (31,4) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_17_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  3.1  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_17_LC.COUT
Info:  0.0  3.1    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[13] budget 0.000000 ns (31,4) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_16_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  3.2  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_16_LC.COUT
Info:  0.0  3.2    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[14] budget 0.000000 ns (31,4) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_15_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  3.3  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_15_LC.COUT
Info:  0.0  3.3    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[15] budget 0.000000 ns (31,4) -> (31,4)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_14_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  3.5  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_14_LC.COUT
Info:  0.2  3.7    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[16] budget 0.190000 ns (31,4) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_13_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  3.8  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_13_LC.COUT
Info:  0.0  3.8    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[17] budget 0.000000 ns (31,5) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_12_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  3.9  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_12_LC.COUT
Info:  0.0  3.9    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[18] budget 0.000000 ns (31,5) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_11_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  4.0  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_11_LC.COUT
Info:  0.0  4.0    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[19] budget 0.000000 ns (31,5) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_10_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  4.2  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_10_LC.COUT
Info:  0.0  4.2    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[20] budget 0.000000 ns (31,5) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_8_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  4.3  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_8_LC.COUT
Info:  0.0  4.3    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[21] budget 0.000000 ns (31,5) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_7_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  4.4  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_7_LC.COUT
Info:  0.0  4.4    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[22] budget 0.000000 ns (31,5) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_6_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  4.6  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_6_LC.COUT
Info:  0.0  4.6    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[23] budget 0.000000 ns (31,5) -> (31,5)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_5_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  4.7  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_5_LC.COUT
Info:  0.2  4.9    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[24] budget 0.190000 ns (31,5) -> (31,6)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_4_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  5.0  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_4_LC.COUT
Info:  0.0  5.0    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[25] budget 0.000000 ns (31,6) -> (31,6)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_3_LC.CIN
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.1  5.1  Source pin_led_0.led_0__o_SB_LUT4_I2_O_SB_LUT4_O_3_LC.COUT
Info:  0.3  5.4    Net pin_led_0.led_0__o_SB_LUT4_I2_I3[26] budget 0.260000 ns (31,6) -> (31,6)
Info:                Sink pin_led_0.led_0__o_SB_LUT4_I2_LC.I3
Info:                Defined in:
Info:                  ./01_blinky.py:14
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.3  5.7  Setup pin_led_0.led_0__o_SB_LUT4_I2_LC.I3
Info: 4.3 ns logic, 1.4 ns routing

Info: Critical path report for cross-domain path 'posedge cd_sync_clk100_0__i' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source pin_led_0.led_0__o_SB_LUT4_I2_LC.O
Info:  1.6  2.2    Net pin_led_0_led_0__o budget 82.792999 ns (31,6) -> (33,1)
Info:                Sink pin_led_6.led_6_0.D_OUT_0
Info:                Defined in:
Info:                  ./01_blinky.py:11
Info: 0.5 ns logic, 1.6 ns routing

Info: Max frequency for clock 'cd_sync_clk100_0__i': 174.83 MHz (PASS at 100.00 MHz)

Info: Max delay posedge cd_sync_clk100_0__i -> <async>: 2.18 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [  4280,   8142) |************************************************************ 
Info: [  8142,  12004) |********************************+
Info: [ 12004,  15866) | 
Info: [ 15866,  19728) | 
Info: [ 19728,  23590) | 
Info: [ 23590,  27452) | 
Info: [ 27452,  31314) | 
Info: [ 31314,  35176) | 
Info: [ 35176,  39038) | 
Info: [ 39038,  42900) | 
Info: [ 42900,  46762) | 
Info: [ 46762,  50624) | 
Info: [ 50624,  54486) | 
Info: [ 54486,  58348) | 
Info: [ 58348,  62210) | 
Info: [ 62210,  66072) | 
Info: [ 66072,  69934) | 
Info: [ 69934,  73796) | 
Info: [ 73796,  77658) | 
Info: [ 77658,  81520) |******+