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PATCH v10 of the Intel Graphics VM_BIND set, rebased against drm-tip from 2023-04-19
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| 17 Jan 2023 23:16:13 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 00/23] drm/i915/vm_bind: Add VM_BIND functionality | |
| Date: Tue, 17 Jan 2023 23:15:46 -0800 | |
| Message-Id: <20230118071609.17572-1-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
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| DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM | |
| buffer objects (BOs) or sections of a BOs at specified GPU virtual | |
| addresses on a specified address space (VM). Multiple mappings can map | |
| to the same physical pages of an object (aliasing). These mappings (also | |
| referred to as persistent mappings) will be persistent across multiple | |
| GPU submissions (execbuf calls) issued by the UMD, without user having | |
| to provide a list of all required mappings during each submission (as | |
| required by older execbuf mode). | |
| This patch series support VM_BIND version 1, as described by the param | |
| I915_PARAM_VM_BIND_VERSION. | |
| Add new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only works in | |
| vm_bind mode. The vm_bind mode only works with this new execbuf3 ioctl. | |
| The new execbuf3 ioctl will not have any execlist support and all the | |
| legacy support like relocations etc., are removed. | |
| NOTEs: | |
| * It is based on below VM_BIND design+uapi rfc. | |
| Documentation/gpu/rfc/i915_vm_bind.rst | |
| * The IGT RFC series is posted as, | |
| [PATCH i-g-t v10 0/19] vm_bind: Add VM_BIND validation support | |
| v2: Address various review comments | |
| v3: Address review comments and other fixes | |
| v4: Remove vm_unbind out fence uapi which is not supported yet, | |
| replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode() | |
| v5: Render kernel-doc, use PIN_NOEVICT, limit vm_bind support to | |
| non-recoverable faults | |
| v6: Rebased, minor fixes, add reserved fields to drm_i915_gem_vm_bind, | |
| add new patch for async vm_unbind support | |
| v7: Rebased, minor cleanups as per review feedback | |
| v8: Rebased, add capture support | |
| v9: Address capture support feedback from v8 | |
| v10: Properly handle vma->resource for mappings with capture request | |
| Test-with: 20230118071350.17498-1-niranjana.vishwanathapura@intel.com | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Niranjana Vishwanathapura (23): | |
| drm/i915/vm_bind: Expose vm lookup function | |
| drm/i915/vm_bind: Add __i915_sw_fence_await_reservation() | |
| drm/i915/vm_bind: Expose i915_gem_object_max_page_size() | |
| drm/i915/vm_bind: Support partially mapped vma resource | |
| drm/i915/vm_bind: Add support to create persistent vma | |
| drm/i915/vm_bind: Implement bind and unbind of object | |
| drm/i915/vm_bind: Support for VM private BOs | |
| drm/i915/vm_bind: Add support to handle object evictions | |
| drm/i915/vm_bind: Support persistent vma activeness tracking | |
| drm/i915/vm_bind: Add out fence support | |
| drm/i915/vm_bind: Abstract out common execbuf functions | |
| drm/i915/vm_bind: Use common execbuf functions in execbuf path | |
| drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl | |
| drm/i915/vm_bind: Update i915_vma_verify_bind_complete() | |
| drm/i915/vm_bind: Expose i915_request_await_bind() | |
| drm/i915/vm_bind: Handle persistent vmas in execbuf3 | |
| drm/i915/vm_bind: userptr dma-resv changes | |
| drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts | |
| drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode | |
| drm/i915/vm_bind: Render VM_BIND documentation | |
| drm/i915/vm_bind: Async vm_unbind support | |
| drm/i915/vm_bind: Properly build persistent map sg table | |
| drm/i915/vm_bind: Support capture of persistent mappings | |
| Documentation/gpu/i915.rst | 78 +- | |
| drivers/gpu/drm/i915/Makefile | 3 + | |
| drivers/gpu/drm/i915/gem/i915_gem_context.c | 43 +- | |
| drivers/gpu/drm/i915/gem/i915_gem_context.h | 17 + | |
| drivers/gpu/drm/i915/gem/i915_gem_create.c | 72 +- | |
| drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 6 + | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 522 +---------- | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 872 ++++++++++++++++++ | |
| .../drm/i915/gem/i915_gem_execbuffer_common.c | 671 ++++++++++++++ | |
| .../drm/i915/gem/i915_gem_execbuffer_common.h | 76 ++ | |
| drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 2 + | |
| drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 + | |
| drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 + | |
| .../gpu/drm/i915/gem/i915_gem_object_types.h | 6 + | |
| drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 19 + | |
| drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 30 + | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 463 ++++++++++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.c | 22 + | |
| drivers/gpu/drm/i915/gt/intel_gtt.h | 28 + | |
| drivers/gpu/drm/i915/i915_driver.c | 4 + | |
| drivers/gpu/drm/i915/i915_drv.h | 2 + | |
| drivers/gpu/drm/i915/i915_gem.c | 14 +- | |
| drivers/gpu/drm/i915/i915_gem_gtt.c | 39 + | |
| drivers/gpu/drm/i915/i915_gem_gtt.h | 3 + | |
| drivers/gpu/drm/i915/i915_getparam.c | 3 + | |
| drivers/gpu/drm/i915/i915_gpu_error.c | 48 +- | |
| drivers/gpu/drm/i915/i915_sw_fence.c | 28 +- | |
| drivers/gpu/drm/i915/i915_sw_fence.h | 23 +- | |
| drivers/gpu/drm/i915/i915_vma.c | 301 +++++- | |
| drivers/gpu/drm/i915/i915_vma.h | 70 +- | |
| drivers/gpu/drm/i915/i915_vma_types.h | 43 + | |
| include/uapi/drm/i915_drm.h | 281 +++++- | |
| 32 files changed, 3245 insertions(+), 553 deletions(-) | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| by smtp.lore.kernel.org (Postfix) with ESMTPS id D6B54C38159 | |
| for <dri-devel@archiver.kernel.org>; Wed, 18 Jan 2023 07:16:53 +0000 (UTC) | |
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| 17 Jan 2023 23:16:14 -0800 | |
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| by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:13 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 01/23] drm/i915/vm_bind: Expose vm lookup function | |
| Date: Tue, 17 Jan 2023 23:15:47 -0800 | |
| Message-Id: <20230118071609.17572-2-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
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| Make i915_gem_vm_lookup() function non-static as it will be | |
| used by the vm_bind feature. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++++++++++- | |
| drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 +++ | |
| 2 files changed, 13 insertions(+), 1 deletion(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| index 46e71f62fcec..b90901ad6866 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| @@ -346,7 +346,16 @@ static int proto_context_register(struct drm_i915_file_private *fpriv, | |
| return ret; | |
| } | |
| -static struct i915_address_space * | |
| +/** | |
| + * i915_gem_vm_lookup() - looks up for the VM reference given the vm id | |
| + * @file_priv: the private data associated with the user's file | |
| + * @id: the VM id | |
| + * | |
| + * Finds the VM reference associated to a specific id. | |
| + * | |
| + * Returns the VM pointer on success, NULL in case of failure. | |
| + */ | |
| +struct i915_address_space * | |
| i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
| { | |
| struct i915_address_space *vm; | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| index e5b0f66ea1fe..899fa8f1e0fe 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| @@ -139,6 +139,9 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
| int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, | |
| struct drm_file *file); | |
| +struct i915_address_space * | |
| +i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id); | |
| + | |
| struct i915_gem_context * | |
| i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id); | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| 17 Jan 2023 23:16:13 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 02/23] drm/i915/vm_bind: Add | |
| __i915_sw_fence_await_reservation() | |
| Date: Tue, 17 Jan 2023 23:15:48 -0800 | |
| Message-Id: <20230118071609.17572-3-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Add function __i915_sw_fence_await_reservation() for | |
| asynchronous wait on a dma-resv object with specified | |
| dma_resv_usage. This is required for async vma unbind | |
| with vm_bind. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| drivers/gpu/drm/i915/i915_sw_fence.c | 28 +++++++++++++++++++++------- | |
| drivers/gpu/drm/i915/i915_sw_fence.h | 23 +++++++++++++++++------ | |
| 2 files changed, 38 insertions(+), 13 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c | |
| index cc2a8821d22a..ae06d35db056 100644 | |
| --- a/drivers/gpu/drm/i915/i915_sw_fence.c | |
| +++ b/drivers/gpu/drm/i915/i915_sw_fence.c | |
| @@ -7,7 +7,6 @@ | |
| #include <linux/slab.h> | |
| #include <linux/dma-fence.h> | |
| #include <linux/irq_work.h> | |
| -#include <linux/dma-resv.h> | |
| #include "i915_sw_fence.h" | |
| #include "i915_selftest.h" | |
| @@ -569,11 +568,26 @@ int __i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, | |
| return ret; | |
| } | |
| -int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, | |
| - struct dma_resv *resv, | |
| - bool write, | |
| - unsigned long timeout, | |
| - gfp_t gfp) | |
| +/** | |
| + * __i915_sw_fence_await_reservation() - Setup a fence to wait on a dma-resv | |
| + * object with specified usage. | |
| + * @fence: the fence that needs to wait | |
| + * @resv: dma-resv object | |
| + * @usage: dma_resv_usage (See enum dma_resv_usage) | |
| + * @timeout: how long to wait in jiffies | |
| + * @gfp: allocation mode | |
| + * | |
| + * Setup the @fence to asynchronously wait on dma-resv object @resv for | |
| + * @usage to complete before signaling. | |
| + * | |
| + * Returns 0 if there is nothing to wait on, -ve error code upon error | |
| + * and >0 upon successfully setting up the wait. | |
| + */ | |
| +int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence, | |
| + struct dma_resv *resv, | |
| + enum dma_resv_usage usage, | |
| + unsigned long timeout, | |
| + gfp_t gfp) | |
| { | |
| struct dma_resv_iter cursor; | |
| struct dma_fence *f; | |
| @@ -582,7 +596,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, | |
| debug_fence_assert(fence); | |
| might_sleep_if(gfpflags_allow_blocking(gfp)); | |
| - dma_resv_iter_begin(&cursor, resv, dma_resv_usage_rw(write)); | |
| + dma_resv_iter_begin(&cursor, resv, usage); | |
| dma_resv_for_each_fence_unlocked(&cursor, f) { | |
| pending = i915_sw_fence_await_dma_fence(fence, f, timeout, | |
| gfp); | |
| diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h b/drivers/gpu/drm/i915/i915_sw_fence.h | |
| index f752bfc7c6e1..9c4859dc4c0d 100644 | |
| --- a/drivers/gpu/drm/i915/i915_sw_fence.h | |
| +++ b/drivers/gpu/drm/i915/i915_sw_fence.h | |
| @@ -10,13 +10,13 @@ | |
| #define _I915_SW_FENCE_H_ | |
| #include <linux/dma-fence.h> | |
| +#include <linux/dma-resv.h> | |
| #include <linux/gfp.h> | |
| #include <linux/kref.h> | |
| #include <linux/notifier.h> /* for NOTIFY_DONE */ | |
| #include <linux/wait.h> | |
| struct completion; | |
| -struct dma_resv; | |
| struct i915_sw_fence; | |
| enum i915_sw_fence_notify { | |
| @@ -89,11 +89,22 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, | |
| unsigned long timeout, | |
| gfp_t gfp); | |
| -int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, | |
| - struct dma_resv *resv, | |
| - bool write, | |
| - unsigned long timeout, | |
| - gfp_t gfp); | |
| +int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence, | |
| + struct dma_resv *resv, | |
| + enum dma_resv_usage usage, | |
| + unsigned long timeout, | |
| + gfp_t gfp); | |
| + | |
| +static inline int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, | |
| + struct dma_resv *resv, | |
| + bool write, | |
| + unsigned long timeout, | |
| + gfp_t gfp) | |
| +{ | |
| + return __i915_sw_fence_await_reservation(fence, resv, | |
| + dma_resv_usage_rw(write), | |
| + timeout, gfp); | |
| +} | |
| bool i915_sw_fence_await(struct i915_sw_fence *fence); | |
| void i915_sw_fence_complete(struct i915_sw_fence *fence); | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| by smtp.lore.kernel.org (Postfix) with ESMTPS id DDFBEC32793 | |
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| by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:14 -0800 | |
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| by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:13 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 03/23] drm/i915/vm_bind: Expose | |
| i915_gem_object_max_page_size() | |
| Date: Tue, 17 Jan 2023 23:15:49 -0800 | |
| Message-Id: <20230118071609.17572-4-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
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| Expose i915_gem_object_max_page_size() function non-static | |
| which will be used by the vm_bind feature. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/gem/i915_gem_create.c | 18 +++++++++++++----- | |
| drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 ++ | |
| 2 files changed, 15 insertions(+), 5 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c | |
| index 005a7f842784..86469710bd59 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c | |
| @@ -16,10 +16,18 @@ | |
| #include "i915_trace.h" | |
| #include "i915_user_extensions.h" | |
| -static u32 object_max_page_size(struct intel_memory_region **placements, | |
| - unsigned int n_placements) | |
| +/** | |
| + * i915_gem_object_max_page_size() - max of min_page_size of the regions | |
| + * @placements: list of regions | |
| + * @n_placements: number of the placements | |
| + * | |
| + * Returns the largest of min_page_size of the @placements, | |
| + * or I915_GTT_PAGE_SIZE_4K if @n_placements is 0. | |
| + */ | |
| +u32 i915_gem_object_max_page_size(struct intel_memory_region **placements, | |
| + unsigned int n_placements) | |
| { | |
| - u32 max_page_size = 0; | |
| + u32 max_page_size = I915_GTT_PAGE_SIZE_4K; | |
| int i; | |
| for (i = 0; i < n_placements; i++) { | |
| @@ -29,7 +37,6 @@ static u32 object_max_page_size(struct intel_memory_region **placements, | |
| max_page_size = max_t(u32, max_page_size, mr->min_page_size); | |
| } | |
| - GEM_BUG_ON(!max_page_size); | |
| return max_page_size; | |
| } | |
| @@ -100,7 +107,8 @@ __i915_gem_object_create_user_ext(struct drm_i915_private *i915, u64 size, | |
| i915_gem_flush_free_objects(i915); | |
| - size = round_up(size, object_max_page_size(placements, n_placements)); | |
| + size = round_up(size, i915_gem_object_max_page_size(placements, | |
| + n_placements)); | |
| if (size == 0) | |
| return ERR_PTR(-EINVAL); | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h | |
| index 3db53769864c..5455ca0eabe9 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h | |
| @@ -31,6 +31,8 @@ static inline bool i915_gem_object_size_2big(u64 size) | |
| } | |
| void i915_gem_init__objects(struct drm_i915_private *i915); | |
| +u32 i915_gem_object_max_page_size(struct intel_memory_region **placements, | |
| + unsigned int n_placements); | |
| void i915_objects_module_exit(void); | |
| int i915_objects_module_init(void); | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
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| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 04/23] drm/i915/vm_bind: Support partially mapped vma | |
| resource | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
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| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| As persistent vmas can be partialled mapped to an object, | |
| remove restriction which require vma resource sg table to | |
| be just pointer to object's sg table. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| drivers/gpu/drm/i915/i915_vma.c | 3 +-- | |
| 1 file changed, 1 insertion(+), 2 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 34f0e6c923c2..79b2e19a299f 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -2062,8 +2062,7 @@ static struct dma_fence *__i915_vma_unbind_async(struct i915_vma *vma) | |
| if (!drm_mm_node_allocated(&vma->node)) | |
| return NULL; | |
| - if (i915_vma_is_pinned(vma) || | |
| - &vma->obj->mm.rsgt->table != vma->resource->bi.pages) | |
| + if (i915_vma_is_pinned(vma)) | |
| return ERR_PTR(-EAGAIN); | |
| /* | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| 17 Jan 2023 23:16:14 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 05/23] drm/i915/vm_bind: Add support to create persistent | |
| vma | |
| Date: Tue, 17 Jan 2023 23:15:51 -0800 | |
| Message-Id: <20230118071609.17572-6-niranjana.vishwanathapura@intel.com> | |
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| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
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| Add i915_vma_instance_persistent() to create persistent vmas. | |
| Persistent vmas will use i915_gtt_view to support partial binding. | |
| vma_lookup is tied to segment of the object instead of section | |
| of VA space. Hence, it do not support aliasing. ie., multiple | |
| mappings (at different VA) point to the same gtt_view of object. | |
| Skip vma_lookup for persistent vmas to support aliasing. | |
| v2: Remove unused I915_VMA_PERSISTENT definition, | |
| update validity check in i915_vma_compare(), | |
| remove unwanted is_persistent check in release_references(). | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/i915_vma.c | 36 +++++++++++++++++++++++++-- | |
| drivers/gpu/drm/i915/i915_vma.h | 17 ++++++++++++- | |
| drivers/gpu/drm/i915/i915_vma_types.h | 6 +++++ | |
| 3 files changed, 56 insertions(+), 3 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 79b2e19a299f..e43cbb5fa154 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -112,7 +112,8 @@ static void __i915_vma_retire(struct i915_active *ref) | |
| static struct i915_vma * | |
| vma_create(struct drm_i915_gem_object *obj, | |
| struct i915_address_space *vm, | |
| - const struct i915_gtt_view *view) | |
| + const struct i915_gtt_view *view, | |
| + bool skip_lookup_cache) | |
| { | |
| struct i915_vma *pos = ERR_PTR(-E2BIG); | |
| struct i915_vma *vma; | |
| @@ -199,6 +200,9 @@ vma_create(struct drm_i915_gem_object *obj, | |
| __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma)); | |
| } | |
| + if (skip_lookup_cache) | |
| + goto skip_rb_insert; | |
| + | |
| rb = NULL; | |
| p = &obj->vma.tree.rb_node; | |
| while (*p) { | |
| @@ -223,6 +227,7 @@ vma_create(struct drm_i915_gem_object *obj, | |
| rb_link_node(&vma->obj_node, rb, p); | |
| rb_insert_color(&vma->obj_node, &obj->vma.tree); | |
| +skip_rb_insert: | |
| if (i915_vma_is_ggtt(vma)) | |
| /* | |
| * We put the GGTT vma at the start of the vma-list, followed | |
| @@ -302,7 +307,34 @@ i915_vma_instance(struct drm_i915_gem_object *obj, | |
| /* vma_create() will resolve the race if another creates the vma */ | |
| if (unlikely(!vma)) | |
| - vma = vma_create(obj, vm, view); | |
| + vma = vma_create(obj, vm, view, false); | |
| + | |
| + GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view)); | |
| + return vma; | |
| +} | |
| + | |
| +/** | |
| + * i915_vma_create_persistent - create a persistent VMA | |
| + * @obj: parent &struct drm_i915_gem_object to be mapped | |
| + * @vm: address space in which the mapping is located | |
| + * @view: additional mapping requirements | |
| + * | |
| + * Creates a persistent vma. | |
| + * | |
| + * Returns the vma, or an error pointer. | |
| + */ | |
| +struct i915_vma * | |
| +i915_vma_create_persistent(struct drm_i915_gem_object *obj, | |
| + struct i915_address_space *vm, | |
| + const struct i915_gtt_view *view) | |
| +{ | |
| + struct i915_vma *vma; | |
| + | |
| + GEM_BUG_ON(!kref_read(&vm->ref)); | |
| + | |
| + vma = vma_create(obj, vm, view, true); | |
| + if (!IS_ERR(vma)) | |
| + i915_vma_set_persistent(vma); | |
| GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view)); | |
| return vma; | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h | |
| index ed5c9d682a1b..dd9951a41ff3 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma.h | |
| @@ -44,6 +44,10 @@ struct i915_vma * | |
| i915_vma_instance(struct drm_i915_gem_object *obj, | |
| struct i915_address_space *vm, | |
| const struct i915_gtt_view *view); | |
| +struct i915_vma * | |
| +i915_vma_create_persistent(struct drm_i915_gem_object *obj, | |
| + struct i915_address_space *vm, | |
| + const struct i915_gtt_view *view); | |
| void i915_vma_unpin_and_release(struct i915_vma **p_vma, unsigned int flags); | |
| #define I915_VMA_RELEASE_MAP BIT(0) | |
| @@ -185,6 +189,16 @@ static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma) | |
| return i915_vm_to_ggtt(vma->vm)->pin_bias; | |
| } | |
| +static inline bool i915_vma_is_persistent(const struct i915_vma *vma) | |
| +{ | |
| + return test_bit(I915_VMA_PERSISTENT_BIT, __i915_vma_flags(vma)); | |
| +} | |
| + | |
| +static inline void i915_vma_set_persistent(struct i915_vma *vma) | |
| +{ | |
| + set_bit(I915_VMA_PERSISTENT_BIT, __i915_vma_flags(vma)); | |
| +} | |
| + | |
| static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) | |
| { | |
| i915_gem_object_get(vma->obj); | |
| @@ -211,7 +225,8 @@ i915_vma_compare(struct i915_vma *vma, | |
| { | |
| ptrdiff_t cmp; | |
| - GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm)); | |
| + GEM_BUG_ON(view && !(i915_is_ggtt_or_dpt(vm) || | |
| + i915_vma_is_persistent(vma))); | |
| cmp = ptrdiff(vma->vm, vm); | |
| if (cmp) | |
| diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h | |
| index 77fda2244d16..be1cd76304cb 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma_types.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma_types.h | |
| @@ -265,6 +265,12 @@ struct i915_vma { | |
| #define I915_VMA_SCANOUT_BIT 17 | |
| #define I915_VMA_SCANOUT ((int)BIT(I915_VMA_SCANOUT_BIT)) | |
| +/** | |
| + * I915_VMA_PERSISTENT_BIT: | |
| + * The vma is persistent (created with VM_BIND call). | |
| + */ | |
| +#define I915_VMA_PERSISTENT_BIT 19 | |
| + | |
| struct i915_active active; | |
| #define I915_VMA_PAGES_BIAS 24 | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 06/23] drm/i915/vm_bind: Implement bind and unbind of | |
| object | |
| Date: Tue, 17 Jan 2023 23:15:52 -0800 | |
| Message-Id: <20230118071609.17572-7-niranjana.vishwanathapura@intel.com> | |
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| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
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| Add uapi and implement support for bind and unbind of an | |
| object at the specified GPU virtual addresses. | |
| The vm_bind mode is not supported in legacy execbuf2 ioctl. | |
| It will be supported only in the newer execbuf3 ioctl. | |
| v2: On older platforms ctx->vm is not set, check for it. | |
| In vm_bind call, add vma to vm_bind_list. | |
| Add more input validity checks. | |
| Update some documentation. | |
| v3: In vm_bind call, add vma to vm_bound_list as user can | |
| request a fence and pass to execbuf3 as input fence. | |
| Remove short term pinning with PIN_VALIDATE flag. | |
| v4: Replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode(). | |
| v5: Ensure all reserved fields are 0, use PIN_NOEVICT. | |
| v6: Add reserved fields to drm_i915_gem_vm_bind. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/Makefile | 1 + | |
| drivers/gpu/drm/i915/gem/i915_gem_context.h | 15 + | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 5 + | |
| drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 26 ++ | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 330 ++++++++++++++++++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.c | 10 + | |
| drivers/gpu/drm/i915/gt/intel_gtt.h | 9 + | |
| drivers/gpu/drm/i915/i915_driver.c | 3 + | |
| drivers/gpu/drm/i915/i915_vma.c | 1 + | |
| drivers/gpu/drm/i915/i915_vma_types.h | 14 + | |
| include/uapi/drm/i915_drm.h | 105 ++++++ | |
| 11 files changed, 519 insertions(+) | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile | |
| index f47f00b162a4..fc3ed0aea034 100644 | |
| --- a/drivers/gpu/drm/i915/Makefile | |
| +++ b/drivers/gpu/drm/i915/Makefile | |
| @@ -172,6 +172,7 @@ gem-y += \ | |
| gem/i915_gem_ttm_move.o \ | |
| gem/i915_gem_ttm_pm.o \ | |
| gem/i915_gem_userptr.o \ | |
| + gem/i915_gem_vm_bind_object.o \ | |
| gem/i915_gem_wait.o \ | |
| gem/i915_gemfs.o | |
| i915-y += \ | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| index 899fa8f1e0fe..e8b41aa8f8c4 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| @@ -139,6 +139,21 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
| int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, | |
| struct drm_file *file); | |
| +/** | |
| + * i915_gem_vm_is_vm_bind_mode() - Check if address space is in vm_bind mode | |
| + * @vm: the address space | |
| + * | |
| + * Returns: | |
| + * true: @vm is in vm_bind mode; allows only vm_bind method of binding. | |
| + * false: @vm is not in vm_bind mode; allows only legacy execbuff method | |
| + * of binding. | |
| + */ | |
| +static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm) | |
| +{ | |
| + /* No support to enable vm_bind mode yet */ | |
| + return false; | |
| +} | |
| + | |
| struct i915_address_space * | |
| i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id); | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| index 192bb3f10733..6456f15448bd 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| @@ -822,6 +822,11 @@ static int eb_select_context(struct i915_execbuffer *eb) | |
| if (unlikely(IS_ERR(ctx))) | |
| return PTR_ERR(ctx); | |
| + if (ctx->vm && i915_gem_vm_is_vm_bind_mode(ctx->vm)) { | |
| + i915_gem_context_put(ctx); | |
| + return -EOPNOTSUPP; | |
| + } | |
| + | |
| eb->gem_context = ctx; | |
| if (i915_gem_context_has_full_ppgtt(ctx)) | |
| eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | |
| new file mode 100644 | |
| index 000000000000..36262a6357b5 | |
| --- /dev/null | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | |
| @@ -0,0 +1,26 @@ | |
| +/* SPDX-License-Identifier: MIT */ | |
| +/* | |
| + * Copyright © 2022 Intel Corporation | |
| + */ | |
| + | |
| +#ifndef __I915_GEM_VM_BIND_H | |
| +#define __I915_GEM_VM_BIND_H | |
| + | |
| +#include <linux/types.h> | |
| + | |
| +struct drm_device; | |
| +struct drm_file; | |
| +struct i915_address_space; | |
| +struct i915_vma; | |
| + | |
| +struct i915_vma * | |
| +i915_gem_vm_bind_lookup_vma(struct i915_address_space *vm, u64 va); | |
| + | |
| +int i915_gem_vm_bind_ioctl(struct drm_device *dev, void *data, | |
| + struct drm_file *file); | |
| +int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void *data, | |
| + struct drm_file *file); | |
| + | |
| +void i915_gem_vm_unbind_all(struct i915_address_space *vm); | |
| + | |
| +#endif /* __I915_GEM_VM_BIND_H */ | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| new file mode 100644 | |
| index 000000000000..5064aba9ab87 | |
| --- /dev/null | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| @@ -0,0 +1,330 @@ | |
| +// SPDX-License-Identifier: MIT | |
| +/* | |
| + * Copyright © 2022 Intel Corporation | |
| + */ | |
| + | |
| +#include <uapi/drm/i915_drm.h> | |
| + | |
| +#include <linux/interval_tree_generic.h> | |
| + | |
| +#include "gem/i915_gem_context.h" | |
| +#include "gem/i915_gem_vm_bind.h" | |
| + | |
| +#include "gt/intel_gpu_commands.h" | |
| + | |
| +#define START(node) ((node)->start) | |
| +#define LAST(node) ((node)->last) | |
| + | |
| +/* Not all defined functions are used, hence use __maybe_unused */ | |
| +INTERVAL_TREE_DEFINE(struct i915_vma, rb, u64, __subtree_last, | |
| + START, LAST, __maybe_unused static inline, i915_vm_bind_it) | |
| + | |
| +#undef START | |
| +#undef LAST | |
| + | |
| +/** | |
| + * DOC: VM_BIND/UNBIND ioctls | |
| + * | |
| + * DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM buffer | |
| + * objects (BOs) or sections of a BOs at specified GPU virtual addresses on a | |
| + * specified address space (VM). Multiple mappings can map to the same physical | |
| + * pages of an object (aliasing). These mappings (also referred to as persistent | |
| + * mappings) will be persistent across multiple GPU submissions (execbuf calls) | |
| + * issued by the UMD, without user having to provide a list of all required | |
| + * mappings during each submission (as required by older execbuf mode). | |
| + * | |
| + * The VM_BIND/UNBIND calls allow UMDs to request a timeline out fence for | |
| + * signaling the completion of bind/unbind operation. | |
| + * | |
| + * VM_BIND feature is advertised to user via I915_PARAM_VM_BIND_VERSION. | |
| + * User has to opt-in for VM_BIND mode of binding for an address space (VM) | |
| + * during VM creation time via I915_VM_CREATE_FLAGS_USE_VM_BIND extension. | |
| + * | |
| + * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently | |
| + * are not ordered. Furthermore, parts of the VM_BIND/UNBIND operations can be | |
| + * done asynchronously, when valid out fence is specified. | |
| + * | |
| + * VM_BIND locking order is as below. | |
| + * | |
| + * 1) vm_bind_lock mutex will protect vm_bind lists. This lock is taken in | |
| + * vm_bind/vm_unbind ioctl calls, in the execbuf path and while releasing the | |
| + * mapping. | |
| + * | |
| + * In future, when GPU page faults are supported, we can potentially use a | |
| + * rwsem instead, so that multiple page fault handlers can take the read | |
| + * side lock to lookup the mapping and hence can run in parallel. | |
| + * The older execbuf mode of binding do not need this lock. | |
| + * | |
| + * 2) The object's dma-resv lock will protect i915_vma state and needs | |
| + * to be held while binding/unbinding a vma in the async worker and while | |
| + * updating dma-resv fence list of an object. Note that private BOs of a VM | |
| + * will all share a dma-resv object. | |
| + * | |
| + * 3) Spinlock/s to protect some of the VM's lists like the list of | |
| + * invalidated vmas (due to eviction and userptr invalidation) etc. | |
| + */ | |
| + | |
| +/** | |
| + * i915_gem_vm_bind_lookup_vma() - lookup for persistent vma mapped at a | |
| + * specified address | |
| + * @vm: virtual address space to look for persistent vma | |
| + * @va: starting address where vma is mapped | |
| + * | |
| + * Retrieves the persistent vma mapped address @va from the @vm's vma tree. | |
| + * | |
| + * Returns vma pointer on success, NULL on failure. | |
| + */ | |
| +struct i915_vma * | |
| +i915_gem_vm_bind_lookup_vma(struct i915_address_space *vm, u64 va) | |
| +{ | |
| + lockdep_assert_held(&vm->vm_bind_lock); | |
| + | |
| + return i915_vm_bind_it_iter_first(&vm->va, va, va); | |
| +} | |
| + | |
| +static void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj) | |
| +{ | |
| + lockdep_assert_held(&vma->vm->vm_bind_lock); | |
| + | |
| + list_del_init(&vma->vm_bind_link); | |
| + i915_vm_bind_it_remove(vma, &vma->vm->va); | |
| + | |
| + /* Release object */ | |
| + if (release_obj) | |
| + i915_gem_object_put(vma->obj); | |
| +} | |
| + | |
| +static int i915_gem_vm_unbind_vma(struct i915_address_space *vm, | |
| + struct drm_i915_gem_vm_unbind *va) | |
| +{ | |
| + struct drm_i915_gem_object *obj; | |
| + struct i915_vma *vma; | |
| + int ret; | |
| + | |
| + ret = mutex_lock_interruptible(&vm->vm_bind_lock); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + va->start = gen8_noncanonical_addr(va->start); | |
| + vma = i915_gem_vm_bind_lookup_vma(vm, va->start); | |
| + | |
| + if (!vma) | |
| + ret = -ENOENT; | |
| + else if (vma->size != va->length) | |
| + ret = -EINVAL; | |
| + | |
| + if (ret) { | |
| + mutex_unlock(&vm->vm_bind_lock); | |
| + return ret; | |
| + } | |
| + | |
| + i915_gem_vm_bind_remove(vma, false); | |
| + | |
| + mutex_unlock(&vm->vm_bind_lock); | |
| + | |
| + /* | |
| + * Destroy the vma and then release the object. | |
| + * As persistent vma holds object reference, it can only be destroyed | |
| + * either by vm_unbind ioctl or when VM is being released. As we are | |
| + * holding VM reference here, it is safe accessing the vma here. | |
| + */ | |
| + obj = vma->obj; | |
| + i915_gem_object_lock(obj, NULL); | |
| + i915_vma_destroy(vma); | |
| + i915_gem_object_unlock(obj); | |
| + | |
| + i915_gem_object_put(obj); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/** | |
| + * i915_gem_vm_unbind_all() - unbind all persistent mappings from an | |
| + * address space | |
| + * @vm: Address spece to remove persistent mappings from | |
| + * | |
| + * Unbind all userspace requested vm_bind mappings from @vm. | |
| + */ | |
| +void i915_gem_vm_unbind_all(struct i915_address_space *vm) | |
| +{ | |
| + struct i915_vma *vma, *t; | |
| + | |
| + mutex_lock(&vm->vm_bind_lock); | |
| + list_for_each_entry_safe(vma, t, &vm->vm_bind_list, vm_bind_link) | |
| + i915_gem_vm_bind_remove(vma, true); | |
| + list_for_each_entry_safe(vma, t, &vm->vm_bound_list, vm_bind_link) | |
| + i915_gem_vm_bind_remove(vma, true); | |
| + mutex_unlock(&vm->vm_bind_lock); | |
| +} | |
| + | |
| +static struct i915_vma *vm_bind_get_vma(struct i915_address_space *vm, | |
| + struct drm_i915_gem_object *obj, | |
| + struct drm_i915_gem_vm_bind *va) | |
| +{ | |
| + struct i915_gtt_view view; | |
| + struct i915_vma *vma; | |
| + | |
| + va->start = gen8_noncanonical_addr(va->start); | |
| + vma = i915_gem_vm_bind_lookup_vma(vm, va->start); | |
| + if (vma) | |
| + return ERR_PTR(-EEXIST); | |
| + | |
| + view.type = I915_GTT_VIEW_PARTIAL; | |
| + view.partial.offset = va->offset >> PAGE_SHIFT; | |
| + view.partial.size = va->length >> PAGE_SHIFT; | |
| + vma = i915_vma_create_persistent(obj, vm, &view); | |
| + if (IS_ERR(vma)) | |
| + return vma; | |
| + | |
| + vma->start = va->start; | |
| + vma->last = va->start + va->length - 1; | |
| + | |
| + return vma; | |
| +} | |
| + | |
| +static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| + struct drm_i915_gem_vm_bind *va, | |
| + struct drm_file *file) | |
| +{ | |
| + struct drm_i915_gem_object *obj; | |
| + struct i915_vma *vma = NULL; | |
| + struct i915_gem_ww_ctx ww; | |
| + u64 pin_flags; | |
| + int ret = 0; | |
| + | |
| + if (!i915_gem_vm_is_vm_bind_mode(vm)) | |
| + return -EOPNOTSUPP; | |
| + | |
| + /* Ensure start and length fields are valid */ | |
| + if (!va->length || !IS_ALIGNED(va->start, I915_GTT_PAGE_SIZE)) | |
| + ret = -EINVAL; | |
| + | |
| + obj = i915_gem_object_lookup(file, va->handle); | |
| + if (!obj) | |
| + return -ENOENT; | |
| + | |
| + /* Ensure offset and length are aligned to object's max page size */ | |
| + if (!IS_ALIGNED(va->offset | va->length, | |
| + i915_gem_object_max_page_size(obj->mm.placements, | |
| + obj->mm.n_placements))) | |
| + ret = -EINVAL; | |
| + | |
| + /* Check for mapping range overflow */ | |
| + if (range_overflows_t(u64, va->offset, va->length, obj->base.size)) | |
| + ret = -EINVAL; | |
| + | |
| + if (ret) | |
| + goto put_obj; | |
| + | |
| + ret = mutex_lock_interruptible(&vm->vm_bind_lock); | |
| + if (ret) | |
| + goto put_obj; | |
| + | |
| + vma = vm_bind_get_vma(vm, obj, va); | |
| + if (IS_ERR(vma)) { | |
| + ret = PTR_ERR(vma); | |
| + goto unlock_vm; | |
| + } | |
| + | |
| + pin_flags = va->start | PIN_OFFSET_FIXED | PIN_USER | | |
| + PIN_VALIDATE | PIN_NOEVICT; | |
| + | |
| + for_i915_gem_ww(&ww, ret, true) { | |
| + ret = i915_gem_object_lock(vma->obj, &ww); | |
| + if (ret) | |
| + continue; | |
| + | |
| + ret = i915_vma_pin_ww(vma, &ww, 0, 0, pin_flags); | |
| + if (ret) | |
| + continue; | |
| + | |
| + /* Wait for bind to complete */ | |
| + ret = i915_vma_wait_for_bind(vma); | |
| + if (ret) | |
| + continue; | |
| + | |
| + list_add_tail(&vma->vm_bind_link, &vm->vm_bound_list); | |
| + i915_vm_bind_it_insert(vma, &vm->va); | |
| + | |
| + /* Hold object reference until vm_unbind */ | |
| + i915_gem_object_get(vma->obj); | |
| + } | |
| + | |
| + if (ret) | |
| + i915_vma_destroy(vma); | |
| +unlock_vm: | |
| + mutex_unlock(&vm->vm_bind_lock); | |
| +put_obj: | |
| + i915_gem_object_put(obj); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +/** | |
| + * i915_gem_vm_bind_ioctl() - ioctl function for binding a section of object | |
| + * at a specified virtual address | |
| + * @dev: drm_device pointer | |
| + * @data: ioctl data structure | |
| + * @file: drm_file pointer | |
| + * | |
| + * Adds the specified persistent mapping (virtual address to a section of an | |
| + * object) and binds it in the device page table. | |
| + * | |
| + * Returns 0 on success, error code on failure. | |
| + */ | |
| +int i915_gem_vm_bind_ioctl(struct drm_device *dev, void *data, | |
| + struct drm_file *file) | |
| +{ | |
| + struct drm_i915_gem_vm_bind *args = data; | |
| + struct i915_address_space *vm; | |
| + int ret; | |
| + | |
| + /* Reserved fields must be 0 */ | |
| + if ((args->flags & __I915_GEM_VM_BIND_UNKNOWN_FLAGS) || | |
| + args->rsvd[0] || args->rsvd[1] || args->extensions) | |
| + return -EINVAL; | |
| + | |
| + vm = i915_gem_vm_lookup(file->driver_priv, args->vm_id); | |
| + if (unlikely(!vm)) | |
| + return -ENOENT; | |
| + | |
| + ret = i915_gem_vm_bind_obj(vm, args, file); | |
| + | |
| + i915_vm_put(vm); | |
| + return ret; | |
| +} | |
| + | |
| +/** | |
| + * i915_gem_vm_unbind_ioctl() - ioctl function for unbinding a mapping at a | |
| + * specified virtual address | |
| + * @dev: drm_device pointer | |
| + * @data: ioctl data structure | |
| + * @file: drm_file pointer | |
| + * | |
| + * Removes the persistent mapping at the specified address and unbinds it | |
| + * from the device page table. | |
| + * | |
| + * Returns 0 on success, error code on failure. -ENOENT is returned if the | |
| + * specified mapping is not found. | |
| + */ | |
| +int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void *data, | |
| + struct drm_file *file) | |
| +{ | |
| + struct drm_i915_gem_vm_unbind *args = data; | |
| + struct i915_address_space *vm; | |
| + int ret; | |
| + | |
| + /* Reserved fields must be 0 */ | |
| + if ((args->flags & __I915_GEM_VM_UNBIND_UNKNOWN_FLAGS) || | |
| + args->pad || args->rsvd[0] || args->rsvd[1] || args->extensions) | |
| + return -EINVAL; | |
| + | |
| + vm = i915_gem_vm_lookup(file->driver_priv, args->vm_id); | |
| + if (unlikely(!vm)) | |
| + return -ENOENT; | |
| + | |
| + ret = i915_gem_vm_unbind_vma(vm, args); | |
| + | |
| + i915_vm_put(vm); | |
| + return ret; | |
| +} | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| index e37164a60d37..3d61204f7e1e 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| @@ -12,6 +12,7 @@ | |
| #include "gem/i915_gem_internal.h" | |
| #include "gem/i915_gem_lmem.h" | |
| +#include "gem/i915_gem_vm_bind.h" | |
| #include "i915_reg.h" | |
| #include "i915_trace.h" | |
| #include "i915_utils.h" | |
| @@ -179,6 +180,8 @@ int i915_vm_lock_objects(struct i915_address_space *vm, | |
| void i915_address_space_fini(struct i915_address_space *vm) | |
| { | |
| drm_mm_takedown(&vm->mm); | |
| + GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root)); | |
| + mutex_destroy(&vm->vm_bind_lock); | |
| } | |
| /** | |
| @@ -205,6 +208,8 @@ static void __i915_vm_release(struct work_struct *work) | |
| struct i915_address_space *vm = | |
| container_of(work, struct i915_address_space, release_work); | |
| + i915_gem_vm_unbind_all(vm); | |
| + | |
| __i915_vm_close(vm); | |
| /* Synchronize async unbinds. */ | |
| @@ -281,6 +286,11 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) | |
| INIT_LIST_HEAD(&vm->bound_list); | |
| INIT_LIST_HEAD(&vm->unbound_list); | |
| + | |
| + vm->va = RB_ROOT_CACHED; | |
| + INIT_LIST_HEAD(&vm->vm_bind_list); | |
| + INIT_LIST_HEAD(&vm->vm_bound_list); | |
| + mutex_init(&vm->vm_bind_lock); | |
| } | |
| void *__px_vaddr(struct drm_i915_gem_object *p) | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| index 5a775310d3fc..88c54a85f22c 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| @@ -260,6 +260,15 @@ struct i915_address_space { | |
| */ | |
| struct list_head unbound_list; | |
| + /** @vm_bind_lock: Mutex to protect @vm_bind_list and @vm_bound_list */ | |
| + struct mutex vm_bind_lock; | |
| + /** @vm_bind_list: List of vm_binding in process */ | |
| + struct list_head vm_bind_list; | |
| + /** @vm_bound_list: List of vm_binding completed */ | |
| + struct list_head vm_bound_list; | |
| + /** @va: tree of persistent vmas */ | |
| + struct rb_root_cached va; | |
| + | |
| /* Global GTT */ | |
| bool is_ggtt:1; | |
| diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c | |
| index c1e427ba57ae..fdc9c55829e8 100644 | |
| --- a/drivers/gpu/drm/i915/i915_driver.c | |
| +++ b/drivers/gpu/drm/i915/i915_driver.c | |
| @@ -69,6 +69,7 @@ | |
| #include "gem/i915_gem_ioctls.h" | |
| #include "gem/i915_gem_mman.h" | |
| #include "gem/i915_gem_pm.h" | |
| +#include "gem/i915_gem_vm_bind.h" | |
| #include "gt/intel_gt.h" | |
| #include "gt/intel_gt_pm.h" | |
| #include "gt/intel_rc6.h" | |
| @@ -1771,6 +1772,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = { | |
| DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), | |
| DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), | |
| DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), | |
| + DRM_IOCTL_DEF_DRV(I915_GEM_VM_BIND, i915_gem_vm_bind_ioctl, DRM_RENDER_ALLOW), | |
| + DRM_IOCTL_DEF_DRV(I915_GEM_VM_UNBIND, i915_gem_vm_unbind_ioctl, DRM_RENDER_ALLOW), | |
| }; | |
| /* | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index e43cbb5fa154..ba24deaa87dc 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -242,6 +242,7 @@ vma_create(struct drm_i915_gem_object *obj, | |
| spin_unlock(&obj->vma.lock); | |
| mutex_unlock(&vm->mutex); | |
| + INIT_LIST_HEAD(&vma->vm_bind_link); | |
| return vma; | |
| err_unlock: | |
| diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h | |
| index be1cd76304cb..5fadcd9d4282 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma_types.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma_types.h | |
| @@ -296,6 +296,20 @@ struct i915_vma { | |
| /** This object's place on the active/inactive lists */ | |
| struct list_head vm_link; | |
| + /** @vm_bind_link: node for the vm_bind related lists of vm */ | |
| + struct list_head vm_bind_link; | |
| + | |
| + /** Interval tree structures for persistent vma */ | |
| + | |
| + /** @rb: node for the interval tree of vm for persistent vmas */ | |
| + struct rb_node rb; | |
| + /** @start: start endpoint of the rb node */ | |
| + u64 start; | |
| + /** @last: Last endpoint of the rb node */ | |
| + u64 last; | |
| + /** @__subtree_last: last in subtree */ | |
| + u64 __subtree_last; | |
| + | |
| struct list_head obj_link; /* Link in the object's VMA list */ | |
| struct rb_node obj_node; | |
| struct hlist_node obj_hash; | |
| diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h | |
| index 8df261c5ab9b..6bb00ece001a 100644 | |
| --- a/include/uapi/drm/i915_drm.h | |
| +++ b/include/uapi/drm/i915_drm.h | |
| @@ -470,6 +470,8 @@ typedef struct _drm_i915_sarea { | |
| #define DRM_I915_GEM_VM_CREATE 0x3a | |
| #define DRM_I915_GEM_VM_DESTROY 0x3b | |
| #define DRM_I915_GEM_CREATE_EXT 0x3c | |
| +#define DRM_I915_GEM_VM_BIND 0x3d | |
| +#define DRM_I915_GEM_VM_UNBIND 0x3e | |
| /* Must be kept compact -- no holes */ | |
| #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
| @@ -534,6 +536,8 @@ typedef struct _drm_i915_sarea { | |
| #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) | |
| #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) | |
| #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) | |
| +#define DRM_IOCTL_I915_GEM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_BIND, struct drm_i915_gem_vm_bind) | |
| +#define DRM_IOCTL_I915_GEM_VM_UNBIND DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_UNBIND, struct drm_i915_gem_vm_unbind) | |
| /* Allow drivers to submit batchbuffers directly to hardware, relying | |
| * on the security mechanisms provided by hardware. | |
| @@ -3750,6 +3754,107 @@ struct drm_i915_gem_create_ext_protected_content { | |
| /* ID of the protected content session managed by i915 when PXP is active */ | |
| #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf | |
| +/** | |
| + * struct drm_i915_gem_vm_bind - VA to object mapping to bind. | |
| + * | |
| + * This structure is passed to VM_BIND ioctl and specifies the mapping of GPU | |
| + * virtual address (VA) range to the section of an object that should be bound | |
| + * in the device page table of the specified address space (VM). | |
| + * The VA range specified must be unique (ie., not currently bound) and can | |
| + * be mapped to whole object or a section of the object (partial binding). | |
| + * Multiple VA mappings can be created to the same section of the object | |
| + * (aliasing). | |
| + * | |
| + * The @start, @offset and @length must be 4K page aligned. However the DG2 | |
| + * and XEHPSDV has 64K page size for device local memory and has compact page | |
| + * table. On those platforms, for binding device local-memory objects, the | |
| + * @start, @offset and @length must be 64K aligned. | |
| + * | |
| + * Error code -EINVAL will be returned if @start, @offset and @length are not | |
| + * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code | |
| + * -ENOSPC will be returned if the VA range specified can't be reserved. | |
| + * | |
| + * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently | |
| + * are not ordered. | |
| + */ | |
| +struct drm_i915_gem_vm_bind { | |
| + /** @vm_id: VM (address space) id to bind */ | |
| + __u32 vm_id; | |
| + | |
| + /** @handle: Object handle */ | |
| + __u32 handle; | |
| + | |
| + /** @start: Virtual Address start to bind */ | |
| + __u64 start; | |
| + | |
| + /** @offset: Offset in object to bind */ | |
| + __u64 offset; | |
| + | |
| + /** @length: Length of mapping to bind */ | |
| + __u64 length; | |
| + | |
| + /** @flags: Currently reserved, MBZ. */ | |
| + __u64 flags; | |
| +#define __I915_GEM_VM_BIND_UNKNOWN_FLAGS (~0ull) | |
| + | |
| + /** @rsvd: Reserved, MBZ */ | |
| + __u64 rsvd[2]; | |
| + | |
| + /** @rsvd2: Reserved for timeline fence */ | |
| + __u64 rsvd2[2]; | |
| + | |
| + /** | |
| + * @extensions: Zero-terminated chain of extensions. | |
| + * | |
| + * For future extensions. See struct i915_user_extension. | |
| + */ | |
| + __u64 extensions; | |
| +}; | |
| + | |
| +/** | |
| + * struct drm_i915_gem_vm_unbind - VA to object mapping to unbind. | |
| + * | |
| + * This structure is passed to VM_UNBIND ioctl and specifies the GPU virtual | |
| + * address (VA) range that should be unbound from the device page table of the | |
| + * specified address space (VM). VM_UNBIND will force unbind the specified | |
| + * range from device page table without waiting for any GPU job to complete. | |
| + * It is UMDs responsibility to ensure the mapping is no longer in use before | |
| + * calling VM_UNBIND. | |
| + * | |
| + * If the specified mapping is not found, the ioctl will simply return without | |
| + * any error. | |
| + * | |
| + * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently | |
| + * are not ordered. | |
| + */ | |
| +struct drm_i915_gem_vm_unbind { | |
| + /** @vm_id: VM (address space) id to bind */ | |
| + __u32 vm_id; | |
| + | |
| + /** @pad: padding, MBZ */ | |
| + __u32 pad; | |
| + | |
| + /** @start: Virtual Address start to unbind */ | |
| + __u64 start; | |
| + | |
| + /** @length: Length of mapping to unbind */ | |
| + __u64 length; | |
| + | |
| + /** @flags: Currently reserved, MBZ. */ | |
| + __u64 flags; | |
| +#define __I915_GEM_VM_UNBIND_UNKNOWN_FLAGS (~0ull) | |
| + | |
| + /** @rsvd: Reserved, MBZ */ | |
| + __u64 rsvd[2]; | |
| + | |
| + /** | |
| + * @extensions: Zero-terminated chain of extensions. | |
| + * | |
| + * For future extensions. See struct i915_user_extension. | |
| + */ | |
| + __u64 extensions; | |
| +}; | |
| + | |
| #if defined(__cplusplus) | |
| } | |
| #endif | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 07/23] drm/i915/vm_bind: Support for VM private BOs | |
| Date: Tue, 17 Jan 2023 23:15:53 -0800 | |
| Message-Id: <20230118071609.17572-8-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Each VM creates a root_obj and shares it with all of its private objects | |
| to use it as dma_resv object. This has a performance advantage as it | |
| requires a single dma_resv object update for all private BOs vs list of | |
| dma_resv objects update for shared BOs, in the execbuf path. | |
| VM private BOs can be only mapped on specified VM and cannot be dmabuf | |
| exported. Also, they are supported only in vm_bind mode. | |
| v2: Pad struct drm_i915_gem_create_ext_vm_private for 64bit alignment, | |
| add input validity checks. | |
| v3: Create root_obj only for ppgtt. | |
| v4: Fix releasing of obj->priv_root. Do not create vm->root_obj yet. | |
| Allow vm private object creation only in vm_bind mode. | |
| Replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode(). | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + | |
| drivers/gpu/drm/i915/gem/i915_gem_create.c | 54 ++++++++++++++++++- | |
| drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 6 +++ | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++ | |
| drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 ++ | |
| .../gpu/drm/i915/gem/i915_gem_object_types.h | 6 +++ | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 9 ++++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.c | 1 + | |
| drivers/gpu/drm/i915/gt/intel_gtt.h | 4 ++ | |
| drivers/gpu/drm/i915/i915_vma.c | 1 + | |
| drivers/gpu/drm/i915/i915_vma_types.h | 2 + | |
| include/uapi/drm/i915_drm.h | 33 ++++++++++++ | |
| 12 files changed, 122 insertions(+), 2 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| index b90901ad6866..fb4d2dab5053 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| @@ -83,6 +83,7 @@ | |
| #include "i915_file_private.h" | |
| #include "i915_gem_context.h" | |
| +#include "i915_gem_internal.h" | |
| #include "i915_trace.h" | |
| #include "i915_user_extensions.h" | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c | |
| index 86469710bd59..717403c79226 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c | |
| @@ -12,6 +12,7 @@ | |
| #include "pxp/intel_pxp.h" | |
| #include "i915_drv.h" | |
| +#include "i915_gem_context.h" | |
| #include "i915_gem_create.h" | |
| #include "i915_trace.h" | |
| #include "i915_user_extensions.h" | |
| @@ -253,6 +254,7 @@ struct create_ext { | |
| unsigned int n_placements; | |
| unsigned int placement_mask; | |
| unsigned long flags; | |
| + u32 vm_id; | |
| }; | |
| static void repr_placements(char *buf, size_t size, | |
| @@ -402,9 +404,32 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data | |
| return 0; | |
| } | |
| +static int ext_set_vm_private(struct i915_user_extension __user *base, | |
| + void *data) | |
| +{ | |
| + struct drm_i915_gem_create_ext_vm_private ext; | |
| + struct create_ext *ext_data = data; | |
| + | |
| + if (copy_from_user(&ext, base, sizeof(ext))) | |
| + return -EFAULT; | |
| + | |
| + /* Reserved fields must be 0 */ | |
| + if (ext.rsvd) | |
| + return -EINVAL; | |
| + | |
| + /* vm_id 0 is reserved */ | |
| + if (!ext.vm_id) | |
| + return -ENOENT; | |
| + | |
| + ext_data->vm_id = ext.vm_id; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| static const i915_user_extension_fn create_extensions[] = { | |
| [I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements, | |
| [I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected, | |
| + [I915_GEM_CREATE_EXT_VM_PRIVATE] = ext_set_vm_private, | |
| }; | |
| /** | |
| @@ -420,6 +445,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, | |
| struct drm_i915_private *i915 = to_i915(dev); | |
| struct drm_i915_gem_create_ext *args = data; | |
| struct create_ext ext_data = { .i915 = i915 }; | |
| + struct i915_address_space *vm = NULL; | |
| struct drm_i915_gem_object *obj; | |
| int ret; | |
| @@ -433,6 +459,17 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, | |
| if (ret) | |
| return ret; | |
| + if (ext_data.vm_id) { | |
| + vm = i915_gem_vm_lookup(file->driver_priv, ext_data.vm_id); | |
| + if (unlikely(!vm)) | |
| + return -ENOENT; | |
| + | |
| + if (!i915_gem_vm_is_vm_bind_mode(vm)) { | |
| + ret = -EINVAL; | |
| + goto vm_put; | |
| + } | |
| + } | |
| + | |
| if (!ext_data.n_placements) { | |
| ext_data.placements[0] = | |
| intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM); | |
| @@ -459,8 +496,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, | |
| ext_data.placements, | |
| ext_data.n_placements, | |
| ext_data.flags); | |
| - if (IS_ERR(obj)) | |
| - return PTR_ERR(obj); | |
| + if (IS_ERR(obj)) { | |
| + ret = PTR_ERR(obj); | |
| + goto vm_put; | |
| + } | |
| + | |
| + if (vm) { | |
| + obj->base.resv = vm->root_obj->base.resv; | |
| + obj->priv_root = i915_gem_object_get(vm->root_obj); | |
| + i915_vm_put(vm); | |
| + } | |
| return i915_gem_publish(obj, file, &args->size, &args->handle); | |
| +vm_put: | |
| + if (vm) | |
| + i915_vm_put(vm); | |
| + | |
| + return ret; | |
| } | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | |
| index fd556a076d05..ff9c167f3b71 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | |
| @@ -221,6 +221,12 @@ struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags) | |
| struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
| DEFINE_DMA_BUF_EXPORT_INFO(exp_info); | |
| + if (obj->priv_root) { | |
| + drm_dbg(obj->base.dev, | |
| + "Exporting VM private objects is not allowed\n"); | |
| + return ERR_PTR(-EINVAL); | |
| + } | |
| + | |
| exp_info.ops = &i915_dmabuf_ops; | |
| exp_info.size = gem_obj->size; | |
| exp_info.flags = flags; | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| index 6456f15448bd..6a7f0227f65f 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| @@ -905,6 +905,10 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) | |
| if (unlikely(!obj)) | |
| return ERR_PTR(-ENOENT); | |
| + /* VM private objects are not supported here */ | |
| + if (obj->priv_root) | |
| + return ERR_PTR(-EINVAL); | |
| + | |
| /* | |
| * If the user has opted-in for protected-object tracking, make | |
| * sure the object encryption can be used. | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c | |
| index 733696057761..2abef7e5af81 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c | |
| @@ -111,6 +111,9 @@ void __i915_gem_object_fini(struct drm_i915_gem_object *obj) | |
| mutex_destroy(&obj->mm.get_page.lock); | |
| mutex_destroy(&obj->mm.get_dma_page.lock); | |
| dma_resv_fini(&obj->base._resv); | |
| + | |
| + if (obj->priv_root) | |
| + i915_gem_object_put(obj->priv_root); | |
| } | |
| /** | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h | |
| index a7b70701617a..1a41a2526a04 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h | |
| @@ -242,6 +242,12 @@ struct drm_i915_gem_object { | |
| const struct drm_i915_gem_object_ops *ops; | |
| + /** | |
| + * @priv_root: pointer to vm->root_obj if object is private, | |
| + * NULL otherwise. | |
| + */ | |
| + struct drm_i915_gem_object *priv_root; | |
| + | |
| struct { | |
| /** | |
| * @vma.lock: protect the list/tree of vmas | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| index 5064aba9ab87..4f9df4b756d2 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| @@ -87,6 +87,7 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj) | |
| lockdep_assert_held(&vma->vm->vm_bind_lock); | |
| list_del_init(&vma->vm_bind_link); | |
| + list_del_init(&vma->non_priv_vm_bind_link); | |
| i915_vm_bind_it_remove(vma, &vma->vm->va); | |
| /* Release object */ | |
| @@ -216,6 +217,11 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| if (ret) | |
| goto put_obj; | |
| + if (obj->priv_root && obj->priv_root != vm->root_obj) { | |
| + ret = -EINVAL; | |
| + goto put_obj; | |
| + } | |
| + | |
| ret = mutex_lock_interruptible(&vm->vm_bind_lock); | |
| if (ret) | |
| goto put_obj; | |
| @@ -245,6 +251,9 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| list_add_tail(&vma->vm_bind_link, &vm->vm_bound_list); | |
| i915_vm_bind_it_insert(vma, &vm->va); | |
| + if (!obj->priv_root) | |
| + list_add_tail(&vma->non_priv_vm_bind_link, | |
| + &vm->non_priv_vm_bind_list); | |
| /* Hold object reference until vm_unbind */ | |
| i915_gem_object_get(vma->obj); | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| index 3d61204f7e1e..7ce0237d664f 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| @@ -291,6 +291,7 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) | |
| INIT_LIST_HEAD(&vm->vm_bind_list); | |
| INIT_LIST_HEAD(&vm->vm_bound_list); | |
| mutex_init(&vm->vm_bind_lock); | |
| + INIT_LIST_HEAD(&vm->non_priv_vm_bind_list); | |
| } | |
| void *__px_vaddr(struct drm_i915_gem_object *p) | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| index 88c54a85f22c..cb87d0e925c7 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| @@ -268,6 +268,10 @@ struct i915_address_space { | |
| struct list_head vm_bound_list; | |
| /** @va: tree of persistent vmas */ | |
| struct rb_root_cached va; | |
| + /** @non_priv_vm_bind_list: list of non-private object mappings */ | |
| + struct list_head non_priv_vm_bind_list; | |
| + /** @root_obj: root object for dma-resv sharing by private objects */ | |
| + struct drm_i915_gem_object *root_obj; | |
| /* Global GTT */ | |
| bool is_ggtt:1; | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index ba24deaa87dc..30f0c0aca007 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -243,6 +243,7 @@ vma_create(struct drm_i915_gem_object *obj, | |
| mutex_unlock(&vm->mutex); | |
| INIT_LIST_HEAD(&vma->vm_bind_link); | |
| + INIT_LIST_HEAD(&vma->non_priv_vm_bind_link); | |
| return vma; | |
| err_unlock: | |
| diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h | |
| index 5fadcd9d4282..e081ffcb3250 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma_types.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma_types.h | |
| @@ -298,6 +298,8 @@ struct i915_vma { | |
| /** @vm_bind_link: node for the vm_bind related lists of vm */ | |
| struct list_head vm_bind_link; | |
| + /** @non_priv_vm_bind_link: Link in non-private persistent VMA list */ | |
| + struct list_head non_priv_vm_bind_link; | |
| /** Interval tree structures for persistent vma */ | |
| diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h | |
| index 6bb00ece001a..683da7099311 100644 | |
| --- a/include/uapi/drm/i915_drm.h | |
| +++ b/include/uapi/drm/i915_drm.h | |
| @@ -3634,9 +3634,13 @@ struct drm_i915_gem_create_ext { | |
| * | |
| * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see | |
| * struct drm_i915_gem_create_ext_protected_content. | |
| + * | |
| + * For I915_GEM_CREATE_EXT_VM_PRIVATE usage see | |
| + * struct drm_i915_gem_create_ext_vm_private. | |
| */ | |
| #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 | |
| #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 | |
| +#define I915_GEM_CREATE_EXT_VM_PRIVATE 2 | |
| __u64 extensions; | |
| }; | |
| @@ -3754,6 +3758,35 @@ struct drm_i915_gem_create_ext_protected_content { | |
| /* ID of the protected content session managed by i915 when PXP is active */ | |
| #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf | |
| +/** | |
| + * struct drm_i915_gem_create_ext_vm_private - Extension to make the object | |
| + * private to the specified VM. | |
| + * | |
| + * See struct drm_i915_gem_create_ext. | |
| + * | |
| + * By default, BOs can be mapped on multiple VMs and can also be dma-buf | |
| + * exported. Hence these BOs are referred to as Shared BOs. | |
| + * During each execbuf3 submission, the request fence must be added to the | |
| + * dma-resv fence list of all shared BOs mapped on the VM. | |
| + * | |
| + * Unlike Shared BOs, these VM private BOs can only be mapped on the VM they | |
| + * are private to and can't be dma-buf exported. All private BOs of a VM share | |
| + * the dma-resv object. Hence during each execbuf3 submission, they need only | |
| + * one dma-resv fence list updated. Thus, the fast path (where required | |
| + * mappings are already bound) submission latency is O(1) w.r.t the number of | |
| + * VM private BOs. | |
| + */ | |
| +struct drm_i915_gem_create_ext_vm_private { | |
| + /** @base: Extension link. See struct i915_user_extension. */ | |
| + struct i915_user_extension base; | |
| + | |
| + /** @vm_id: Id of the VM to which Object is private */ | |
| + __u32 vm_id; | |
| + | |
| + /** @rsvd: Reserved, MBZ */ | |
| + __u32 rsvd; | |
| +}; | |
| + | |
| /** | |
| * struct drm_i915_gem_vm_bind - VA to object mapping to bind. | |
| * | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 08/23] drm/i915/vm_bind: Add support to handle object | |
| evictions | |
| Date: Tue, 17 Jan 2023 23:15:54 -0800 | |
| Message-Id: <20230118071609.17572-9-niranjana.vishwanathapura@intel.com> | |
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| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
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| Support eviction by maintaining a list of evicted persistent vmas | |
| for rebinding during next submission. Ensure the list do not | |
| include persistent vmas that are being purged. | |
| v2: Remove unused I915_VMA_PURGED definition. | |
| v3: Properly handle __i915_vma_unbind_async() case. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 6 ++++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.c | 2 ++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.h | 4 +++ | |
| drivers/gpu/drm/i915/i915_vma.c | 28 +++++++++++++++++++ | |
| drivers/gpu/drm/i915/i915_vma.h | 10 +++++++ | |
| drivers/gpu/drm/i915/i915_vma_types.h | 8 ++++++ | |
| 6 files changed, 58 insertions(+) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| index 4f9df4b756d2..dc738677466b 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| @@ -86,6 +86,12 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj) | |
| { | |
| lockdep_assert_held(&vma->vm->vm_bind_lock); | |
| + spin_lock(&vma->vm->vm_rebind_lock); | |
| + if (!list_empty(&vma->vm_rebind_link)) | |
| + list_del_init(&vma->vm_rebind_link); | |
| + i915_vma_set_purged(vma); | |
| + spin_unlock(&vma->vm->vm_rebind_lock); | |
| + | |
| list_del_init(&vma->vm_bind_link); | |
| list_del_init(&vma->non_priv_vm_bind_link); | |
| i915_vm_bind_it_remove(vma, &vma->vm->va); | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| index 7ce0237d664f..4f91857dca46 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| @@ -292,6 +292,8 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) | |
| INIT_LIST_HEAD(&vm->vm_bound_list); | |
| mutex_init(&vm->vm_bind_lock); | |
| INIT_LIST_HEAD(&vm->non_priv_vm_bind_list); | |
| + INIT_LIST_HEAD(&vm->vm_rebind_list); | |
| + spin_lock_init(&vm->vm_rebind_lock); | |
| } | |
| void *__px_vaddr(struct drm_i915_gem_object *p) | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| index cb87d0e925c7..dbe6792df3e5 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| @@ -266,6 +266,10 @@ struct i915_address_space { | |
| struct list_head vm_bind_list; | |
| /** @vm_bound_list: List of vm_binding completed */ | |
| struct list_head vm_bound_list; | |
| + /** @vm_rebind_list: list of vmas to be rebinded */ | |
| + struct list_head vm_rebind_list; | |
| + /** @vm_rebind_lock: protects vm_rebound_list */ | |
| + spinlock_t vm_rebind_lock; | |
| /** @va: tree of persistent vmas */ | |
| struct rb_root_cached va; | |
| /** @non_priv_vm_bind_list: list of non-private object mappings */ | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 30f0c0aca007..353203bd5685 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -244,6 +244,7 @@ vma_create(struct drm_i915_gem_object *obj, | |
| INIT_LIST_HEAD(&vma->vm_bind_link); | |
| INIT_LIST_HEAD(&vma->non_priv_vm_bind_link); | |
| + INIT_LIST_HEAD(&vma->vm_rebind_link); | |
| return vma; | |
| err_unlock: | |
| @@ -1718,6 +1719,14 @@ static void force_unbind(struct i915_vma *vma) | |
| if (!drm_mm_node_allocated(&vma->node)) | |
| return; | |
| + /* | |
| + * Persistent vma should have been purged by now. | |
| + * If not, issue a warning and purge it. | |
| + */ | |
| + if (GEM_WARN_ON(i915_vma_is_persistent(vma) && | |
| + !i915_vma_is_purged(vma))) | |
| + i915_vma_set_purged(vma); | |
| + | |
| atomic_and(~I915_VMA_PIN_MASK, &vma->flags); | |
| WARN_ON(__i915_vma_unbind(vma)); | |
| GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); | |
| @@ -2084,6 +2093,16 @@ int __i915_vma_unbind(struct i915_vma *vma) | |
| __i915_vma_evict(vma, false); | |
| drm_mm_remove_node(&vma->node); /* pairs with i915_vma_release() */ | |
| + | |
| + if (i915_vma_is_persistent(vma)) { | |
| + spin_lock(&vma->vm->vm_rebind_lock); | |
| + if (list_empty(&vma->vm_rebind_link) && | |
| + !i915_vma_is_purged(vma)) | |
| + list_add_tail(&vma->vm_rebind_link, | |
| + &vma->vm->vm_rebind_list); | |
| + spin_unlock(&vma->vm->vm_rebind_lock); | |
| + } | |
| + | |
| return 0; | |
| } | |
| @@ -2118,6 +2137,15 @@ static struct dma_fence *__i915_vma_unbind_async(struct i915_vma *vma) | |
| drm_mm_remove_node(&vma->node); /* pairs with i915_vma_release() */ | |
| + if (i915_vma_is_persistent(vma)) { | |
| + spin_lock(&vma->vm->vm_rebind_lock); | |
| + if (list_empty(&vma->vm_rebind_link) && | |
| + !i915_vma_is_purged(vma)) | |
| + list_add_tail(&vma->vm_rebind_link, | |
| + &vma->vm->vm_rebind_list); | |
| + spin_unlock(&vma->vm->vm_rebind_lock); | |
| + } | |
| + | |
| return fence; | |
| } | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h | |
| index dd9951a41ff3..7b1bf5ba4f12 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma.h | |
| @@ -199,6 +199,16 @@ static inline void i915_vma_set_persistent(struct i915_vma *vma) | |
| set_bit(I915_VMA_PERSISTENT_BIT, __i915_vma_flags(vma)); | |
| } | |
| +static inline bool i915_vma_is_purged(const struct i915_vma *vma) | |
| +{ | |
| + return test_bit(I915_VMA_PURGED_BIT, __i915_vma_flags(vma)); | |
| +} | |
| + | |
| +static inline void i915_vma_set_purged(struct i915_vma *vma) | |
| +{ | |
| + set_bit(I915_VMA_PURGED_BIT, __i915_vma_flags(vma)); | |
| +} | |
| + | |
| static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) | |
| { | |
| i915_gem_object_get(vma->obj); | |
| diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h | |
| index e081ffcb3250..6b1cce537846 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma_types.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma_types.h | |
| @@ -268,8 +268,14 @@ struct i915_vma { | |
| /** | |
| * I915_VMA_PERSISTENT_BIT: | |
| * The vma is persistent (created with VM_BIND call). | |
| + * | |
| + * I915_VMA_PURGED_BIT: | |
| + * The persistent vma is force unbound either due to VM_UNBIND call | |
| + * from UMD or VM is released. Do not check/wait for VM activeness | |
| + * in i915_vma_is_active() and i915_vma_sync() calls. | |
| */ | |
| #define I915_VMA_PERSISTENT_BIT 19 | |
| +#define I915_VMA_PURGED_BIT 20 | |
| struct i915_active active; | |
| @@ -300,6 +306,8 @@ struct i915_vma { | |
| struct list_head vm_bind_link; | |
| /** @non_priv_vm_bind_link: Link in non-private persistent VMA list */ | |
| struct list_head non_priv_vm_bind_link; | |
| + /** @vm_rebind_link: link to vm_rebind_list and protected by vm_rebind_lock */ | |
| + struct list_head vm_rebind_link; /* Link in vm_rebind_list */ | |
| /** Interval tree structures for persistent vma */ | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| 17 Jan 2023 23:16:14 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 09/23] drm/i915/vm_bind: Support persistent vma activeness | |
| tracking | |
| Date: Tue, 17 Jan 2023 23:15:55 -0800 | |
| Message-Id: <20230118071609.17572-10-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
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| Do not use i915_vma activeness tracking for persistent vmas. | |
| As persistent vmas are part of working set for each execbuf | |
| submission on that address space (VM), a persistent vma is | |
| active if the VM active. As vm->root_obj->base.resv will be | |
| updated for each submission on that VM, it correctly | |
| represent whether the VM is active or not. | |
| Add i915_vm_is_active() and i915_vm_sync() functions based | |
| on vm->root_obj->base.resv with DMA_RESV_USAGE_BOOKKEEP | |
| usage. dma-resv fence list will be updated with this usage | |
| during each submission with this VM in the new execbuf3 | |
| ioctl path. | |
| Update i915_vma_is_active(), i915_vma_sync() and the | |
| __i915_vma_unbind_async() functions to properly handle | |
| persistent vmas. | |
| v2: Ensure lvalue of dma_resv_wait_timeout() call is long. | |
| v3: Do not await for purged vmas to become idle during | |
| async unbind | |
| Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +++++++++++++++++++++++++++++ | |
| drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +++ | |
| drivers/gpu/drm/i915/i915_vma.c | 28 +++++++++++++++++++++ | |
| drivers/gpu/drm/i915/i915_vma.h | 25 +++++++++--------- | |
| 4 files changed, 83 insertions(+), 12 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c | |
| index 7bd1861ddbdf..1d8506548d4a 100644 | |
| --- a/drivers/gpu/drm/i915/i915_gem_gtt.c | |
| +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |
| @@ -25,6 +25,45 @@ | |
| #include "i915_trace.h" | |
| #include "i915_vgpu.h" | |
| +/** | |
| + * i915_vm_sync() - Wait until address space is not in use | |
| + * @vm: address space | |
| + * | |
| + * Waits until all requests using the address space are complete. | |
| + * | |
| + * Returns: 0 if success, -ve err code upon failure | |
| + */ | |
| +int i915_vm_sync(struct i915_address_space *vm) | |
| +{ | |
| + long ret; | |
| + | |
| + /* Wait for all requests under this vm to finish */ | |
| + ret = dma_resv_wait_timeout(vm->root_obj->base.resv, | |
| + DMA_RESV_USAGE_BOOKKEEP, false, | |
| + MAX_SCHEDULE_TIMEOUT); | |
| + if (ret < 0) | |
| + return ret; | |
| + else if (ret > 0) | |
| + return 0; | |
| + else | |
| + return -ETIMEDOUT; | |
| +} | |
| + | |
| +/** | |
| + * i915_vm_is_active() - Check if address space is being used | |
| + * @vm: address space | |
| + * | |
| + * Check if any request using the specified address space is | |
| + * active. | |
| + * | |
| + * Returns: true if address space is active, false otherwise. | |
| + */ | |
| +bool i915_vm_is_active(const struct i915_address_space *vm) | |
| +{ | |
| + return !dma_resv_test_signaled(vm->root_obj->base.resv, | |
| + DMA_RESV_USAGE_BOOKKEEP); | |
| +} | |
| + | |
| int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, | |
| struct sg_table *pages) | |
| { | |
| diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h | |
| index 243419783052..e62b52c74586 100644 | |
| --- a/drivers/gpu/drm/i915/i915_gem_gtt.h | |
| +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h | |
| @@ -54,4 +54,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm, | |
| #define PIN_OFFSET_MASK I915_GTT_PAGE_MASK | |
| +int i915_vm_sync(struct i915_address_space *vm); | |
| +bool i915_vm_is_active(const struct i915_address_space *vm); | |
| + | |
| #endif | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 353203bd5685..b44fd5f73b64 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -35,6 +35,7 @@ | |
| #include "gt/intel_gt.h" | |
| #include "gt/intel_gt_requests.h" | |
| +#include "i915_config.h" | |
| #include "i915_drv.h" | |
| #include "i915_gem_evict.h" | |
| #include "i915_sw_fence_work.h" | |
| @@ -423,6 +424,24 @@ int i915_vma_wait_for_bind(struct i915_vma *vma) | |
| return err; | |
| } | |
| +/** | |
| + * i915_vma_sync() - Wait for the vma to be idle | |
| + * @vma: vma to be tested | |
| + * | |
| + * Returns 0 on success and error code on failure | |
| + */ | |
| +int i915_vma_sync(struct i915_vma *vma) | |
| +{ | |
| + int ret; | |
| + | |
| + /* Wait for the asynchronous bindings and pending GPU reads */ | |
| + ret = i915_active_wait(&vma->active); | |
| + if (ret || !i915_vma_is_persistent(vma) || i915_vma_is_purged(vma)) | |
| + return ret; | |
| + | |
| + return i915_vm_sync(vma->vm); | |
| +} | |
| + | |
| #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) | |
| static int i915_vma_verify_bind_complete(struct i915_vma *vma) | |
| { | |
| @@ -1921,6 +1938,8 @@ int _i915_vma_move_to_active(struct i915_vma *vma, | |
| int err; | |
| assert_object_held(obj); | |
| + if (i915_vma_is_persistent(vma)) | |
| + return -EINVAL; | |
| GEM_BUG_ON(!vma->pages); | |
| @@ -2134,6 +2154,14 @@ static struct dma_fence *__i915_vma_unbind_async(struct i915_vma *vma) | |
| return ERR_PTR(-EBUSY); | |
| } | |
| + if (i915_vma_is_persistent(vma) && !i915_vma_is_purged(vma) && | |
| + __i915_sw_fence_await_reservation(&vma->resource->chain, | |
| + vma->vm->root_obj->base.resv, | |
| + DMA_RESV_USAGE_BOOKKEEP, | |
| + i915_fence_timeout(vma->vm->i915), | |
| + GFP_NOWAIT | __GFP_NOWARN) < 0) | |
| + return ERR_PTR(-EBUSY); | |
| + | |
| fence = __i915_vma_evict(vma, true); | |
| drm_mm_remove_node(&vma->node); /* pairs with i915_vma_release() */ | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h | |
| index 7b1bf5ba4f12..de1756e4f638 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma.h | |
| @@ -51,12 +51,6 @@ i915_vma_create_persistent(struct drm_i915_gem_object *obj, | |
| void i915_vma_unpin_and_release(struct i915_vma **p_vma, unsigned int flags); | |
| #define I915_VMA_RELEASE_MAP BIT(0) | |
| - | |
| -static inline bool i915_vma_is_active(const struct i915_vma *vma) | |
| -{ | |
| - return !i915_active_is_idle(&vma->active); | |
| -} | |
| - | |
| /* do not reserve memory to prevent deadlocks */ | |
| #define __EXEC_OBJECT_NO_RESERVE BIT(31) | |
| #define __EXEC_OBJECT_NO_REQUEST_AWAIT BIT(30) | |
| @@ -209,6 +203,18 @@ static inline void i915_vma_set_purged(struct i915_vma *vma) | |
| set_bit(I915_VMA_PURGED_BIT, __i915_vma_flags(vma)); | |
| } | |
| +static inline bool i915_vma_is_active(const struct i915_vma *vma) | |
| +{ | |
| + if (i915_vma_is_persistent(vma)) { | |
| + if (i915_vma_is_purged(vma)) | |
| + return false; | |
| + | |
| + return i915_vm_is_active(vma->vm); | |
| + } | |
| + | |
| + return !i915_active_is_idle(&vma->active); | |
| +} | |
| + | |
| static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) | |
| { | |
| i915_gem_object_get(vma->obj); | |
| @@ -480,12 +486,7 @@ void i915_vma_make_shrinkable(struct i915_vma *vma); | |
| void i915_vma_make_purgeable(struct i915_vma *vma); | |
| int i915_vma_wait_for_bind(struct i915_vma *vma); | |
| - | |
| -static inline int i915_vma_sync(struct i915_vma *vma) | |
| -{ | |
| - /* Wait for the asynchronous bindings and pending GPU reads */ | |
| - return i915_active_wait(&vma->active); | |
| -} | |
| +int i915_vma_sync(struct i915_vma *vma); | |
| /** | |
| * i915_vma_get_current_resource - Get the current resource of the vma | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| 17 Jan 2023 23:16:14 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 10/23] drm/i915/vm_bind: Add out fence support | |
| Date: Tue, 17 Jan 2023 23:15:56 -0800 | |
| Message-Id: <20230118071609.17572-11-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
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| Add support for handling out fence for vm_bind call. | |
| v2: Reset vma->vm_bind_fence.syncobj to NULL at the end | |
| of vm_bind call. | |
| v3: Remove vm_unbind out fence uapi which is not supported yet. | |
| v4: Return error if I915_TIMELINE_FENCE_WAIT fence flag is set. | |
| Wait for bind to complete iff I915_TIMELINE_FENCE_SIGNAL is | |
| not specified. | |
| v5: Ensure __I915_TIMELINE_FENCE_UNKNOWN_FLAGS are not set. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 4 + | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 98 ++++++++++++++++++- | |
| drivers/gpu/drm/i915/i915_vma.c | 7 +- | |
| drivers/gpu/drm/i915/i915_vma_types.h | 7 ++ | |
| include/uapi/drm/i915_drm.h | 58 ++++++++++- | |
| 5 files changed, 165 insertions(+), 9 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | |
| index 36262a6357b5..b70e900e35ab 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | |
| @@ -8,6 +8,7 @@ | |
| #include <linux/types.h> | |
| +struct dma_fence; | |
| struct drm_device; | |
| struct drm_file; | |
| struct i915_address_space; | |
| @@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void *data, | |
| void i915_gem_vm_unbind_all(struct i915_address_space *vm); | |
| +void i915_vm_bind_signal_fence(struct i915_vma *vma, | |
| + struct dma_fence * const fence); | |
| + | |
| #endif /* __I915_GEM_VM_BIND_H */ | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| index dc738677466b..fd1d82ce99e6 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| @@ -7,6 +7,8 @@ | |
| #include <linux/interval_tree_generic.h> | |
| +#include <drm/drm_syncobj.h> | |
| + | |
| #include "gem/i915_gem_context.h" | |
| #include "gem/i915_gem_vm_bind.h" | |
| @@ -101,6 +103,77 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj) | |
| i915_gem_object_put(vma->obj); | |
| } | |
| +static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma, | |
| + u32 handle, u64 point) | |
| +{ | |
| + struct drm_syncobj *syncobj; | |
| + | |
| + syncobj = drm_syncobj_find(file, handle); | |
| + if (!syncobj) { | |
| + drm_dbg(&vma->vm->i915->drm, | |
| + "Invalid syncobj handle provided\n"); | |
| + return -ENOENT; | |
| + } | |
| + | |
| + /* | |
| + * For timeline syncobjs we need to preallocate chains for | |
| + * later signaling. | |
| + */ | |
| + if (point) { | |
| + vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc(); | |
| + if (!vma->vm_bind_fence.chain_fence) { | |
| + drm_syncobj_put(syncobj); | |
| + return -ENOMEM; | |
| + } | |
| + } else { | |
| + vma->vm_bind_fence.chain_fence = NULL; | |
| + } | |
| + vma->vm_bind_fence.syncobj = syncobj; | |
| + vma->vm_bind_fence.value = point; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static void i915_vm_bind_put_fence(struct i915_vma *vma) | |
| +{ | |
| + if (!vma->vm_bind_fence.syncobj) | |
| + return; | |
| + | |
| + drm_syncobj_put(vma->vm_bind_fence.syncobj); | |
| + dma_fence_chain_free(vma->vm_bind_fence.chain_fence); | |
| + vma->vm_bind_fence.syncobj = NULL; | |
| +} | |
| + | |
| +/** | |
| + * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj | |
| + * @vma: vma mapping requiring signaling | |
| + * @fence: fence to be added | |
| + * | |
| + * Associate specified @fence with the @vma's syncobj to be | |
| + * signaled after the @fence work completes. | |
| + */ | |
| +void i915_vm_bind_signal_fence(struct i915_vma *vma, | |
| + struct dma_fence * const fence) | |
| +{ | |
| + struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj; | |
| + | |
| + if (!syncobj) | |
| + return; | |
| + | |
| + if (vma->vm_bind_fence.chain_fence) { | |
| + drm_syncobj_add_point(syncobj, | |
| + vma->vm_bind_fence.chain_fence, | |
| + fence, vma->vm_bind_fence.value); | |
| + /* | |
| + * The chain's ownership is transferred to the | |
| + * timeline. | |
| + */ | |
| + vma->vm_bind_fence.chain_fence = NULL; | |
| + } else { | |
| + drm_syncobj_replace_fence(syncobj, fence); | |
| + } | |
| +} | |
| + | |
| static int i915_gem_vm_unbind_vma(struct i915_address_space *vm, | |
| struct drm_i915_gem_vm_unbind *va) | |
| { | |
| @@ -206,6 +279,11 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| if (!va->length || !IS_ALIGNED(va->start, I915_GTT_PAGE_SIZE)) | |
| ret = -EINVAL; | |
| + /* In fences are not supported */ | |
| + if ((va->fence.flags & I915_TIMELINE_FENCE_WAIT) || | |
| + (va->fence.flags & __I915_TIMELINE_FENCE_UNKNOWN_FLAGS)) | |
| + ret = -EINVAL; | |
| + | |
| obj = i915_gem_object_lookup(file, va->handle); | |
| if (!obj) | |
| return -ENOENT; | |
| @@ -238,6 +316,13 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| goto unlock_vm; | |
| } | |
| + if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL) { | |
| + ret = i915_vm_bind_add_fence(file, vma, va->fence.handle, | |
| + va->fence.value); | |
| + if (ret) | |
| + goto put_vma; | |
| + } | |
| + | |
| pin_flags = va->start | PIN_OFFSET_FIXED | PIN_USER | | |
| PIN_VALIDATE | PIN_NOEVICT; | |
| @@ -250,10 +335,12 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| if (ret) | |
| continue; | |
| - /* Wait for bind to complete */ | |
| - ret = i915_vma_wait_for_bind(vma); | |
| - if (ret) | |
| - continue; | |
| + /* If out fence is not requested, wait for bind to complete */ | |
| + if (!(va->fence.flags & I915_TIMELINE_FENCE_SIGNAL)) { | |
| + ret = i915_vma_wait_for_bind(vma); | |
| + if (ret) | |
| + continue; | |
| + } | |
| list_add_tail(&vma->vm_bind_link, &vm->vm_bound_list); | |
| i915_vm_bind_it_insert(vma, &vm->va); | |
| @@ -265,6 +352,9 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| i915_gem_object_get(vma->obj); | |
| } | |
| + if (va->fence.flags & I915_TIMELINE_FENCE_SIGNAL) | |
| + i915_vm_bind_put_fence(vma); | |
| +put_vma: | |
| if (ret) | |
| i915_vma_destroy(vma); | |
| unlock_vm: | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index b44fd5f73b64..763ead20ad55 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -30,6 +30,7 @@ | |
| #include "display/intel_frontbuffer.h" | |
| #include "gem/i915_gem_lmem.h" | |
| #include "gem/i915_gem_tiling.h" | |
| +#include "gem/i915_gem_vm_bind.h" | |
| #include "gt/intel_engine.h" | |
| #include "gt/intel_engine_heartbeat.h" | |
| #include "gt/intel_gt.h" | |
| @@ -1602,8 +1603,12 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, | |
| err_vma_res: | |
| i915_vma_resource_free(vma_res); | |
| err_fence: | |
| - if (work) | |
| + if (work) { | |
| + if (i915_vma_is_persistent(vma)) | |
| + i915_vm_bind_signal_fence(vma, &work->base.dma); | |
| + | |
| dma_fence_work_commit_imm(&work->base); | |
| + } | |
| err_rpm: | |
| if (wakeref) | |
| intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); | |
| diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h | |
| index 6b1cce537846..4c386473923a 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma_types.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma_types.h | |
| @@ -309,6 +309,13 @@ struct i915_vma { | |
| /** @vm_rebind_link: link to vm_rebind_list and protected by vm_rebind_lock */ | |
| struct list_head vm_rebind_link; /* Link in vm_rebind_list */ | |
| + /** Timeline fence for vm_bind completion notification */ | |
| + struct { | |
| + struct dma_fence_chain *chain_fence; | |
| + struct drm_syncobj *syncobj; | |
| + u64 value; | |
| + } vm_bind_fence; | |
| + | |
| /** Interval tree structures for persistent vma */ | |
| /** @rb: node for the interval tree of vm for persistent vmas */ | |
| diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h | |
| index 683da7099311..f35a9bb35ab3 100644 | |
| --- a/include/uapi/drm/i915_drm.h | |
| +++ b/include/uapi/drm/i915_drm.h | |
| @@ -1533,6 +1533,41 @@ struct drm_i915_gem_execbuffer2 { | |
| #define i915_execbuffer2_get_context_id(eb2) \ | |
| ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) | |
| +/** | |
| + * struct drm_i915_gem_timeline_fence - An input or output timeline fence. | |
| + * | |
| + * The operation will wait for input fence to signal. | |
| + * | |
| + * The returned output fence will be signaled after the completion of the | |
| + * operation. | |
| + */ | |
| +struct drm_i915_gem_timeline_fence { | |
| + /** @handle: User's handle for a drm_syncobj to wait on or signal. */ | |
| + __u32 handle; | |
| + | |
| + /** | |
| + * @flags: Supported flags are: | |
| + * | |
| + * I915_TIMELINE_FENCE_WAIT: | |
| + * Wait for the input fence before the operation. | |
| + * | |
| + * I915_TIMELINE_FENCE_SIGNAL: | |
| + * Return operation completion fence as output. | |
| + */ | |
| + __u32 flags; | |
| +#define I915_TIMELINE_FENCE_WAIT (1 << 0) | |
| +#define I915_TIMELINE_FENCE_SIGNAL (1 << 1) | |
| +#define __I915_TIMELINE_FENCE_UNKNOWN_FLAGS (-(I915_TIMELINE_FENCE_SIGNAL << 1)) | |
| + | |
| + /** | |
| + * @value: A point in the timeline. | |
| + * Value must be 0 for a binary drm_syncobj. A Value of 0 for a | |
| + * timeline drm_syncobj is invalid as it turns a drm_syncobj into a | |
| + * binary one. | |
| + */ | |
| + __u64 value; | |
| +}; | |
| + | |
| struct drm_i915_gem_pin { | |
| /** Handle of the buffer to be pinned. */ | |
| __u32 handle; | |
| @@ -3808,7 +3843,8 @@ struct drm_i915_gem_create_ext_vm_private { | |
| * -ENOSPC will be returned if the VA range specified can't be reserved. | |
| * | |
| * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently | |
| - * are not ordered. | |
| + * are not ordered. Furthermore, parts of the VM_BIND operation can be done | |
| + * asynchronously, if valid @fence is specified. | |
| */ | |
| struct drm_i915_gem_vm_bind { | |
| /** @vm_id: VM (address space) id to bind */ | |
| @@ -3826,15 +3862,29 @@ struct drm_i915_gem_vm_bind { | |
| /** @length: Length of mapping to bind */ | |
| __u64 length; | |
| - /** @flags: Currently reserved, MBZ. */ | |
| + /** | |
| + * @flags: Currently reserved, MBZ. | |
| + * | |
| + * Note that @fence carries its own flags. | |
| + */ | |
| __u64 flags; | |
| #define __I915_GEM_VM_BIND_UNKNOWN_FLAGS (~0ull) | |
| /** @rsvd: Reserved, MBZ */ | |
| __u64 rsvd[2]; | |
| - /** @rsvd2: Reserved for timeline fence */ | |
| - __u64 rsvd2[2]; | |
| + /** | |
| + * @fence: Timeline fence for bind completion signaling. | |
| + * | |
| + * Timeline fence is of format struct drm_i915_gem_timeline_fence. | |
| + * | |
| + * It is an out fence, hence using I915_TIMELINE_FENCE_WAIT flag | |
| + * is invalid, and an error will be returned. | |
| + * | |
| + * If I915_TIMELINE_FENCE_SIGNAL flag is not set, then out fence | |
| + * is not requested and binding is completed synchronously. | |
| + */ | |
| + struct drm_i915_gem_timeline_fence fence; | |
| /** | |
| * @extensions: Zero-terminated chain of extensions. | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 11/23] drm/i915/vm_bind: Abstract out common execbuf | |
| functions | |
| Date: Tue, 17 Jan 2023 23:15:57 -0800 | |
| Message-Id: <20230118071609.17572-12-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| The new execbuf3 ioctl path and the legacy execbuf ioctl | |
| paths have many common functionalities. | |
| Abstract out the common execbuf functionalities into a | |
| separate file where possible, thus allowing code sharing. | |
| v2: Use drm_dbg instead of DRM_DEBUG | |
| Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| drivers/gpu/drm/i915/Makefile | 1 + | |
| .../drm/i915/gem/i915_gem_execbuffer_common.c | 671 ++++++++++++++++++ | |
| .../drm/i915/gem/i915_gem_execbuffer_common.h | 76 ++ | |
| 3 files changed, 748 insertions(+) | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h | |
| diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile | |
| index fc3ed0aea034..68b209a859f1 100644 | |
| --- a/drivers/gpu/drm/i915/Makefile | |
| +++ b/drivers/gpu/drm/i915/Makefile | |
| @@ -154,6 +154,7 @@ gem-y += \ | |
| gem/i915_gem_create.o \ | |
| gem/i915_gem_dmabuf.o \ | |
| gem/i915_gem_domain.o \ | |
| + gem/i915_gem_execbuffer_common.o \ | |
| gem/i915_gem_execbuffer.o \ | |
| gem/i915_gem_internal.o \ | |
| gem/i915_gem_object.o \ | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c | |
| new file mode 100644 | |
| index 000000000000..fb1364f08a61 | |
| --- /dev/null | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c | |
| @@ -0,0 +1,671 @@ | |
| +// SPDX-License-Identifier: MIT | |
| +/* | |
| + * Copyright © 2022 Intel Corporation | |
| + */ | |
| + | |
| +#include <linux/dma-fence-array.h> | |
| + | |
| +#include <drm/drm_syncobj.h> | |
| + | |
| +#include "gt/intel_context.h" | |
| +#include "gt/intel_gt.h" | |
| +#include "gt/intel_gt_pm.h" | |
| +#include "gt/intel_ring.h" | |
| + | |
| +#include "i915_drv.h" | |
| +#include "i915_gem_execbuffer_common.h" | |
| + | |
| +#define __EXEC_COMMON_FENCE_WAIT BIT(0) | |
| +#define __EXEC_COMMON_FENCE_SIGNAL BIT(1) | |
| + | |
| +static struct i915_request *eb_throttle(struct intel_context *ce) | |
| +{ | |
| + struct intel_ring *ring = ce->ring; | |
| + struct intel_timeline *tl = ce->timeline; | |
| + struct i915_request *rq; | |
| + | |
| + /* | |
| + * Completely unscientific finger-in-the-air estimates for suitable | |
| + * maximum user request size (to avoid blocking) and then backoff. | |
| + */ | |
| + if (intel_ring_update_space(ring) >= PAGE_SIZE) | |
| + return NULL; | |
| + | |
| + /* | |
| + * Find a request that after waiting upon, there will be at least half | |
| + * the ring available. The hysteresis allows us to compete for the | |
| + * shared ring and should mean that we sleep less often prior to | |
| + * claiming our resources, but not so long that the ring completely | |
| + * drains before we can submit our next request. | |
| + */ | |
| + list_for_each_entry(rq, &tl->requests, link) { | |
| + if (rq->ring != ring) | |
| + continue; | |
| + | |
| + if (__intel_ring_space(rq->postfix, | |
| + ring->emit, ring->size) > ring->size / 2) | |
| + break; | |
| + } | |
| + if (&rq->link == &tl->requests) | |
| + return NULL; /* weird, we will check again later for real */ | |
| + | |
| + return i915_request_get(rq); | |
| +} | |
| + | |
| +static int eb_pin_timeline(struct intel_context *ce, bool throttle, | |
| + bool nonblock) | |
| +{ | |
| + struct intel_timeline *tl; | |
| + struct i915_request *rq = NULL; | |
| + | |
| + /* | |
| + * Take a local wakeref for preparing to dispatch the execbuf as | |
| + * we expect to access the hardware fairly frequently in the | |
| + * process, and require the engine to be kept awake between accesses. | |
| + * Upon dispatch, we acquire another prolonged wakeref that we hold | |
| + * until the timeline is idle, which in turn releases the wakeref | |
| + * taken on the engine, and the parent device. | |
| + */ | |
| + tl = intel_context_timeline_lock(ce); | |
| + if (IS_ERR(tl)) | |
| + return PTR_ERR(tl); | |
| + | |
| + intel_context_enter(ce); | |
| + if (throttle) | |
| + rq = eb_throttle(ce); | |
| + intel_context_timeline_unlock(tl); | |
| + | |
| + if (rq) { | |
| + long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT; | |
| + | |
| + if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, | |
| + timeout) < 0) { | |
| + i915_request_put(rq); | |
| + | |
| + /* | |
| + * Error path, cannot use intel_context_timeline_lock as | |
| + * that is user interruptable and this clean up step | |
| + * must be done. | |
| + */ | |
| + mutex_lock(&ce->timeline->mutex); | |
| + intel_context_exit(ce); | |
| + mutex_unlock(&ce->timeline->mutex); | |
| + | |
| + if (nonblock) | |
| + return -EWOULDBLOCK; | |
| + else | |
| + return -EINTR; | |
| + } | |
| + i915_request_put(rq); | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_pin_engine() - Pin the engine | |
| + * @ce: the context | |
| + * @ww: optional locking context or NULL | |
| + * @throttle: throttle to ensure enough ring space | |
| + * @nonblock: do not block during throttle | |
| + * | |
| + * Pin the @ce timeline. If @throttle is set, enable throttling to ensure | |
| + * enough ring space is available either by waiting for requests to complete | |
| + * (if @nonblock is not set) or by returning error -EWOULDBLOCK (if @nonblock | |
| + * is set). | |
| + * | |
| + * Returns 0 upon success, -ve error code upon error. | |
| + */ | |
| +int i915_eb_pin_engine(struct intel_context *ce, struct i915_gem_ww_ctx *ww, | |
| + bool throttle, bool nonblock) | |
| +{ | |
| + struct intel_context *child; | |
| + int err; | |
| + int i = 0, j = 0; | |
| + | |
| + if (unlikely(intel_context_is_banned(ce))) | |
| + return -EIO; | |
| + | |
| + /* | |
| + * Pinning the contexts may generate requests in order to acquire | |
| + * GGTT space, so do this first before we reserve a seqno for | |
| + * ourselves. | |
| + */ | |
| + err = intel_context_pin_ww(ce, ww); | |
| + if (err) | |
| + return err; | |
| + | |
| + for_each_child(ce, child) { | |
| + err = intel_context_pin_ww(child, ww); | |
| + GEM_BUG_ON(err); /* perma-pinned should incr a counter */ | |
| + } | |
| + | |
| + for_each_child(ce, child) { | |
| + err = eb_pin_timeline(child, throttle, nonblock); | |
| + if (err) | |
| + goto unwind; | |
| + ++i; | |
| + } | |
| + err = eb_pin_timeline(ce, throttle, nonblock); | |
| + if (err) | |
| + goto unwind; | |
| + | |
| + return 0; | |
| + | |
| +unwind: | |
| + for_each_child(ce, child) { | |
| + if (j++ < i) { | |
| + mutex_lock(&child->timeline->mutex); | |
| + intel_context_exit(child); | |
| + mutex_unlock(&child->timeline->mutex); | |
| + } | |
| + } | |
| + for_each_child(ce, child) | |
| + intel_context_unpin(child); | |
| + intel_context_unpin(ce); | |
| + return err; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_unpin_engine() - Unpin the engine | |
| + * @ce: the context | |
| + * | |
| + * Unpin the @ce timeline. | |
| + */ | |
| +void i915_eb_unpin_engine(struct intel_context *ce) | |
| +{ | |
| + struct intel_context *child; | |
| + | |
| + for_each_child(ce, child) { | |
| + mutex_lock(&child->timeline->mutex); | |
| + intel_context_exit(child); | |
| + mutex_unlock(&child->timeline->mutex); | |
| + | |
| + intel_context_unpin(child); | |
| + } | |
| + | |
| + mutex_lock(&ce->timeline->mutex); | |
| + intel_context_exit(ce); | |
| + mutex_unlock(&ce->timeline->mutex); | |
| + | |
| + intel_context_unpin(ce); | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_find_context() - Find the context | |
| + * @context: the context | |
| + * @context_number: required context index | |
| + * | |
| + * Returns the @context_number'th child of specified @context, | |
| + * or NULL if the child context is not found. | |
| + * If @context_number is 0, return the specified @context. | |
| + */ | |
| +struct intel_context * | |
| +i915_eb_find_context(struct intel_context *context, unsigned int context_number) | |
| +{ | |
| + struct intel_context *child; | |
| + | |
| + if (likely(context_number == 0)) | |
| + return context; | |
| + | |
| + for_each_child(context, child) | |
| + if (!--context_number) | |
| + return child; | |
| + | |
| + GEM_BUG_ON("Context not found"); | |
| + | |
| + return NULL; | |
| +} | |
| + | |
| +static void __free_fence_array(struct eb_fence *fences, u64 n) | |
| +{ | |
| + while (n--) { | |
| + drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2)); | |
| + dma_fence_put(fences[n].dma_fence); | |
| + dma_fence_chain_free(fences[n].chain_fence); | |
| + } | |
| + kvfree(fences); | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_put_fence_array() - Free Execbuffer fence array | |
| + * @fences: Pointer to array of Execbuffer fences (See struct eb_fences) | |
| + * @num_fences: Number of fences in @fences array | |
| + * | |
| + * Free the Execbuffer fences in @fences array. | |
| + */ | |
| +void i915_eb_put_fence_array(struct eb_fence *fences, u64 num_fences) | |
| +{ | |
| + if (fences) | |
| + __free_fence_array(fences, num_fences); | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_add_timeline_fence() - Add a fence to the specified Execbuffer fence | |
| + * array. | |
| + * @i915: i915 private | |
| + * @file: drm file pointer | |
| + * @handle: drm_syncobj handle | |
| + * @point: point in the timeline | |
| + * @f: Execbuffer fence | |
| + * @wait: wait for the specified fence | |
| + * @signal: signal the specified fence | |
| + * | |
| + * Add the fence specified by drm_syncobj @handle at specified @point in the | |
| + * timeline to the Execbuffer fence array @f. If @wait is specified, it is an | |
| + * input fence and if @signal is specified it is an output fence. | |
| + * | |
| + * Returns 0 if the timeline fence to be added is already signaled (@f is not | |
| + * updated). Returns 1 upon successfully adding the timeline fence (@f is | |
| + * updated) and -ve error code upon failure. | |
| + */ | |
| +int i915_eb_add_timeline_fence(struct drm_i915_private *i915, | |
| + struct drm_file *file, u32 handle, u64 point, | |
| + struct eb_fence *f, bool wait, bool signal) | |
| +{ | |
| + struct drm_syncobj *syncobj; | |
| + struct dma_fence *fence = NULL; | |
| + u32 flags = 0; | |
| + int err = 0; | |
| + | |
| + syncobj = drm_syncobj_find(file, handle); | |
| + if (!syncobj) { | |
| + drm_dbg(&i915->drm, "Invalid syncobj handle provided\n"); | |
| + return -ENOENT; | |
| + } | |
| + | |
| + fence = drm_syncobj_fence_get(syncobj); | |
| + | |
| + if (!fence && wait && !signal) { | |
| + drm_dbg(&i915->drm, "Syncobj handle has no fence\n"); | |
| + drm_syncobj_put(syncobj); | |
| + return -EINVAL; | |
| + } | |
| + | |
| + if (fence) | |
| + err = dma_fence_chain_find_seqno(&fence, point); | |
| + | |
| + if (err && !signal) { | |
| + drm_dbg(&i915->drm, | |
| + "Syncobj handle missing requested point %llu\n", point); | |
| + dma_fence_put(fence); | |
| + drm_syncobj_put(syncobj); | |
| + return err; | |
| + } | |
| + | |
| + /* | |
| + * A point might have been signaled already and | |
| + * garbage collected from the timeline. In this case | |
| + * just ignore the point and carry on. | |
| + */ | |
| + if (!fence && !signal) { | |
| + drm_syncobj_put(syncobj); | |
| + return 0; | |
| + } | |
| + | |
| + /* | |
| + * For timeline syncobjs we need to preallocate chains for | |
| + * later signaling. | |
| + */ | |
| + if (point != 0 && signal) { | |
| + /* | |
| + * Waiting and signaling the same point (when point != | |
| + * 0) would break the timeline. | |
| + */ | |
| + if (wait) { | |
| + drm_dbg(&i915->drm, | |
| + "Trying to wait & signal the same timeline point.\n"); | |
| + dma_fence_put(fence); | |
| + drm_syncobj_put(syncobj); | |
| + return -EINVAL; | |
| + } | |
| + | |
| + f->chain_fence = dma_fence_chain_alloc(); | |
| + if (!f->chain_fence) { | |
| + drm_syncobj_put(syncobj); | |
| + dma_fence_put(fence); | |
| + return -ENOMEM; | |
| + } | |
| + } else { | |
| + f->chain_fence = NULL; | |
| + } | |
| + | |
| + flags |= wait ? __EXEC_COMMON_FENCE_WAIT : 0; | |
| + flags |= signal ? __EXEC_COMMON_FENCE_SIGNAL : 0; | |
| + | |
| + f->syncobj = ptr_pack_bits(syncobj, flags, 2); | |
| + f->dma_fence = fence; | |
| + f->value = point; | |
| + return 1; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_await_fence_array() - Setup a request to asynchronously | |
| + * wait for fences in the specified Execbuffer fence array. | |
| + * @fences: pointer to Execbuffer fence array | |
| + * @num_fences: number of fences in @fences array | |
| + * @rq: the i915_request that should wait for fences in @fences array | |
| + * | |
| + * Setup the request @rq to asynchronously wait for fences specified in | |
| + * @fences array to signal before starting execution. | |
| + * | |
| + * Returns 0 upon success, -ve error upon failure. | |
| + */ | |
| +int i915_eb_await_fence_array(struct eb_fence *fences, u64 num_fences, | |
| + struct i915_request *rq) | |
| +{ | |
| + unsigned int n; | |
| + | |
| + for (n = 0; n < num_fences; n++) { | |
| + int err; | |
| + | |
| + if (!fences[n].dma_fence) | |
| + continue; | |
| + | |
| + err = i915_request_await_dma_fence(rq, fences[n].dma_fence); | |
| + if (err < 0) | |
| + return err; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_signal_fence_array() - Attach a dma-fence to all out fences of | |
| + * Execbuffer fence array. | |
| + * @fences: pointer to Execbuffer fence array | |
| + * @num_fences: number of fences in @fences array | |
| + * @fence: the dma-fence to attach to all out fences in @fences array | |
| + * | |
| + * Attach the specified @fence to all out fences of Execbuffer fence array | |
| + * @fences, at the specified timeline point. Thus, the out fences gets | |
| + * signaled when the specified @fence gets signaled. | |
| + */ | |
| +void i915_eb_signal_fence_array(struct eb_fence *fences, u64 num_fences, | |
| + struct dma_fence * const fence) | |
| +{ | |
| + unsigned int n; | |
| + | |
| + for (n = 0; n < num_fences; n++) { | |
| + struct drm_syncobj *syncobj; | |
| + unsigned int flags; | |
| + | |
| + syncobj = ptr_unpack_bits(fences[n].syncobj, &flags, 2); | |
| + if (!(flags & __EXEC_COMMON_FENCE_SIGNAL)) | |
| + continue; | |
| + | |
| + if (fences[n].chain_fence) { | |
| + drm_syncobj_add_point(syncobj, | |
| + fences[n].chain_fence, | |
| + fence, | |
| + fences[n].value); | |
| + /* | |
| + * The chain's ownership is transferred to the | |
| + * timeline. | |
| + */ | |
| + fences[n].chain_fence = NULL; | |
| + } else { | |
| + drm_syncobj_replace_fence(syncobj, fence); | |
| + } | |
| + } | |
| +} | |
| + | |
| +/* | |
| + * Using two helper loops for the order of which requests / batches are created | |
| + * and added the to backend. Requests are created in order from the parent to | |
| + * the last child. Requests are added in the reverse order, from the last child | |
| + * to parent. This is done for locking reasons as the timeline lock is acquired | |
| + * during request creation and released when the request is added to the | |
| + * backend. To make lockdep happy (see intel_context_timeline_lock) this must be | |
| + * the ordering. | |
| + */ | |
| +#define for_each_batch_create_order(_num_batches) \ | |
| + for (unsigned int i = 0; i < (_num_batches); ++i) | |
| +#define for_each_batch_add_order(_num_batches) \ | |
| + for (int i = (_num_batches) - 1; i >= 0; --i) | |
| + | |
| +static void retire_requests(struct intel_timeline *tl, struct i915_request *end) | |
| +{ | |
| + struct i915_request *rq, *rn; | |
| + | |
| + list_for_each_entry_safe(rq, rn, &tl->requests, link) | |
| + if (rq == end || !i915_request_retire(rq)) | |
| + break; | |
| +} | |
| + | |
| +static int eb_request_add(struct intel_context *context, | |
| + struct i915_request *rq, | |
| + struct i915_sched_attr sched, | |
| + int err, bool last_parallel) | |
| +{ | |
| + struct intel_timeline * const tl = i915_request_timeline(rq); | |
| + struct i915_sched_attr attr = {}; | |
| + struct i915_request *prev; | |
| + | |
| + lockdep_assert_held(&tl->mutex); | |
| + lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
| + | |
| + trace_i915_request_add(rq); | |
| + | |
| + prev = __i915_request_commit(rq); | |
| + | |
| + /* Check that the context wasn't destroyed before submission */ | |
| + if (likely(!intel_context_is_closed(context))) { | |
| + attr = sched; | |
| + } else { | |
| + /* Serialise with context_close via the add_to_timeline */ | |
| + i915_request_set_error_once(rq, -ENOENT); | |
| + __i915_request_skip(rq); | |
| + err = -ENOENT; /* override any transient errors */ | |
| + } | |
| + | |
| + if (intel_context_is_parallel(context)) { | |
| + if (err) { | |
| + __i915_request_skip(rq); | |
| + set_bit(I915_FENCE_FLAG_SKIP_PARALLEL, | |
| + &rq->fence.flags); | |
| + } | |
| + if (last_parallel) | |
| + set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL, | |
| + &rq->fence.flags); | |
| + } | |
| + | |
| + __i915_request_queue(rq, &attr); | |
| + | |
| + /* Try to clean up the client's timeline after submitting the request */ | |
| + if (prev) | |
| + retire_requests(tl, prev); | |
| + | |
| + mutex_unlock(&tl->mutex); | |
| + | |
| + return err; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_requests_add() - Handle request queuing | |
| + * @requests: pointer to an array of request pointers | |
| + * @num_requests: size of @requests array | |
| + * @context: the context | |
| + * @sched: schedule attribute | |
| + * @err: error path if true | |
| + * | |
| + * Add requests to timeline queue. | |
| + * | |
| + * Return 0 upon success, error code upon failure. | |
| + */ | |
| +int i915_eb_requests_add(struct i915_request **requests, | |
| + unsigned int num_requests, | |
| + struct intel_context *context, | |
| + struct i915_sched_attr sched, | |
| + int err) | |
| +{ | |
| + /* | |
| + * We iterate in reverse order of creation to release timeline mutexes | |
| + * in same order. | |
| + */ | |
| + for_each_batch_add_order(num_requests) { | |
| + struct i915_request *rq = requests[i]; | |
| + | |
| + if (!rq) | |
| + continue; | |
| + | |
| + err |= eb_request_add(context, rq, sched, err, i == 0); | |
| + } | |
| + | |
| + return err; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_requests_get() - Get reference of requests | |
| + * @requests: pointer to an array of request pointers | |
| + * @num_requests: size of @requests array | |
| + * | |
| + * Get reference for each requests in @requests array. | |
| + */ | |
| +void i915_eb_requests_get(struct i915_request **requests, | |
| + unsigned int num_requests) | |
| +{ | |
| + for_each_batch_create_order(num_requests) { | |
| + if (!requests[i]) | |
| + break; | |
| + | |
| + i915_request_get(requests[i]); | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_requests_put() - Release reference of requests | |
| + * @requests: pointer to an array of request pointers | |
| + * @num_requests: size of @requests array | |
| + * | |
| + * Release reference for each requests in @requests array. | |
| + */ | |
| +void i915_eb_requests_put(struct i915_request **requests, | |
| + unsigned int num_requests) | |
| +{ | |
| + for_each_batch_create_order(num_requests) { | |
| + if (!requests[i]) | |
| + break; | |
| + | |
| + i915_request_put(requests[i]); | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_composite_fence_create() - Create a composite fence for an array of | |
| + * requests on a specified context. | |
| + * @requests: pointer to an array of request pointers | |
| + * @num_requests: size of @requests array | |
| + * @context: the context | |
| + * | |
| + * Create and return the base class of a dma_fence_array with fences of all | |
| + * requests in @requests array with fence context specified by @context. | |
| + * | |
| + * Returns fence array base upon success, an error pointer upon failure. | |
| + */ | |
| +struct dma_fence *i915_eb_composite_fence_create(struct i915_request **requests, | |
| + unsigned int num_requests, | |
| + struct intel_context *context) | |
| +{ | |
| + struct dma_fence_array *fence_array; | |
| + struct dma_fence **fences; | |
| + | |
| + GEM_BUG_ON(!intel_context_is_parent(context)); | |
| + | |
| + fences = kmalloc_array(num_requests, sizeof(*fences), GFP_KERNEL); | |
| + if (!fences) | |
| + return ERR_PTR(-ENOMEM); | |
| + | |
| + for_each_batch_create_order(num_requests) { | |
| + fences[i] = &requests[i]->fence; | |
| + __set_bit(I915_FENCE_FLAG_COMPOSITE, | |
| + &requests[i]->fence.flags); | |
| + } | |
| + | |
| + fence_array = dma_fence_array_create(num_requests, | |
| + fences, | |
| + context->parallel.fence_context, | |
| + context->parallel.seqno++, | |
| + false); | |
| + if (!fence_array) { | |
| + kfree(fences); | |
| + return ERR_PTR(-ENOMEM); | |
| + } | |
| + | |
| + /* Move ownership to the dma_fence_array created above */ | |
| + for_each_batch_create_order(num_requests) | |
| + dma_fence_get(fences[i]); | |
| + | |
| + return &fence_array->base; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_select_engine() - Get engine references | |
| + * @ce: the context | |
| + * | |
| + * Get reference of context @ce and children, reference of associated VM | |
| + * and wakeref of associated tile. Also allocate @ce resources. | |
| + * | |
| + * Returns 0 upon success, -ve error upon failure. | |
| + * Returns -EIO if the associated tile is wedged. | |
| + */ | |
| +int i915_eb_select_engine(struct intel_context *ce) | |
| +{ | |
| + struct intel_context *child; | |
| + int err; | |
| + | |
| + for_each_child(ce, child) | |
| + intel_context_get(child); | |
| + intel_gt_pm_get(ce->engine->gt); | |
| + | |
| + if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { | |
| + err = intel_context_alloc_state(ce); | |
| + if (err) | |
| + goto err; | |
| + } | |
| + for_each_child(ce, child) { | |
| + if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) { | |
| + err = intel_context_alloc_state(child); | |
| + if (err) | |
| + goto err; | |
| + } | |
| + } | |
| + | |
| + /* | |
| + * ABI: Before userspace accesses the GPU (e.g. execbuffer), report | |
| + * EIO if the GPU is already wedged. | |
| + */ | |
| + err = intel_gt_terminally_wedged(ce->engine->gt); | |
| + if (err) | |
| + goto err; | |
| + | |
| + if (!i915_vm_tryget(ce->vm)) { | |
| + err = -ENOENT; | |
| + goto err; | |
| + } | |
| + | |
| + return 0; | |
| +err: | |
| + intel_gt_pm_put(ce->engine->gt); | |
| + for_each_child(ce, child) | |
| + intel_context_put(child); | |
| + return err; | |
| +} | |
| + | |
| +/** | |
| + * i915_eb_put_engine() - Release engine references | |
| + * @ce: the context | |
| + * | |
| + * Release reference of context @ce and children, reference of associated VM | |
| + * and wakeref of associated tile. | |
| + */ | |
| +void i915_eb_put_engine(struct intel_context *ce) | |
| +{ | |
| + struct intel_context *child; | |
| + | |
| + i915_vm_put(ce->vm); | |
| + intel_gt_pm_put(ce->engine->gt); | |
| + for_each_child(ce, child) | |
| + intel_context_put(child); | |
| + intel_context_put(ce); | |
| +} | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h | |
| new file mode 100644 | |
| index 000000000000..de2432def07d | |
| --- /dev/null | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h | |
| @@ -0,0 +1,76 @@ | |
| +/* SPDX-License-Identifier: MIT */ | |
| +/* | |
| + * Copyright © 2022 Intel Corporation | |
| + */ | |
| + | |
| +#ifndef __I915_GEM_EXECBUFFER_COMMON_H | |
| +#define __I915_GEM_EXECBUFFER_COMMON_H | |
| + | |
| +#include <linux/types.h> | |
| + | |
| +struct dma_fence; | |
| +struct dma_fence_chain; | |
| +struct drm_file; | |
| +struct drm_syncobj; | |
| + | |
| +struct drm_i915_private; | |
| +struct intel_context; | |
| +struct intel_gt; | |
| +struct i915_gem_ww_ctx; | |
| +struct i915_request; | |
| +struct i915_sched_attr; | |
| + | |
| +/** | |
| + * struct eb_fence - Execbuffer fence | |
| + * | |
| + * Data structure for execbuffer timeline fence handling. | |
| + */ | |
| +struct eb_fence { | |
| + /** @syncobj: Pointer to user specified syncobj */ | |
| + struct drm_syncobj *syncobj; | |
| + | |
| + /** @dma_fence: Fence associated with @syncobj */ | |
| + struct dma_fence *dma_fence; | |
| + | |
| + /** @value: User specified point in the timeline */ | |
| + u64 value; | |
| + | |
| + /** @chain_fence: Fence chain to add the timeline point */ | |
| + struct dma_fence_chain *chain_fence; | |
| +}; | |
| + | |
| +int i915_eb_pin_engine(struct intel_context *ce, struct i915_gem_ww_ctx *ww, | |
| + bool throttle, bool nonblock); | |
| +void i915_eb_unpin_engine(struct intel_context *ce); | |
| +int i915_eb_select_engine(struct intel_context *ce); | |
| +void i915_eb_put_engine(struct intel_context *ce); | |
| + | |
| +struct intel_context * | |
| +i915_eb_find_context(struct intel_context *context, | |
| + unsigned int context_number); | |
| + | |
| +int i915_eb_add_timeline_fence(struct drm_i915_private *i915, | |
| + struct drm_file *file, u32 handle, u64 point, | |
| + struct eb_fence *f, bool wait, bool signal); | |
| +void i915_eb_put_fence_array(struct eb_fence *fences, u64 num_fences); | |
| +int i915_eb_await_fence_array(struct eb_fence *fences, u64 num_fences, | |
| + struct i915_request *rq); | |
| +void i915_eb_signal_fence_array(struct eb_fence *fences, u64 num_fences, | |
| + struct dma_fence * const fence); | |
| + | |
| +int i915_eb_requests_add(struct i915_request **requests, | |
| + unsigned int num_requests, | |
| + struct intel_context *context, | |
| + struct i915_sched_attr sched, | |
| + int err); | |
| +void i915_eb_requests_get(struct i915_request **requests, | |
| + unsigned int num_requests); | |
| +void i915_eb_requests_put(struct i915_request **requests, | |
| + unsigned int num_requests); | |
| + | |
| +struct dma_fence * | |
| +i915_eb_composite_fence_create(struct i915_request **requests, | |
| + unsigned int num_requests, | |
| + struct intel_context *context); | |
| + | |
| +#endif /* __I915_GEM_EXECBUFFER_COMMON_H */ | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
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| by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:14 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 12/23] drm/i915/vm_bind: Use common execbuf functions in | |
| execbuf path | |
| Date: Tue, 17 Jan 2023 23:15:58 -0800 | |
| Message-Id: <20230118071609.17572-13-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Update the execbuf path to use common execbuf functions to | |
| reduce code duplication with the newer execbuf3 path. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 513 ++---------------- | |
| 1 file changed, 39 insertions(+), 474 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| index 6a7f0227f65f..8b49543f3265 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| @@ -28,6 +28,7 @@ | |
| #include "i915_file_private.h" | |
| #include "i915_gem_clflush.h" | |
| #include "i915_gem_context.h" | |
| +#include "i915_gem_execbuffer_common.h" | |
| #include "i915_gem_evict.h" | |
| #include "i915_gem_ioctls.h" | |
| #include "i915_reg.h" | |
| @@ -236,13 +237,6 @@ enum { | |
| * the batchbuffer in trusted mode, otherwise the ioctl is rejected. | |
| */ | |
| -struct eb_fence { | |
| - struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */ | |
| - struct dma_fence *dma_fence; | |
| - u64 value; | |
| - struct dma_fence_chain *chain_fence; | |
| -}; | |
| - | |
| struct i915_execbuffer { | |
| struct drm_i915_private *i915; /** i915 backpointer */ | |
| struct drm_file *file; /** per-file lookup tables and limits */ | |
| @@ -2484,164 +2478,29 @@ static const enum intel_engine_id user_ring_map[] = { | |
| [I915_EXEC_VEBOX] = VECS0 | |
| }; | |
| -static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce) | |
| -{ | |
| - struct intel_ring *ring = ce->ring; | |
| - struct intel_timeline *tl = ce->timeline; | |
| - struct i915_request *rq; | |
| - | |
| - /* | |
| - * Completely unscientific finger-in-the-air estimates for suitable | |
| - * maximum user request size (to avoid blocking) and then backoff. | |
| - */ | |
| - if (intel_ring_update_space(ring) >= PAGE_SIZE) | |
| - return NULL; | |
| - | |
| - /* | |
| - * Find a request that after waiting upon, there will be at least half | |
| - * the ring available. The hysteresis allows us to compete for the | |
| - * shared ring and should mean that we sleep less often prior to | |
| - * claiming our resources, but not so long that the ring completely | |
| - * drains before we can submit our next request. | |
| - */ | |
| - list_for_each_entry(rq, &tl->requests, link) { | |
| - if (rq->ring != ring) | |
| - continue; | |
| - | |
| - if (__intel_ring_space(rq->postfix, | |
| - ring->emit, ring->size) > ring->size / 2) | |
| - break; | |
| - } | |
| - if (&rq->link == &tl->requests) | |
| - return NULL; /* weird, we will check again later for real */ | |
| - | |
| - return i915_request_get(rq); | |
| -} | |
| - | |
| -static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce, | |
| - bool throttle) | |
| -{ | |
| - struct intel_timeline *tl; | |
| - struct i915_request *rq = NULL; | |
| - | |
| - /* | |
| - * Take a local wakeref for preparing to dispatch the execbuf as | |
| - * we expect to access the hardware fairly frequently in the | |
| - * process, and require the engine to be kept awake between accesses. | |
| - * Upon dispatch, we acquire another prolonged wakeref that we hold | |
| - * until the timeline is idle, which in turn releases the wakeref | |
| - * taken on the engine, and the parent device. | |
| - */ | |
| - tl = intel_context_timeline_lock(ce); | |
| - if (IS_ERR(tl)) | |
| - return PTR_ERR(tl); | |
| - | |
| - intel_context_enter(ce); | |
| - if (throttle) | |
| - rq = eb_throttle(eb, ce); | |
| - intel_context_timeline_unlock(tl); | |
| - | |
| - if (rq) { | |
| - bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; | |
| - long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT; | |
| - | |
| - if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, | |
| - timeout) < 0) { | |
| - i915_request_put(rq); | |
| - | |
| - /* | |
| - * Error path, cannot use intel_context_timeline_lock as | |
| - * that is user interruptable and this clean up step | |
| - * must be done. | |
| - */ | |
| - mutex_lock(&ce->timeline->mutex); | |
| - intel_context_exit(ce); | |
| - mutex_unlock(&ce->timeline->mutex); | |
| - | |
| - if (nonblock) | |
| - return -EWOULDBLOCK; | |
| - else | |
| - return -EINTR; | |
| - } | |
| - i915_request_put(rq); | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle) | |
| { | |
| - struct intel_context *ce = eb->context, *child; | |
| int err; | |
| - int i = 0, j = 0; | |
| GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED); | |
| - if (unlikely(intel_context_is_banned(ce))) | |
| - return -EIO; | |
| - | |
| - /* | |
| - * Pinning the contexts may generate requests in order to acquire | |
| - * GGTT space, so do this first before we reserve a seqno for | |
| - * ourselves. | |
| - */ | |
| - err = intel_context_pin_ww(ce, &eb->ww); | |
| + err = i915_eb_pin_engine(eb->context, &eb->ww, throttle, | |
| + eb->file->filp->f_flags & O_NONBLOCK); | |
| if (err) | |
| return err; | |
| - for_each_child(ce, child) { | |
| - err = intel_context_pin_ww(child, &eb->ww); | |
| - GEM_BUG_ON(err); /* perma-pinned should incr a counter */ | |
| - } | |
| - | |
| - for_each_child(ce, child) { | |
| - err = eb_pin_timeline(eb, child, throttle); | |
| - if (err) | |
| - goto unwind; | |
| - ++i; | |
| - } | |
| - err = eb_pin_timeline(eb, ce, throttle); | |
| - if (err) | |
| - goto unwind; | |
| eb->args->flags |= __EXEC_ENGINE_PINNED; | |
| return 0; | |
| - | |
| -unwind: | |
| - for_each_child(ce, child) { | |
| - if (j++ < i) { | |
| - mutex_lock(&child->timeline->mutex); | |
| - intel_context_exit(child); | |
| - mutex_unlock(&child->timeline->mutex); | |
| - } | |
| - } | |
| - for_each_child(ce, child) | |
| - intel_context_unpin(child); | |
| - intel_context_unpin(ce); | |
| - return err; | |
| } | |
| static void eb_unpin_engine(struct i915_execbuffer *eb) | |
| { | |
| - struct intel_context *ce = eb->context, *child; | |
| - | |
| if (!(eb->args->flags & __EXEC_ENGINE_PINNED)) | |
| return; | |
| eb->args->flags &= ~__EXEC_ENGINE_PINNED; | |
| - for_each_child(ce, child) { | |
| - mutex_lock(&child->timeline->mutex); | |
| - intel_context_exit(child); | |
| - mutex_unlock(&child->timeline->mutex); | |
| - | |
| - intel_context_unpin(child); | |
| - } | |
| - | |
| - mutex_lock(&ce->timeline->mutex); | |
| - intel_context_exit(ce); | |
| - mutex_unlock(&ce->timeline->mutex); | |
| - | |
| - intel_context_unpin(ce); | |
| + i915_eb_unpin_engine(eb->context); | |
| } | |
| static unsigned int | |
| @@ -2691,7 +2550,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb) | |
| static int | |
| eb_select_engine(struct i915_execbuffer *eb) | |
| { | |
| - struct intel_context *ce, *child; | |
| + struct intel_context *ce; | |
| unsigned int idx; | |
| int err; | |
| @@ -2716,36 +2575,10 @@ eb_select_engine(struct i915_execbuffer *eb) | |
| } | |
| eb->num_batches = ce->parallel.number_children + 1; | |
| - for_each_child(ce, child) | |
| - intel_context_get(child); | |
| - intel_gt_pm_get(ce->engine->gt); | |
| - | |
| - if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { | |
| - err = intel_context_alloc_state(ce); | |
| - if (err) | |
| - goto err; | |
| - } | |
| - for_each_child(ce, child) { | |
| - if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) { | |
| - err = intel_context_alloc_state(child); | |
| - if (err) | |
| - goto err; | |
| - } | |
| - } | |
| - | |
| - /* | |
| - * ABI: Before userspace accesses the GPU (e.g. execbuffer), report | |
| - * EIO if the GPU is already wedged. | |
| - */ | |
| - err = intel_gt_terminally_wedged(ce->engine->gt); | |
| + err = i915_eb_select_engine(ce); | |
| if (err) | |
| goto err; | |
| - if (!i915_vm_tryget(ce->vm)) { | |
| - err = -ENOENT; | |
| - goto err; | |
| - } | |
| - | |
| eb->context = ce; | |
| eb->gt = ce->engine->gt; | |
| @@ -2754,12 +2587,9 @@ eb_select_engine(struct i915_execbuffer *eb) | |
| * during ww handling. The pool is destroyed when last pm reference | |
| * is dropped, which breaks our -EDEADLK handling. | |
| */ | |
| - return err; | |
| + return 0; | |
| err: | |
| - intel_gt_pm_put(ce->engine->gt); | |
| - for_each_child(ce, child) | |
| - intel_context_put(child); | |
| intel_context_put(ce); | |
| return err; | |
| } | |
| @@ -2767,24 +2597,7 @@ eb_select_engine(struct i915_execbuffer *eb) | |
| static void | |
| eb_put_engine(struct i915_execbuffer *eb) | |
| { | |
| - struct intel_context *child; | |
| - | |
| - i915_vm_put(eb->context->vm); | |
| - intel_gt_pm_put(eb->gt); | |
| - for_each_child(eb->context, child) | |
| - intel_context_put(child); | |
| - intel_context_put(eb->context); | |
| -} | |
| - | |
| -static void | |
| -__free_fence_array(struct eb_fence *fences, unsigned int n) | |
| -{ | |
| - while (n--) { | |
| - drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2)); | |
| - dma_fence_put(fences[n].dma_fence); | |
| - dma_fence_chain_free(fences[n].chain_fence); | |
| - } | |
| - kvfree(fences); | |
| + i915_eb_put_engine(eb->context); | |
| } | |
| static int | |
| @@ -2795,7 +2608,6 @@ add_timeline_fence_array(struct i915_execbuffer *eb, | |
| u64 __user *user_values; | |
| struct eb_fence *f; | |
| u64 nfences; | |
| - int err = 0; | |
| nfences = timeline_fences->fence_count; | |
| if (!nfences) | |
| @@ -2830,9 +2642,9 @@ add_timeline_fence_array(struct i915_execbuffer *eb, | |
| while (nfences--) { | |
| struct drm_i915_gem_exec_fence user_fence; | |
| - struct drm_syncobj *syncobj; | |
| - struct dma_fence *fence = NULL; | |
| + bool wait, signal; | |
| u64 point; | |
| + int ret; | |
| if (__copy_from_user(&user_fence, | |
| user_fences++, | |
| @@ -2845,75 +2657,16 @@ add_timeline_fence_array(struct i915_execbuffer *eb, | |
| if (__get_user(point, user_values++)) | |
| return -EFAULT; | |
| - syncobj = drm_syncobj_find(eb->file, user_fence.handle); | |
| - if (!syncobj) { | |
| - drm_dbg(&eb->i915->drm, | |
| - "Invalid syncobj handle provided\n"); | |
| - return -ENOENT; | |
| - } | |
| - | |
| - fence = drm_syncobj_fence_get(syncobj); | |
| - | |
| - if (!fence && user_fence.flags && | |
| - !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { | |
| - drm_dbg(&eb->i915->drm, | |
| - "Syncobj handle has no fence\n"); | |
| - drm_syncobj_put(syncobj); | |
| - return -EINVAL; | |
| - } | |
| - | |
| - if (fence) | |
| - err = dma_fence_chain_find_seqno(&fence, point); | |
| - | |
| - if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { | |
| - drm_dbg(&eb->i915->drm, | |
| - "Syncobj handle missing requested point %llu\n", | |
| - point); | |
| - dma_fence_put(fence); | |
| - drm_syncobj_put(syncobj); | |
| - return err; | |
| - } | |
| - | |
| - /* | |
| - * A point might have been signaled already and | |
| - * garbage collected from the timeline. In this case | |
| - * just ignore the point and carry on. | |
| - */ | |
| - if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { | |
| - drm_syncobj_put(syncobj); | |
| + wait = user_fence.flags & I915_EXEC_FENCE_WAIT; | |
| + signal = user_fence.flags & I915_EXEC_FENCE_SIGNAL; | |
| + ret = i915_eb_add_timeline_fence(eb->i915, eb->file, | |
| + user_fence.handle, point, | |
| + f, wait, signal); | |
| + if (ret < 0) | |
| + return ret; | |
| + else if (!ret) | |
| continue; | |
| - } | |
| - | |
| - /* | |
| - * For timeline syncobjs we need to preallocate chains for | |
| - * later signaling. | |
| - */ | |
| - if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) { | |
| - /* | |
| - * Waiting and signaling the same point (when point != | |
| - * 0) would break the timeline. | |
| - */ | |
| - if (user_fence.flags & I915_EXEC_FENCE_WAIT) { | |
| - drm_dbg(&eb->i915->drm, | |
| - "Trying to wait & signal the same timeline point.\n"); | |
| - dma_fence_put(fence); | |
| - drm_syncobj_put(syncobj); | |
| - return -EINVAL; | |
| - } | |
| - | |
| - f->chain_fence = dma_fence_chain_alloc(); | |
| - if (!f->chain_fence) { | |
| - drm_syncobj_put(syncobj); | |
| - dma_fence_put(fence); | |
| - return -ENOMEM; | |
| - } | |
| - } else { | |
| - f->chain_fence = NULL; | |
| - } | |
| - f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2); | |
| - f->dma_fence = fence; | |
| - f->value = point; | |
| f++; | |
| eb->num_fences++; | |
| } | |
| @@ -2995,60 +2748,6 @@ static int add_fence_array(struct i915_execbuffer *eb) | |
| return 0; | |
| } | |
| -static void put_fence_array(struct eb_fence *fences, int num_fences) | |
| -{ | |
| - if (fences) | |
| - __free_fence_array(fences, num_fences); | |
| -} | |
| - | |
| -static int | |
| -await_fence_array(struct i915_execbuffer *eb, | |
| - struct i915_request *rq) | |
| -{ | |
| - unsigned int n; | |
| - int err; | |
| - | |
| - for (n = 0; n < eb->num_fences; n++) { | |
| - if (!eb->fences[n].dma_fence) | |
| - continue; | |
| - | |
| - err = i915_request_await_dma_fence(rq, eb->fences[n].dma_fence); | |
| - if (err < 0) | |
| - return err; | |
| - } | |
| - | |
| - return 0; | |
| -} | |
| - | |
| -static void signal_fence_array(const struct i915_execbuffer *eb, | |
| - struct dma_fence * const fence) | |
| -{ | |
| - unsigned int n; | |
| - | |
| - for (n = 0; n < eb->num_fences; n++) { | |
| - struct drm_syncobj *syncobj; | |
| - unsigned int flags; | |
| - | |
| - syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2); | |
| - if (!(flags & I915_EXEC_FENCE_SIGNAL)) | |
| - continue; | |
| - | |
| - if (eb->fences[n].chain_fence) { | |
| - drm_syncobj_add_point(syncobj, | |
| - eb->fences[n].chain_fence, | |
| - fence, | |
| - eb->fences[n].value); | |
| - /* | |
| - * The chain's ownership is transferred to the | |
| - * timeline. | |
| - */ | |
| - eb->fences[n].chain_fence = NULL; | |
| - } else { | |
| - drm_syncobj_replace_fence(syncobj, fence); | |
| - } | |
| - } | |
| -} | |
| - | |
| static int | |
| parse_timeline_fences(struct i915_user_extension __user *ext, void *data) | |
| { | |
| @@ -3061,80 +2760,6 @@ parse_timeline_fences(struct i915_user_extension __user *ext, void *data) | |
| return add_timeline_fence_array(eb, &timeline_fences); | |
| } | |
| -static void retire_requests(struct intel_timeline *tl, struct i915_request *end) | |
| -{ | |
| - struct i915_request *rq, *rn; | |
| - | |
| - list_for_each_entry_safe(rq, rn, &tl->requests, link) | |
| - if (rq == end || !i915_request_retire(rq)) | |
| - break; | |
| -} | |
| - | |
| -static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq, | |
| - int err, bool last_parallel) | |
| -{ | |
| - struct intel_timeline * const tl = i915_request_timeline(rq); | |
| - struct i915_sched_attr attr = {}; | |
| - struct i915_request *prev; | |
| - | |
| - lockdep_assert_held(&tl->mutex); | |
| - lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
| - | |
| - trace_i915_request_add(rq); | |
| - | |
| - prev = __i915_request_commit(rq); | |
| - | |
| - /* Check that the context wasn't destroyed before submission */ | |
| - if (likely(!intel_context_is_closed(eb->context))) { | |
| - attr = eb->gem_context->sched; | |
| - } else { | |
| - /* Serialise with context_close via the add_to_timeline */ | |
| - i915_request_set_error_once(rq, -ENOENT); | |
| - __i915_request_skip(rq); | |
| - err = -ENOENT; /* override any transient errors */ | |
| - } | |
| - | |
| - if (intel_context_is_parallel(eb->context)) { | |
| - if (err) { | |
| - __i915_request_skip(rq); | |
| - set_bit(I915_FENCE_FLAG_SKIP_PARALLEL, | |
| - &rq->fence.flags); | |
| - } | |
| - if (last_parallel) | |
| - set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL, | |
| - &rq->fence.flags); | |
| - } | |
| - | |
| - __i915_request_queue(rq, &attr); | |
| - | |
| - /* Try to clean up the client's timeline after submitting the request */ | |
| - if (prev) | |
| - retire_requests(tl, prev); | |
| - | |
| - mutex_unlock(&tl->mutex); | |
| - | |
| - return err; | |
| -} | |
| - | |
| -static int eb_requests_add(struct i915_execbuffer *eb, int err) | |
| -{ | |
| - int i; | |
| - | |
| - /* | |
| - * We iterate in reverse order of creation to release timeline mutexes in | |
| - * same order. | |
| - */ | |
| - for_each_batch_add_order(eb, i) { | |
| - struct i915_request *rq = eb->requests[i]; | |
| - | |
| - if (!rq) | |
| - continue; | |
| - err |= eb_request_add(eb, rq, err, i == 0); | |
| - } | |
| - | |
| - return err; | |
| -} | |
| - | |
| static const i915_user_extension_fn execbuf_extensions[] = { | |
| [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences, | |
| }; | |
| @@ -3161,73 +2786,26 @@ parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args, | |
| eb); | |
| } | |
| -static void eb_requests_get(struct i915_execbuffer *eb) | |
| -{ | |
| - unsigned int i; | |
| - | |
| - for_each_batch_create_order(eb, i) { | |
| - if (!eb->requests[i]) | |
| - break; | |
| - | |
| - i915_request_get(eb->requests[i]); | |
| - } | |
| -} | |
| - | |
| -static void eb_requests_put(struct i915_execbuffer *eb) | |
| -{ | |
| - unsigned int i; | |
| - | |
| - for_each_batch_create_order(eb, i) { | |
| - if (!eb->requests[i]) | |
| - break; | |
| - | |
| - i915_request_put(eb->requests[i]); | |
| - } | |
| -} | |
| - | |
| static struct sync_file * | |
| eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd) | |
| { | |
| struct sync_file *out_fence = NULL; | |
| - struct dma_fence_array *fence_array; | |
| - struct dma_fence **fences; | |
| - unsigned int i; | |
| - | |
| - GEM_BUG_ON(!intel_context_is_parent(eb->context)); | |
| + struct dma_fence *fence; | |
| - fences = kmalloc_array(eb->num_batches, sizeof(*fences), GFP_KERNEL); | |
| - if (!fences) | |
| - return ERR_PTR(-ENOMEM); | |
| - | |
| - for_each_batch_create_order(eb, i) { | |
| - fences[i] = &eb->requests[i]->fence; | |
| - __set_bit(I915_FENCE_FLAG_COMPOSITE, | |
| - &eb->requests[i]->fence.flags); | |
| - } | |
| - | |
| - fence_array = dma_fence_array_create(eb->num_batches, | |
| - fences, | |
| - eb->context->parallel.fence_context, | |
| - eb->context->parallel.seqno++, | |
| - false); | |
| - if (!fence_array) { | |
| - kfree(fences); | |
| - return ERR_PTR(-ENOMEM); | |
| - } | |
| - | |
| - /* Move ownership to the dma_fence_array created above */ | |
| - for_each_batch_create_order(eb, i) | |
| - dma_fence_get(fences[i]); | |
| + fence = i915_eb_composite_fence_create(eb->requests, eb->num_batches, | |
| + eb->context); | |
| + if (IS_ERR(fence)) | |
| + return ERR_CAST(fence); | |
| if (out_fence_fd != -1) { | |
| - out_fence = sync_file_create(&fence_array->base); | |
| + out_fence = sync_file_create(fence); | |
| /* sync_file now owns fence_arry, drop creation ref */ | |
| - dma_fence_put(&fence_array->base); | |
| + dma_fence_put(fence); | |
| if (!out_fence) | |
| return ERR_PTR(-ENOMEM); | |
| } | |
| - eb->composite_fence = &fence_array->base; | |
| + eb->composite_fence = fence; | |
| return out_fence; | |
| } | |
| @@ -3259,7 +2837,7 @@ eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq, | |
| } | |
| if (eb->fences) { | |
| - err = await_fence_array(eb, rq); | |
| + err = i915_eb_await_fence_array(eb->fences, eb->num_fences, rq); | |
| if (err) | |
| return ERR_PTR(err); | |
| } | |
| @@ -3277,23 +2855,6 @@ eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq, | |
| return out_fence; | |
| } | |
| -static struct intel_context * | |
| -eb_find_context(struct i915_execbuffer *eb, unsigned int context_number) | |
| -{ | |
| - struct intel_context *child; | |
| - | |
| - if (likely(context_number == 0)) | |
| - return eb->context; | |
| - | |
| - for_each_child(eb->context, child) | |
| - if (!--context_number) | |
| - return child; | |
| - | |
| - GEM_BUG_ON("Context not found"); | |
| - | |
| - return NULL; | |
| -} | |
| - | |
| static struct sync_file * | |
| eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence, | |
| int out_fence_fd) | |
| @@ -3303,7 +2864,9 @@ eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence, | |
| for_each_batch_create_order(eb, i) { | |
| /* Allocate a request for this batch buffer nice and early. */ | |
| - eb->requests[i] = i915_request_create(eb_find_context(eb, i)); | |
| + eb->requests[i] = | |
| + i915_request_create(i915_eb_find_context(eb->context, | |
| + i)); | |
| if (IS_ERR(eb->requests[i])) { | |
| out_fence = ERR_CAST(eb->requests[i]); | |
| eb->requests[i] = NULL; | |
| @@ -3483,13 +3046,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, | |
| err = eb_submit(&eb); | |
| err_request: | |
| - eb_requests_get(&eb); | |
| - err = eb_requests_add(&eb, err); | |
| + i915_eb_requests_get(eb.requests, eb.num_batches); | |
| + err = i915_eb_requests_add(eb.requests, eb.num_batches, eb.context, | |
| + eb.gem_context->sched, err); | |
| if (eb.fences) | |
| - signal_fence_array(&eb, eb.composite_fence ? | |
| - eb.composite_fence : | |
| - &eb.requests[0]->fence); | |
| + i915_eb_signal_fence_array(eb.fences, eb.num_fences, | |
| + eb.composite_fence ? | |
| + eb.composite_fence : | |
| + &eb.requests[0]->fence); | |
| if (unlikely(eb.gem_context->syncobj)) { | |
| drm_syncobj_replace_fence(eb.gem_context->syncobj, | |
| @@ -3512,7 +3077,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, | |
| if (!out_fence && eb.composite_fence) | |
| dma_fence_put(eb.composite_fence); | |
| - eb_requests_put(&eb); | |
| + i915_eb_requests_put(eb.requests, eb.num_batches); | |
| err_vma: | |
| eb_release_vmas(&eb, true); | |
| @@ -3533,7 +3098,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, | |
| err_in_fence: | |
| dma_fence_put(in_fence); | |
| err_ext: | |
| - put_fence_array(eb.fences, eb.num_fences); | |
| + i915_eb_put_fence_array(eb.fences, eb.num_fences); | |
| return err; | |
| } | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 13/23] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 | |
| ioctl | |
| Date: Tue, 17 Jan 2023 23:15:59 -0800 | |
| Message-Id: <20230118071609.17572-14-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only | |
| works in vm_bind mode. The vm_bind mode only works with | |
| this new execbuf3 ioctl. | |
| The new execbuf3 ioctl will not have any list of objects to validate | |
| bind as all required objects binding would have been requested by the | |
| userspace before submitting the execbuf3. | |
| Legacy features like relocations etc are not supported by execbuf3. | |
| v2: Add more input validity checks. | |
| v3: batch_address is a VA (not an array) if num_batches=1, | |
| minor cleanup | |
| v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode() | |
| v5: Remove unwanted krealloc() and address other review comments. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/Makefile | 1 + | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 579 ++++++++++++++++++ | |
| drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 2 + | |
| drivers/gpu/drm/i915/i915_driver.c | 1 + | |
| include/uapi/drm/i915_drm.h | 61 ++ | |
| 5 files changed, 644 insertions(+) | |
| create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile | |
| index 68b209a859f1..b2477e85570c 100644 | |
| --- a/drivers/gpu/drm/i915/Makefile | |
| +++ b/drivers/gpu/drm/i915/Makefile | |
| @@ -156,6 +156,7 @@ gem-y += \ | |
| gem/i915_gem_domain.o \ | |
| gem/i915_gem_execbuffer_common.o \ | |
| gem/i915_gem_execbuffer.o \ | |
| + gem/i915_gem_execbuffer3.o \ | |
| gem/i915_gem_internal.o \ | |
| gem/i915_gem_object.o \ | |
| gem/i915_gem_lmem.o \ | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| new file mode 100644 | |
| index 000000000000..49045858a3e9 | |
| --- /dev/null | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| @@ -0,0 +1,579 @@ | |
| +// SPDX-License-Identifier: MIT | |
| +/* | |
| + * Copyright © 2022 Intel Corporation | |
| + */ | |
| + | |
| +#include <linux/dma-resv.h> | |
| +#include <linux/uaccess.h> | |
| + | |
| +#include <drm/drm_syncobj.h> | |
| + | |
| +#include "gt/intel_context.h" | |
| +#include "gt/intel_gpu_commands.h" | |
| +#include "gt/intel_gt.h" | |
| + | |
| +#include "i915_drv.h" | |
| +#include "i915_gem_context.h" | |
| +#include "i915_gem_execbuffer_common.h" | |
| +#include "i915_gem_ioctls.h" | |
| +#include "i915_gem_vm_bind.h" | |
| +#include "i915_trace.h" | |
| + | |
| +#define __EXEC3_ENGINE_PINNED BIT_ULL(32) | |
| +#define __EXEC3_INTERNAL_FLAGS (~0ull << 32) | |
| + | |
| +/* Catch emission of unexpected errors for CI! */ | |
| +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) | |
| +#undef EINVAL | |
| +#define EINVAL ({ \ | |
| + DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \ | |
| + 22; \ | |
| +}) | |
| +#endif | |
| + | |
| +/** | |
| + * DOC: User command execution in vm_bind mode | |
| + * | |
| + * A VM in VM_BIND mode will not support older execbuf mode of binding. | |
| + * The execbuf ioctl handling in VM_BIND mode differs significantly from the | |
| + * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2). | |
| + * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See | |
| + * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any | |
| + * execlist. Hence, no support for implicit sync. | |
| + * | |
| + * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only | |
| + * works with execbuf3 ioctl for submission. | |
| + * | |
| + * The execbuf3 ioctl directly specifies the batch addresses instead of as | |
| + * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not | |
| + * support many of the older features like in/out/submit fences, fence array, | |
| + * default gem context etc. (See struct drm_i915_gem_execbuffer3). | |
| + * | |
| + * In VM_BIND mode, VA allocation is completely managed by the user instead of | |
| + * the i915 driver. Hence all VA assignment, eviction are not applicable in | |
| + * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not | |
| + * be using the i915_vma active reference tracking. It will instead check the | |
| + * dma-resv object's fence list for that. | |
| + * | |
| + * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions, | |
| + * vma lookup table, implicit sync, vma active reference tracking etc., are not | |
| + * applicable for execbuf3 ioctl. | |
| + */ | |
| + | |
| +/** | |
| + * struct i915_execbuffer - execbuf struct for execbuf3 | |
| + * @i915: reference to the i915 instance we run on | |
| + * @file: drm file reference | |
| + * @args: execbuf3 ioctl structure | |
| + * @gt: reference to the gt instance ioctl submitted for | |
| + * @context: logical state for the request | |
| + * @gem_context: callers context | |
| + * @requests: requests to be build | |
| + * @composite_fence: used for excl fence in dma_resv objects when > 1 BB submitted | |
| + * @ww: i915_gem_ww_ctx instance | |
| + * @num_batches: number of batches submitted | |
| + * @batch_addresses: addresses corresponds to the submitted batches | |
| + * @batches: references to the i915_vmas corresponding to the batches | |
| + * @fences: array of execbuf fences (See struct eb_fence) | |
| + * @num_fences: number of fences in @fences array | |
| + */ | |
| +struct i915_execbuffer { | |
| + struct drm_i915_private *i915; | |
| + struct drm_file *file; | |
| + struct drm_i915_gem_execbuffer3 *args; | |
| + | |
| + struct intel_gt *gt; | |
| + struct intel_context *context; | |
| + struct i915_gem_context *gem_context; | |
| + | |
| + struct i915_request *requests[MAX_ENGINE_INSTANCE + 1]; | |
| + struct dma_fence *composite_fence; | |
| + | |
| + struct i915_gem_ww_ctx ww; | |
| + | |
| + unsigned int num_batches; | |
| + u64 batch_addresses[MAX_ENGINE_INSTANCE + 1]; | |
| + struct i915_vma *batches[MAX_ENGINE_INSTANCE + 1]; | |
| + | |
| + struct eb_fence *fences; | |
| + u64 num_fences; | |
| +}; | |
| + | |
| +static void eb_unpin_engine(struct i915_execbuffer *eb); | |
| + | |
| +static int eb_select_context(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_gem_context *ctx; | |
| + | |
| + ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->ctx_id); | |
| + if (IS_ERR(ctx)) | |
| + return PTR_ERR(ctx); | |
| + | |
| + if (!i915_gem_vm_is_vm_bind_mode(ctx->vm)) { | |
| + i915_gem_context_put(ctx); | |
| + return -EOPNOTSUPP; | |
| + } | |
| + | |
| + eb->gem_context = ctx; | |
| + return 0; | |
| +} | |
| + | |
| +static struct i915_vma * | |
| +eb_find_vma(struct i915_address_space *vm, u64 addr) | |
| +{ | |
| + u64 va; | |
| + | |
| + lockdep_assert_held(&vm->vm_bind_lock); | |
| + | |
| + va = gen8_noncanonical_addr(addr & PIN_OFFSET_MASK); | |
| + return i915_gem_vm_bind_lookup_vma(vm, va); | |
| +} | |
| + | |
| +static int eb_lookup_vma_all(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_vma *vma; | |
| + unsigned int i; | |
| + | |
| + for (i = 0; i < eb->num_batches; i++) { | |
| + vma = eb_find_vma(eb->context->vm, eb->batch_addresses[i]); | |
| + if (!vma) | |
| + return -EINVAL; | |
| + | |
| + eb->batches[i] = vma; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static void eb_release_vma_all(struct i915_execbuffer *eb) | |
| +{ | |
| + eb_unpin_engine(eb); | |
| +} | |
| + | |
| +/* | |
| + * Using two helper loops for the order of which requests / batches are created | |
| + * and added the to backend. Requests are created in order from the parent to | |
| + * the last child. Requests are added in the reverse order, from the last child | |
| + * to parent. This is done for locking reasons as the timeline lock is acquired | |
| + * during request creation and released when the request is added to the | |
| + * backend. To make lockdep happy (see intel_context_timeline_lock) this must be | |
| + * the ordering. | |
| + */ | |
| +#define for_each_batch_create_order(_eb) \ | |
| + for (unsigned int i = 0; i < (_eb)->num_batches; ++i) | |
| + | |
| +static int eb_move_to_gpu(struct i915_execbuffer *eb) | |
| +{ | |
| + /* Unconditionally flush any chipset caches (for streaming writes). */ | |
| + intel_gt_chipset_flush(eb->gt); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int eb_request_submit(struct i915_execbuffer *eb, | |
| + struct i915_request *rq, | |
| + struct i915_vma *batch, | |
| + u64 batch_len) | |
| +{ | |
| + struct intel_engine_cs *engine = rq->context->engine; | |
| + int err; | |
| + | |
| + if (intel_context_nopreempt(rq->context)) | |
| + __set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags); | |
| + | |
| + /* | |
| + * After we completed waiting for other engines (using HW semaphores) | |
| + * then we can signal that this request/batch is ready to run. This | |
| + * allows us to determine if the batch is still waiting on the GPU | |
| + * or actually running by checking the breadcrumb. | |
| + */ | |
| + if (engine->emit_init_breadcrumb) { | |
| + err = engine->emit_init_breadcrumb(rq); | |
| + if (err) | |
| + return err; | |
| + } | |
| + | |
| + return engine->emit_bb_start(rq, batch->node.start, batch_len, 0); | |
| +} | |
| + | |
| +static int eb_submit(struct i915_execbuffer *eb) | |
| +{ | |
| + int err; | |
| + | |
| + err = eb_move_to_gpu(eb); | |
| + | |
| + for_each_batch_create_order(eb) { | |
| + if (!eb->requests[i]) | |
| + break; | |
| + | |
| + trace_i915_request_queue(eb->requests[i], 0); | |
| + if (!err) | |
| + err = eb_request_submit(eb, eb->requests[i], | |
| + eb->batches[i], | |
| + eb->batches[i]->size); | |
| + } | |
| + | |
| + return err; | |
| +} | |
| + | |
| +static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle) | |
| +{ | |
| + int err; | |
| + | |
| + GEM_BUG_ON(eb->args->flags & __EXEC3_ENGINE_PINNED); | |
| + | |
| + err = i915_eb_pin_engine(eb->context, &eb->ww, throttle, | |
| + eb->file->filp->f_flags & O_NONBLOCK); | |
| + if (err) | |
| + return err; | |
| + | |
| + eb->args->flags |= __EXEC3_ENGINE_PINNED; | |
| + return 0; | |
| +} | |
| + | |
| +static void eb_unpin_engine(struct i915_execbuffer *eb) | |
| +{ | |
| + if (!(eb->args->flags & __EXEC3_ENGINE_PINNED)) | |
| + return; | |
| + | |
| + eb->args->flags &= ~__EXEC3_ENGINE_PINNED; | |
| + | |
| + i915_eb_unpin_engine(eb->context); | |
| +} | |
| + | |
| +static int eb_select_engine(struct i915_execbuffer *eb) | |
| +{ | |
| + struct intel_context *ce; | |
| + unsigned int idx; | |
| + int err; | |
| + | |
| + if (!i915_gem_context_user_engines(eb->gem_context)) | |
| + return -EINVAL; | |
| + | |
| + idx = eb->args->engine_idx; | |
| + ce = i915_gem_context_get_engine(eb->gem_context, idx); | |
| + if (IS_ERR(ce)) | |
| + return PTR_ERR(ce); | |
| + | |
| + eb->num_batches = ce->parallel.number_children + 1; | |
| + | |
| + err = i915_eb_select_engine(ce); | |
| + if (err) | |
| + goto err; | |
| + | |
| + eb->context = ce; | |
| + eb->gt = ce->engine->gt; | |
| + | |
| + /* | |
| + * Make sure engine pool stays alive even if we call intel_context_put | |
| + * during ww handling. The pool is destroyed when last pm reference | |
| + * is dropped, which breaks our -EDEADLK handling. | |
| + */ | |
| + return 0; | |
| + | |
| +err: | |
| + intel_context_put(ce); | |
| + return err; | |
| +} | |
| + | |
| +static void eb_put_engine(struct i915_execbuffer *eb) | |
| +{ | |
| + i915_eb_put_engine(eb->context); | |
| +} | |
| + | |
| +static int add_timeline_fence_array(struct i915_execbuffer *eb) | |
| +{ | |
| + struct drm_i915_gem_timeline_fence __user *user_fences; | |
| + struct eb_fence *f; | |
| + u64 nfences; | |
| + | |
| + nfences = eb->args->fence_count; | |
| + if (!nfences) | |
| + return 0; | |
| + | |
| + /* Check multiplication overflow for access_ok() and kvmalloc_array() */ | |
| + BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long)); | |
| + if (nfences > min_t(unsigned long, | |
| + ULONG_MAX / sizeof(*user_fences), | |
| + SIZE_MAX / sizeof(*f))) | |
| + return -EINVAL; | |
| + | |
| + user_fences = u64_to_user_ptr(eb->args->timeline_fences); | |
| + if (!access_ok(user_fences, nfences * sizeof(*user_fences))) | |
| + return -EFAULT; | |
| + | |
| + eb->fences = kcalloc(nfences, sizeof(*f), __GFP_NOWARN | GFP_KERNEL); | |
| + if (!eb->fences) | |
| + return -ENOMEM; | |
| + | |
| + f = eb->fences; | |
| + | |
| + BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) & | |
| + ~__I915_TIMELINE_FENCE_UNKNOWN_FLAGS); | |
| + | |
| + while (nfences--) { | |
| + struct drm_i915_gem_timeline_fence user_fence; | |
| + bool wait, signal; | |
| + int ret; | |
| + | |
| + if (__copy_from_user(&user_fence, | |
| + user_fences++, | |
| + sizeof(user_fence))) | |
| + return -EFAULT; | |
| + | |
| + if (user_fence.flags & __I915_TIMELINE_FENCE_UNKNOWN_FLAGS) | |
| + return -EINVAL; | |
| + | |
| + wait = user_fence.flags & I915_TIMELINE_FENCE_WAIT; | |
| + signal = user_fence.flags & I915_TIMELINE_FENCE_SIGNAL; | |
| + ret = i915_eb_add_timeline_fence(eb->i915, eb->file, | |
| + user_fence.handle, | |
| + user_fence.value, f, wait, | |
| + signal); | |
| + if (ret < 0) | |
| + return ret; | |
| + else if (!ret) | |
| + continue; | |
| + | |
| + f++; | |
| + eb->num_fences++; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int parse_timeline_fences(struct i915_execbuffer *eb) | |
| +{ | |
| + return add_timeline_fence_array(eb); | |
| +} | |
| + | |
| +static int parse_batch_addresses(struct i915_execbuffer *eb) | |
| +{ | |
| + struct drm_i915_gem_execbuffer3 *args = eb->args; | |
| + | |
| + if (eb->num_batches == 1) { | |
| + eb->batch_addresses[0] = args->batch_address; | |
| + } else { | |
| + u64 __user *batch_addr = u64_to_user_ptr(args->batch_address); | |
| + | |
| + if (copy_from_user(eb->batch_addresses, batch_addr, | |
| + sizeof(batch_addr[0]) * eb->num_batches)) | |
| + return -EFAULT; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int eb_composite_fence_create(struct i915_execbuffer *eb) | |
| +{ | |
| + struct dma_fence *fence; | |
| + | |
| + fence = i915_eb_composite_fence_create(eb->requests, eb->num_batches, | |
| + eb->context); | |
| + if (IS_ERR(fence)) | |
| + return PTR_ERR(fence); | |
| + | |
| + eb->composite_fence = fence; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq) | |
| +{ | |
| + int err; | |
| + | |
| + if (unlikely(eb->gem_context->syncobj)) { | |
| + struct dma_fence *fence; | |
| + | |
| + fence = drm_syncobj_fence_get(eb->gem_context->syncobj); | |
| + err = i915_request_await_dma_fence(rq, fence); | |
| + dma_fence_put(fence); | |
| + if (err) | |
| + return err; | |
| + } | |
| + | |
| + if (eb->fences) { | |
| + err = i915_eb_await_fence_array(eb->fences, eb->num_fences, rq); | |
| + if (err) | |
| + return err; | |
| + } | |
| + | |
| + if (intel_context_is_parallel(eb->context)) { | |
| + err = eb_composite_fence_create(eb); | |
| + if (err) | |
| + return err; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int eb_requests_create(struct i915_execbuffer *eb) | |
| +{ | |
| + int err; | |
| + | |
| + for_each_batch_create_order(eb) { | |
| + /* Allocate a request for this batch buffer nice and early. */ | |
| + eb->requests[i] = | |
| + i915_request_create(i915_eb_find_context(eb->context, | |
| + i)); | |
| + if (IS_ERR(eb->requests[i])) { | |
| + err = PTR_ERR(eb->requests[i]); | |
| + eb->requests[i] = NULL; | |
| + return err; | |
| + } | |
| + | |
| + /* | |
| + * Only the first request added (committed to backend) has to | |
| + * take the in fences into account as all subsequent requests | |
| + * will have fences inserted inbetween them. | |
| + */ | |
| + if (i + 1 == eb->num_batches) { | |
| + err = eb_fences_add(eb, eb->requests[i]); | |
| + if (err) | |
| + return err; | |
| + } | |
| + | |
| + if (eb->batches[i]) | |
| + eb->requests[i]->batch_res = | |
| + i915_vma_resource_get(eb->batches[i]->resource); | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int | |
| +i915_gem_do_execbuffer(struct drm_device *dev, | |
| + struct drm_file *file, | |
| + struct drm_i915_gem_execbuffer3 *args) | |
| +{ | |
| + struct drm_i915_private *i915 = to_i915(dev); | |
| + struct i915_execbuffer eb; | |
| + bool throttle = true; | |
| + int err; | |
| + | |
| + BUILD_BUG_ON(__EXEC3_INTERNAL_FLAGS & ~__I915_EXEC3_UNKNOWN_FLAGS); | |
| + | |
| + eb.i915 = i915; | |
| + eb.file = file; | |
| + eb.args = args; | |
| + | |
| + eb.fences = NULL; | |
| + eb.num_fences = 0; | |
| + | |
| + memset(eb.requests, 0, sizeof(struct i915_request *) * | |
| + ARRAY_SIZE(eb.requests)); | |
| + eb.composite_fence = NULL; | |
| + | |
| + err = parse_timeline_fences(&eb); | |
| + if (err) | |
| + return err; | |
| + | |
| + err = eb_select_context(&eb); | |
| + if (unlikely(err)) | |
| + goto err_fences; | |
| + | |
| + err = eb_select_engine(&eb); | |
| + if (unlikely(err)) | |
| + goto err_context; | |
| + | |
| + err = parse_batch_addresses(&eb); | |
| + if (unlikely(err)) | |
| + goto err_engine; | |
| + | |
| + mutex_lock(&eb.context->vm->vm_bind_lock); | |
| + | |
| + err = eb_lookup_vma_all(&eb); | |
| + if (err) { | |
| + eb_release_vma_all(&eb); | |
| + goto err_vm_bind_lock; | |
| + } | |
| + | |
| + i915_gem_ww_ctx_init(&eb.ww, true); | |
| + | |
| +retry_validate: | |
| + err = eb_pin_engine(&eb, throttle); | |
| + if (err) | |
| + goto err_validate; | |
| + | |
| + /* only throttle once, even if we didn't need to throttle */ | |
| + throttle = false; | |
| + | |
| +err_validate: | |
| + if (err == -EDEADLK) { | |
| + eb_release_vma_all(&eb); | |
| + err = i915_gem_ww_ctx_backoff(&eb.ww); | |
| + if (!err) | |
| + goto retry_validate; | |
| + } | |
| + if (err) | |
| + goto err_vma; | |
| + | |
| + ww_acquire_done(&eb.ww.ctx); | |
| + | |
| + err = eb_requests_create(&eb); | |
| + if (err) { | |
| + if (eb.requests[0]) | |
| + goto err_request; | |
| + else | |
| + goto err_vma; | |
| + } | |
| + | |
| + err = eb_submit(&eb); | |
| + | |
| +err_request: | |
| + i915_eb_requests_get(eb.requests, eb.num_batches); | |
| + err = i915_eb_requests_add(eb.requests, eb.num_batches, eb.context, | |
| + eb.gem_context->sched, err); | |
| + | |
| + if (eb.fences) | |
| + i915_eb_signal_fence_array(eb.fences, eb.num_fences, | |
| + eb.composite_fence ? | |
| + eb.composite_fence : | |
| + &eb.requests[0]->fence); | |
| + | |
| + if (unlikely(eb.gem_context->syncobj)) { | |
| + drm_syncobj_replace_fence(eb.gem_context->syncobj, | |
| + eb.composite_fence ? | |
| + eb.composite_fence : | |
| + &eb.requests[0]->fence); | |
| + } | |
| + | |
| + if (eb.composite_fence) | |
| + dma_fence_put(eb.composite_fence); | |
| + | |
| + i915_eb_requests_put(eb.requests, eb.num_batches); | |
| + | |
| +err_vma: | |
| + eb_release_vma_all(&eb); | |
| + WARN_ON(err == -EDEADLK); | |
| + i915_gem_ww_ctx_fini(&eb.ww); | |
| +err_vm_bind_lock: | |
| + mutex_unlock(&eb.context->vm->vm_bind_lock); | |
| +err_engine: | |
| + eb_put_engine(&eb); | |
| +err_context: | |
| + i915_gem_context_put(eb.gem_context); | |
| +err_fences: | |
| + i915_eb_put_fence_array(eb.fences, eb.num_fences); | |
| + return err; | |
| +} | |
| + | |
| +int | |
| +i915_gem_execbuffer3_ioctl(struct drm_device *dev, void *data, | |
| + struct drm_file *file) | |
| +{ | |
| + struct drm_i915_gem_execbuffer3 *args = data; | |
| + int err; | |
| + | |
| + /* Reserved fields must be 0 */ | |
| + if (args->rsvd || args->extensions) | |
| + return -EINVAL; | |
| + | |
| + if (args->flags & __I915_EXEC3_UNKNOWN_FLAGS) | |
| + return -EINVAL; | |
| + | |
| + err = i915_gem_do_execbuffer(dev, file, args); | |
| + | |
| + args->flags &= ~__I915_EXEC3_UNKNOWN_FLAGS; | |
| + return err; | |
| +} | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | |
| index 28d6526e32ab..b7a1e9725a84 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | |
| @@ -18,6 +18,8 @@ int i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, | |
| struct drm_file *file); | |
| int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, | |
| struct drm_file *file); | |
| +int i915_gem_execbuffer3_ioctl(struct drm_device *dev, void *data, | |
| + struct drm_file *file); | |
| int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
| struct drm_file *file); | |
| int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, | |
| diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c | |
| index fdc9c55829e8..4fd65805bc97 100644 | |
| --- a/drivers/gpu/drm/i915/i915_driver.c | |
| +++ b/drivers/gpu/drm/i915/i915_driver.c | |
| @@ -1733,6 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = { | |
| DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
| DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), | |
| DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), | |
| + DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER3, i915_gem_execbuffer3_ioctl, DRM_RENDER_ALLOW), | |
| DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
| DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
| DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), | |
| diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h | |
| index f35a9bb35ab3..9846d4323a42 100644 | |
| --- a/include/uapi/drm/i915_drm.h | |
| +++ b/include/uapi/drm/i915_drm.h | |
| @@ -472,6 +472,7 @@ typedef struct _drm_i915_sarea { | |
| #define DRM_I915_GEM_CREATE_EXT 0x3c | |
| #define DRM_I915_GEM_VM_BIND 0x3d | |
| #define DRM_I915_GEM_VM_UNBIND 0x3e | |
| +#define DRM_I915_GEM_EXECBUFFER3 0x3f | |
| /* Must be kept compact -- no holes */ | |
| #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
| @@ -538,6 +539,7 @@ typedef struct _drm_i915_sarea { | |
| #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) | |
| #define DRM_IOCTL_I915_GEM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_BIND, struct drm_i915_gem_vm_bind) | |
| #define DRM_IOCTL_I915_GEM_VM_UNBIND DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_UNBIND, struct drm_i915_gem_vm_unbind) | |
| +#define DRM_IOCTL_I915_GEM_EXECBUFFER3 DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER3, struct drm_i915_gem_execbuffer3) | |
| /* Allow drivers to submit batchbuffers directly to hardware, relying | |
| * on the security mechanisms provided by hardware. | |
| @@ -1568,6 +1570,65 @@ struct drm_i915_gem_timeline_fence { | |
| __u64 value; | |
| }; | |
| +/** | |
| + * struct drm_i915_gem_execbuffer3 - Structure for DRM_I915_GEM_EXECBUFFER3 | |
| + * ioctl. | |
| + * | |
| + * DRM_I915_GEM_EXECBUFFER3 ioctl only works in VM_BIND mode and VM_BIND mode | |
| + * only works with this ioctl for submission. | |
| + * See I915_VM_CREATE_FLAGS_USE_VM_BIND. | |
| + */ | |
| +struct drm_i915_gem_execbuffer3 { | |
| + /** | |
| + * @ctx_id: Context id | |
| + * | |
| + * Only contexts with user engine map are allowed. | |
| + */ | |
| + __u32 ctx_id; | |
| + | |
| + /** | |
| + * @engine_idx: Engine index | |
| + * | |
| + * An index in the user engine map of the context specified by @ctx_id. | |
| + */ | |
| + __u32 engine_idx; | |
| + | |
| + /** | |
| + * @batch_address: Batch gpu virtual address/es. | |
| + * | |
| + * For normal submission, it is the gpu virtual address of the batch | |
| + * buffer. For parallel submission, it is a pointer to an array of | |
| + * batch buffer gpu virtual addresses with array size equal to the | |
| + * number of (parallel) engines involved in that submission (See | |
| + * struct i915_context_engines_parallel_submit). | |
| + */ | |
| + __u64 batch_address; | |
| + | |
| + /** @flags: Currently reserved, MBZ */ | |
| + __u64 flags; | |
| +#define __I915_EXEC3_UNKNOWN_FLAGS (~0ull) | |
| + | |
| + /** @fence_count: Number of fences in @timeline_fences array. */ | |
| + __u64 fence_count; | |
| + | |
| + /** | |
| + * @timeline_fences: Pointer to an array of timeline fences. | |
| + * | |
| + * Timeline fences are of format struct drm_i915_gem_timeline_fence. | |
| + */ | |
| + __u64 timeline_fences; | |
| + | |
| + /** @rsvd: Reserved, MBZ */ | |
| + __u64 rsvd; | |
| + | |
| + /** | |
| + * @extensions: Zero-terminated chain of extensions. | |
| + * | |
| + * For future extensions. See struct i915_user_extension. | |
| + */ | |
| + __u64 extensions; | |
| +}; | |
| + | |
| struct drm_i915_gem_pin { | |
| /** Handle of the buffer to be pinned. */ | |
| __u32 handle; | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
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| by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
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| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 14/23] drm/i915/vm_bind: Update | |
| i915_vma_verify_bind_complete() | |
| Date: Tue, 17 Jan 2023 23:16:00 -0800 | |
| Message-Id: <20230118071609.17572-15-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Ensure i915_vma_verify_bind_complete() handles case where bind | |
| is not initiated. Also make it non static, add documentation | |
| and move it out of CONFIG_DRM_I915_DEBUG_GEM. | |
| v2: Fix fence leak | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/i915_vma.c | 22 ++++++++++++++++------ | |
| drivers/gpu/drm/i915/i915_vma.h | 1 + | |
| 2 files changed, 17 insertions(+), 6 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 763ead20ad55..804f01b9002d 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -443,12 +443,25 @@ int i915_vma_sync(struct i915_vma *vma) | |
| return i915_vm_sync(vma->vm); | |
| } | |
| -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) | |
| -static int i915_vma_verify_bind_complete(struct i915_vma *vma) | |
| +/** | |
| + * i915_vma_verify_bind_complete() - Check for the bind completion of the vma | |
| + * @vma: vma to check for bind completion | |
| + * | |
| + * As the fence reference is obtained under RCU, no locking is required by | |
| + * the caller. | |
| + * | |
| + * Returns: 0 if the vma bind is completed. Error code otherwise. | |
| + */ | |
| +int i915_vma_verify_bind_complete(struct i915_vma *vma) | |
| { | |
| - struct dma_fence *fence = i915_active_fence_get(&vma->active.excl); | |
| + struct dma_fence *fence; | |
| int err; | |
| + /* Ensure vma bind is initiated */ | |
| + if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK)) | |
| + return -EINVAL; | |
| + | |
| + fence = i915_active_fence_get(&vma->active.excl); | |
| if (!fence) | |
| return 0; | |
| @@ -461,9 +474,6 @@ static int i915_vma_verify_bind_complete(struct i915_vma *vma) | |
| return err; | |
| } | |
| -#else | |
| -#define i915_vma_verify_bind_complete(_vma) 0 | |
| -#endif | |
| I915_SELFTEST_EXPORT void | |
| i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res, | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h | |
| index de1756e4f638..1f25e45a6325 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma.h | |
| @@ -487,6 +487,7 @@ void i915_vma_make_purgeable(struct i915_vma *vma); | |
| int i915_vma_wait_for_bind(struct i915_vma *vma); | |
| int i915_vma_sync(struct i915_vma *vma); | |
| +int i915_vma_verify_bind_complete(struct i915_vma *vma); | |
| /** | |
| * i915_vma_get_current_resource - Get the current resource of the vma | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| by smtp.lore.kernel.org (Postfix) with ESMTPS id E7FECC54EBE | |
| for <dri-devel@archiver.kernel.org>; Wed, 18 Jan 2023 07:17:21 +0000 (UTC) | |
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| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 15/23] drm/i915/vm_bind: Expose i915_request_await_bind() | |
| Date: Tue, 17 Jan 2023 23:16:01 -0800 | |
| Message-Id: <20230118071609.17572-16-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
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| Rename __i915_request_await_bind() as i915_request_await_bind() | |
| and make it non-static as it will be used in execbuf3 ioctl path. | |
| v2: add documentation | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| drivers/gpu/drm/i915/i915_vma.c | 8 +------- | |
| drivers/gpu/drm/i915/i915_vma.h | 16 ++++++++++++++++ | |
| 2 files changed, 17 insertions(+), 7 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 804f01b9002d..8fc93f20f70d 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -1926,18 +1926,12 @@ void i915_vma_revoke_mmap(struct i915_vma *vma) | |
| list_del(&vma->obj->userfault_link); | |
| } | |
| -static int | |
| -__i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma) | |
| -{ | |
| - return __i915_request_await_exclusive(rq, &vma->active); | |
| -} | |
| - | |
| static int __i915_vma_move_to_active(struct i915_vma *vma, struct i915_request *rq) | |
| { | |
| int err; | |
| /* Wait for the vma to be bound before we start! */ | |
| - err = __i915_request_await_bind(rq, vma); | |
| + err = i915_request_await_bind(rq, vma); | |
| if (err) | |
| return err; | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h | |
| index 1f25e45a6325..d6c05227fb04 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma.h | |
| @@ -55,6 +55,22 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma, unsigned int flags); | |
| #define __EXEC_OBJECT_NO_RESERVE BIT(31) | |
| #define __EXEC_OBJECT_NO_REQUEST_AWAIT BIT(30) | |
| +/** | |
| + * i915_request_await_bind() - Setup request to wait for a vma bind completion | |
| + * @rq: the request which should wait | |
| + * @vma: vma whose binding @rq should wait to complete | |
| + * | |
| + * Setup the request @rq to asynchronously wait for @vma bind to complete | |
| + * before starting execution. | |
| + * | |
| + * Returns 0 on success, error code on failure. | |
| + */ | |
| +static inline int | |
| +i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma) | |
| +{ | |
| + return __i915_request_await_exclusive(rq, &vma->active); | |
| +} | |
| + | |
| int __must_check _i915_vma_move_to_active(struct i915_vma *vma, | |
| struct i915_request *rq, | |
| struct dma_fence *fence, | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 16/23] drm/i915/vm_bind: Handle persistent vmas in execbuf3 | |
| Date: Tue, 17 Jan 2023 23:16:02 -0800 | |
| Message-Id: <20230118071609.17572-17-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Handle persistent (VM_BIND) mappings during the request submission | |
| in the execbuf3 path. | |
| v2: Ensure requests wait for bindings to complete. | |
| v3: Remove short term pinning with PIN_VALIDATE flag. | |
| Individualize fences before adding to dma_resv obj. | |
| v4: Fix bind completion check, use PIN_NOEVICT, | |
| use proper lock while checking if vm_rebind_list is empty. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 215 +++++++++++++++++- | |
| 1 file changed, 214 insertions(+), 1 deletion(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| index 49045858a3e9..913b1f8bda9f 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| @@ -3,6 +3,7 @@ | |
| * Copyright © 2022 Intel Corporation | |
| */ | |
| +#include <linux/dma-fence-array.h> | |
| #include <linux/dma-resv.h> | |
| #include <linux/uaccess.h> | |
| @@ -19,6 +20,7 @@ | |
| #include "i915_gem_vm_bind.h" | |
| #include "i915_trace.h" | |
| +#define __EXEC3_HAS_PIN BIT_ULL(33) | |
| #define __EXEC3_ENGINE_PINNED BIT_ULL(32) | |
| #define __EXEC3_INTERNAL_FLAGS (~0ull << 32) | |
| @@ -42,7 +44,9 @@ | |
| * execlist. Hence, no support for implicit sync. | |
| * | |
| * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only | |
| - * works with execbuf3 ioctl for submission. | |
| + * works with execbuf3 ioctl for submission. All BOs mapped on that VM (through | |
| + * VM_BIND call) at the time of execbuf3 call are deemed required for that | |
| + * submission. | |
| * | |
| * The execbuf3 ioctl directly specifies the batch addresses instead of as | |
| * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not | |
| @@ -58,6 +62,13 @@ | |
| * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions, | |
| * vma lookup table, implicit sync, vma active reference tracking etc., are not | |
| * applicable for execbuf3 ioctl. | |
| + * | |
| + * During each execbuf submission, request fence is added to all VM_BIND mapped | |
| + * objects with DMA_RESV_USAGE_BOOKKEEP. The DMA_RESV_USAGE_BOOKKEEP usage will | |
| + * prevent over sync (See enum dma_resv_usage). Note that DRM_I915_GEM_WAIT and | |
| + * DRM_I915_GEM_BUSY ioctls do not check for DMA_RESV_USAGE_BOOKKEEP usage and | |
| + * hence should not be used for end of batch check. Instead, the execbuf3 | |
| + * timeline out fence should be used for end of batch check. | |
| */ | |
| /** | |
| @@ -129,6 +140,23 @@ eb_find_vma(struct i915_address_space *vm, u64 addr) | |
| return i915_gem_vm_bind_lookup_vma(vm, va); | |
| } | |
| +static void eb_scoop_unbound_vma_all(struct i915_address_space *vm) | |
| +{ | |
| + struct i915_vma *vma, *vn; | |
| + | |
| + /** | |
| + * Move all unbound vmas back into vm_bind_list so that they are | |
| + * revalidated. | |
| + */ | |
| + spin_lock(&vm->vm_rebind_lock); | |
| + list_for_each_entry_safe(vma, vn, &vm->vm_rebind_list, vm_rebind_link) { | |
| + list_del_init(&vma->vm_rebind_link); | |
| + if (!list_empty(&vma->vm_bind_link)) | |
| + list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list); | |
| + } | |
| + spin_unlock(&vm->vm_rebind_lock); | |
| +} | |
| + | |
| static int eb_lookup_vma_all(struct i915_execbuffer *eb) | |
| { | |
| struct i915_vma *vma; | |
| @@ -142,14 +170,108 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb) | |
| eb->batches[i] = vma; | |
| } | |
| + eb_scoop_unbound_vma_all(eb->context->vm); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int eb_lock_vma_all(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_address_space *vm = eb->context->vm; | |
| + struct i915_vma *vma; | |
| + int err; | |
| + | |
| + err = i915_gem_object_lock(eb->context->vm->root_obj, &eb->ww); | |
| + if (err) | |
| + return err; | |
| + | |
| + list_for_each_entry(vma, &vm->non_priv_vm_bind_list, | |
| + non_priv_vm_bind_link) { | |
| + err = i915_gem_object_lock(vma->obj, &eb->ww); | |
| + if (err) | |
| + return err; | |
| + } | |
| + | |
| return 0; | |
| } | |
| +static void eb_release_persistent_vma_all(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_address_space *vm = eb->context->vm; | |
| + struct i915_vma *vma, *vn; | |
| + | |
| + lockdep_assert_held(&vm->vm_bind_lock); | |
| + | |
| + if (!(eb->args->flags & __EXEC3_HAS_PIN)) | |
| + return; | |
| + | |
| + assert_object_held(vm->root_obj); | |
| + | |
| + list_for_each_entry_safe(vma, vn, &vm->vm_bind_list, vm_bind_link) | |
| + if (!i915_vma_verify_bind_complete(vma)) | |
| + list_move_tail(&vma->vm_bind_link, &vm->vm_bound_list); | |
| + | |
| + eb->args->flags &= ~__EXEC3_HAS_PIN; | |
| +} | |
| + | |
| static void eb_release_vma_all(struct i915_execbuffer *eb) | |
| { | |
| + eb_release_persistent_vma_all(eb); | |
| eb_unpin_engine(eb); | |
| } | |
| +static int eb_reserve_fence_for_persistent_vma_all(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_address_space *vm = eb->context->vm; | |
| + u64 num_fences = 1; | |
| + struct i915_vma *vma; | |
| + int ret; | |
| + | |
| + /* Reserve enough slots to accommodate composite fences */ | |
| + if (intel_context_is_parallel(eb->context)) | |
| + num_fences = eb->num_batches; | |
| + | |
| + ret = dma_resv_reserve_fences(vm->root_obj->base.resv, num_fences); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + list_for_each_entry(vma, &vm->non_priv_vm_bind_list, | |
| + non_priv_vm_bind_link) { | |
| + ret = dma_resv_reserve_fences(vma->obj->base.resv, num_fences); | |
| + if (ret) | |
| + return ret; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int eb_validate_persistent_vma_all(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_address_space *vm = eb->context->vm; | |
| + struct i915_vma *vma; | |
| + int ret = 0; | |
| + | |
| + lockdep_assert_held(&vm->vm_bind_lock); | |
| + assert_object_held(vm->root_obj); | |
| + | |
| + ret = eb_reserve_fence_for_persistent_vma_all(eb); | |
| + if (ret) | |
| + return ret; | |
| + | |
| + list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) { | |
| + u64 pin_flags = vma->start | PIN_OFFSET_FIXED | PIN_USER | | |
| + PIN_VALIDATE | PIN_NOEVICT; | |
| + | |
| + ret = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags); | |
| + if (ret) | |
| + break; | |
| + | |
| + eb->args->flags |= __EXEC3_HAS_PIN; | |
| + } | |
| + | |
| + return ret; | |
| +} | |
| + | |
| /* | |
| * Using two helper loops for the order of which requests / batches are created | |
| * and added the to backend. Requests are created in order from the parent to | |
| @@ -161,13 +283,80 @@ static void eb_release_vma_all(struct i915_execbuffer *eb) | |
| */ | |
| #define for_each_batch_create_order(_eb) \ | |
| for (unsigned int i = 0; i < (_eb)->num_batches; ++i) | |
| +#define for_each_batch_add_order(_eb) \ | |
| + for (int i = (_eb)->num_batches - 1; i >= 0; --i) | |
| + | |
| +static void __eb_persistent_add_shared_fence(struct drm_i915_gem_object *obj, | |
| + struct dma_fence *fence) | |
| +{ | |
| + struct dma_fence *curr; | |
| + int idx; | |
| + | |
| + dma_fence_array_for_each(curr, idx, fence) | |
| + dma_resv_add_fence(obj->base.resv, curr, | |
| + DMA_RESV_USAGE_BOOKKEEP); | |
| + | |
| + obj->write_domain = 0; | |
| + obj->read_domains |= I915_GEM_GPU_DOMAINS; | |
| + obj->mm.dirty = true; | |
| +} | |
| + | |
| +static void eb_persistent_add_shared_fence(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_address_space *vm = eb->context->vm; | |
| + struct dma_fence *fence; | |
| + struct i915_vma *vma; | |
| + | |
| + fence = eb->composite_fence ? eb->composite_fence : | |
| + &eb->requests[0]->fence; | |
| + | |
| + __eb_persistent_add_shared_fence(vm->root_obj, fence); | |
| + list_for_each_entry(vma, &vm->non_priv_vm_bind_list, | |
| + non_priv_vm_bind_link) | |
| + __eb_persistent_add_shared_fence(vma->obj, fence); | |
| +} | |
| + | |
| +static void eb_move_all_persistent_vma_to_active(struct i915_execbuffer *eb) | |
| +{ | |
| + /* Add fence to BOs dma-resv fence list */ | |
| + eb_persistent_add_shared_fence(eb); | |
| +} | |
| static int eb_move_to_gpu(struct i915_execbuffer *eb) | |
| { | |
| + struct i915_address_space *vm = eb->context->vm; | |
| + struct i915_vma *vma; | |
| + int err = 0; | |
| + | |
| + lockdep_assert_held(&vm->vm_bind_lock); | |
| + assert_object_held(vm->root_obj); | |
| + | |
| + eb_move_all_persistent_vma_to_active(eb); | |
| + | |
| + list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) { | |
| + for_each_batch_add_order(eb) { | |
| + if (!eb->requests[i]) | |
| + continue; | |
| + | |
| + err = i915_request_await_bind(eb->requests[i], vma); | |
| + if (err) | |
| + goto err_skip; | |
| + } | |
| + } | |
| + | |
| /* Unconditionally flush any chipset caches (for streaming writes). */ | |
| intel_gt_chipset_flush(eb->gt); | |
| return 0; | |
| + | |
| +err_skip: | |
| + for_each_batch_create_order(eb) { | |
| + if (!eb->requests[i]) | |
| + break; | |
| + | |
| + i915_request_set_error_once(eb->requests[i], err); | |
| + } | |
| + return err; | |
| } | |
| static int eb_request_submit(struct i915_execbuffer *eb, | |
| @@ -482,6 +671,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, | |
| mutex_lock(&eb.context->vm->vm_bind_lock); | |
| +lookup_vmas: | |
| err = eb_lookup_vma_all(&eb); | |
| if (err) { | |
| eb_release_vma_all(&eb); | |
| @@ -498,6 +688,29 @@ i915_gem_do_execbuffer(struct drm_device *dev, | |
| /* only throttle once, even if we didn't need to throttle */ | |
| throttle = false; | |
| + err = eb_lock_vma_all(&eb); | |
| + if (err) | |
| + goto err_validate; | |
| + | |
| + /** | |
| + * No object unbinds possible once the objects are locked. So, | |
| + * check for any unbinds here, which needs to be scooped up. | |
| + * | |
| + * XXX: Probably vm_rebind_list can be scooped in the validation | |
| + * phase instead of lookup phase, after holding object locks. | |
| + * Then this check won't be needed. | |
| + */ | |
| + spin_lock(&eb.context->vm->vm_rebind_lock); | |
| + if (!list_empty(&eb.context->vm->vm_rebind_list)) { | |
| + spin_unlock(&eb.context->vm->vm_rebind_lock); | |
| + eb_release_vma_all(&eb); | |
| + i915_gem_ww_ctx_fini(&eb.ww); | |
| + goto lookup_vmas; | |
| + } | |
| + spin_unlock(&eb.context->vm->vm_rebind_lock); | |
| + | |
| + err = eb_validate_persistent_vma_all(&eb); | |
| + | |
| err_validate: | |
| if (err == -EDEADLK) { | |
| eb_release_vma_all(&eb); | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| (No client certificate requested) | |
| by smtp.lore.kernel.org (Postfix) with ESMTPS id A7EFBC004D4 | |
| for <dri-devel@archiver.kernel.org>; Wed, 18 Jan 2023 07:17:20 +0000 (UTC) | |
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| Wed, 18 Jan 2023 07:17:10 +0000 (UTC) | |
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| by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:15 -0800 | |
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| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 17/23] drm/i915/vm_bind: userptr dma-resv changes | |
| Date: Tue, 17 Jan 2023 23:16:03 -0800 | |
| Message-Id: <20230118071609.17572-18-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| For persistent (vm_bind) vmas of userptr BOs, handle the user | |
| page pinning by using the i915_gem_object_userptr_submit_init() | |
| /done() functions | |
| v2: Do not double add vma to vm->userptr_invalidated_list | |
| v3: Initialize vma->userptr_invalidated_link | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 84 ++++++++++++++++++- | |
| drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 19 +++++ | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 15 ++++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.c | 2 + | |
| drivers/gpu/drm/i915/gt/intel_gtt.h | 4 + | |
| drivers/gpu/drm/i915/i915_vma.c | 1 + | |
| drivers/gpu/drm/i915/i915_vma_types.h | 2 + | |
| 7 files changed, 125 insertions(+), 2 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| index 913b1f8bda9f..a1aee477e2df 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| @@ -20,6 +20,7 @@ | |
| #include "i915_gem_vm_bind.h" | |
| #include "i915_trace.h" | |
| +#define __EXEC3_USERPTR_USED BIT_ULL(34) | |
| #define __EXEC3_HAS_PIN BIT_ULL(33) | |
| #define __EXEC3_ENGINE_PINNED BIT_ULL(32) | |
| #define __EXEC3_INTERNAL_FLAGS (~0ull << 32) | |
| @@ -144,7 +145,22 @@ static void eb_scoop_unbound_vma_all(struct i915_address_space *vm) | |
| { | |
| struct i915_vma *vma, *vn; | |
| - /** | |
| +#ifdef CONFIG_MMU_NOTIFIER | |
| + /* | |
| + * Move all invalidated userptr vmas back into vm_bind_list so that | |
| + * they are looked up and revalidated. | |
| + */ | |
| + spin_lock(&vm->userptr_invalidated_lock); | |
| + list_for_each_entry_safe(vma, vn, &vm->userptr_invalidated_list, | |
| + userptr_invalidated_link) { | |
| + list_del_init(&vma->userptr_invalidated_link); | |
| + if (!list_empty(&vma->vm_bind_link)) | |
| + list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list); | |
| + } | |
| + spin_unlock(&vm->userptr_invalidated_lock); | |
| +#endif | |
| + | |
| + /* | |
| * Move all unbound vmas back into vm_bind_list so that they are | |
| * revalidated. | |
| */ | |
| @@ -157,10 +173,47 @@ static void eb_scoop_unbound_vma_all(struct i915_address_space *vm) | |
| spin_unlock(&vm->vm_rebind_lock); | |
| } | |
| +static int eb_lookup_persistent_userptr_vmas(struct i915_execbuffer *eb) | |
| +{ | |
| + struct i915_address_space *vm = eb->context->vm; | |
| + struct i915_vma *last_vma = NULL; | |
| + struct i915_vma *vma; | |
| + int err; | |
| + | |
| + lockdep_assert_held(&vm->vm_bind_lock); | |
| + | |
| + list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) { | |
| + if (!i915_gem_object_is_userptr(vma->obj)) | |
| + continue; | |
| + | |
| + err = i915_gem_object_userptr_submit_init(vma->obj); | |
| + if (err) | |
| + return err; | |
| + | |
| + /* | |
| + * The above submit_init() call does the object unbind and | |
| + * hence adds vma into vm_rebind_list. Remove it from that | |
| + * list as it is already scooped for revalidation. | |
| + */ | |
| + spin_lock(&vm->vm_rebind_lock); | |
| + if (!list_empty(&vma->vm_rebind_link)) | |
| + list_del_init(&vma->vm_rebind_link); | |
| + spin_unlock(&vm->vm_rebind_lock); | |
| + | |
| + last_vma = vma; | |
| + } | |
| + | |
| + if (last_vma) | |
| + eb->args->flags |= __EXEC3_USERPTR_USED; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| static int eb_lookup_vma_all(struct i915_execbuffer *eb) | |
| { | |
| struct i915_vma *vma; | |
| unsigned int i; | |
| + int err = 0; | |
| for (i = 0; i < eb->num_batches; i++) { | |
| vma = eb_find_vma(eb->context->vm, eb->batch_addresses[i]); | |
| @@ -172,6 +225,10 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb) | |
| eb_scoop_unbound_vma_all(eb->context->vm); | |
| + err = eb_lookup_persistent_userptr_vmas(eb); | |
| + if (err) | |
| + return err; | |
| + | |
| return 0; | |
| } | |
| @@ -344,6 +401,29 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) | |
| } | |
| } | |
| +#ifdef CONFIG_MMU_NOTIFIER | |
| + /* Check for further userptr invalidations */ | |
| + spin_lock(&vm->userptr_invalidated_lock); | |
| + if (!list_empty(&vm->userptr_invalidated_list)) | |
| + err = -EAGAIN; | |
| + spin_unlock(&vm->userptr_invalidated_lock); | |
| + | |
| + if (!err && (eb->args->flags & __EXEC3_USERPTR_USED)) { | |
| + read_lock(&eb->i915->mm.notifier_lock); | |
| + list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) { | |
| + if (!i915_gem_object_is_userptr(vma->obj)) | |
| + continue; | |
| + | |
| + err = i915_gem_object_userptr_submit_done(vma->obj); | |
| + if (err) | |
| + break; | |
| + } | |
| + read_unlock(&eb->i915->mm.notifier_lock); | |
| + } | |
| +#endif | |
| + if (unlikely(err)) | |
| + goto err_skip; | |
| + | |
| /* Unconditionally flush any chipset caches (for streaming writes). */ | |
| intel_gt_chipset_flush(eb->gt); | |
| @@ -692,7 +772,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, | |
| if (err) | |
| goto err_validate; | |
| - /** | |
| + /* | |
| * No object unbinds possible once the objects are locked. So, | |
| * check for any unbinds here, which needs to be scooped up. | |
| * | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c | |
| index 9348b1804d53..5ce75d533b45 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c | |
| @@ -63,6 +63,7 @@ static bool i915_gem_userptr_invalidate(struct mmu_interval_notifier *mni, | |
| { | |
| struct drm_i915_gem_object *obj = container_of(mni, struct drm_i915_gem_object, userptr.notifier); | |
| struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
| + struct i915_vma *vma; | |
| long r; | |
| if (!mmu_notifier_range_blockable(range)) | |
| @@ -85,6 +86,24 @@ static bool i915_gem_userptr_invalidate(struct mmu_interval_notifier *mni, | |
| if (current->flags & PF_EXITING) | |
| return true; | |
| + /** | |
| + * Add persistent vmas into userptr_invalidated list for relookup | |
| + * and revalidation. | |
| + */ | |
| + spin_lock(&obj->vma.lock); | |
| + list_for_each_entry(vma, &obj->vma.list, obj_link) { | |
| + if (!i915_vma_is_persistent(vma)) | |
| + continue; | |
| + | |
| + spin_lock(&vma->vm->userptr_invalidated_lock); | |
| + if (list_empty(&vma->userptr_invalidated_link) && | |
| + !i915_vma_is_purged(vma)) | |
| + list_add_tail(&vma->userptr_invalidated_link, | |
| + &vma->vm->userptr_invalidated_list); | |
| + spin_unlock(&vma->vm->userptr_invalidated_lock); | |
| + } | |
| + spin_unlock(&obj->vma.lock); | |
| + | |
| /* we will unbind on next submission, still have userptr pins */ | |
| r = dma_resv_wait_timeout(obj->base.resv, DMA_RESV_USAGE_BOOKKEEP, false, | |
| MAX_SCHEDULE_TIMEOUT); | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| index fd1d82ce99e6..1cc0b8a4e0e7 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| @@ -306,6 +306,12 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| goto put_obj; | |
| } | |
| + if (i915_gem_object_is_userptr(obj)) { | |
| + ret = i915_gem_object_userptr_submit_init(obj); | |
| + if (ret) | |
| + goto put_obj; | |
| + } | |
| + | |
| ret = mutex_lock_interruptible(&vm->vm_bind_lock); | |
| if (ret) | |
| goto put_obj; | |
| @@ -335,6 +341,15 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| if (ret) | |
| continue; | |
| +#ifdef CONFIG_MMU_NOTIFIER | |
| + if (i915_gem_object_is_userptr(obj)) { | |
| + read_lock(&vm->i915->mm.notifier_lock); | |
| + ret = i915_gem_object_userptr_submit_done(obj); | |
| + read_unlock(&vm->i915->mm.notifier_lock); | |
| + if (ret) | |
| + continue; | |
| + } | |
| +#endif | |
| /* If out fence is not requested, wait for bind to complete */ | |
| if (!(va->fence.flags & I915_TIMELINE_FENCE_SIGNAL)) { | |
| ret = i915_vma_wait_for_bind(vma); | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| index 4f91857dca46..7045b2114df6 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| @@ -294,6 +294,8 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) | |
| INIT_LIST_HEAD(&vm->non_priv_vm_bind_list); | |
| INIT_LIST_HEAD(&vm->vm_rebind_list); | |
| spin_lock_init(&vm->vm_rebind_lock); | |
| + spin_lock_init(&vm->userptr_invalidated_lock); | |
| + INIT_LIST_HEAD(&vm->userptr_invalidated_list); | |
| } | |
| void *__px_vaddr(struct drm_i915_gem_object *p) | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| index dbe6792df3e5..620b4e020a9f 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| @@ -270,6 +270,10 @@ struct i915_address_space { | |
| struct list_head vm_rebind_list; | |
| /** @vm_rebind_lock: protects vm_rebound_list */ | |
| spinlock_t vm_rebind_lock; | |
| + /** @userptr_invalidated_list: list of invalidated userptr vmas */ | |
| + struct list_head userptr_invalidated_list; | |
| + /** @userptr_invalidated_lock: protects userptr_invalidated_list */ | |
| + spinlock_t userptr_invalidated_lock; | |
| /** @va: tree of persistent vmas */ | |
| struct rb_root_cached va; | |
| /** @non_priv_vm_bind_list: list of non-private object mappings */ | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 8fc93f20f70d..59462812ef4e 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -247,6 +247,7 @@ vma_create(struct drm_i915_gem_object *obj, | |
| INIT_LIST_HEAD(&vma->vm_bind_link); | |
| INIT_LIST_HEAD(&vma->non_priv_vm_bind_link); | |
| INIT_LIST_HEAD(&vma->vm_rebind_link); | |
| + INIT_LIST_HEAD(&vma->userptr_invalidated_link); | |
| return vma; | |
| err_unlock: | |
| diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h | |
| index 4c386473923a..89f9854a6f69 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma_types.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma_types.h | |
| @@ -308,6 +308,8 @@ struct i915_vma { | |
| struct list_head non_priv_vm_bind_link; | |
| /** @vm_rebind_link: link to vm_rebind_list and protected by vm_rebind_lock */ | |
| struct list_head vm_rebind_link; /* Link in vm_rebind_list */ | |
| + /** @userptr_invalidated_link: link to the vm->userptr_invalidated_list */ | |
| + struct list_head userptr_invalidated_link; | |
| /** Timeline fence for vm_bind completion notification */ | |
| struct { | |
| -- | |
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| by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 18/23] drm/i915/vm_bind: Limit vm_bind mode to | |
| non-recoverable contexts | |
| Date: Tue, 17 Jan 2023 23:16:04 -0800 | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Only support vm_bind mode with non-recoverable contexts. | |
| With new vm_bind mode with eb3 submission path, we need not | |
| support older recoverable contexts. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++++++ | |
| 1 file changed, 6 insertions(+) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| index fb4d2dab5053..9809c58316c2 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| @@ -1616,6 +1616,12 @@ i915_gem_create_context(struct drm_i915_private *i915, | |
| INIT_LIST_HEAD(&ctx->stale.engines); | |
| if (pc->vm) { | |
| + /* Only non-recoverable contexts are allowed in vm_bind mode */ | |
| + if (i915_gem_vm_is_vm_bind_mode(pc->vm) && | |
| + (pc->user_flags & BIT(UCONTEXT_RECOVERABLE))) { | |
| + err = -EINVAL; | |
| + goto err_ctx; | |
| + } | |
| vm = i915_vm_get(pc->vm); | |
| } else if (HAS_FULL_PPGTT(i915)) { | |
| struct i915_ppgtt *ppgtt; | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| for <dri-devel@archiver.kernel.org>; Wed, 18 Jan 2023 07:17:23 +0000 (UTC) | |
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| Wed, 18 Jan 2023 07:17:12 +0000 (UTC) | |
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| 17 Jan 2023 23:16:15 -0800 | |
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| by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 19/23] drm/i915/vm_bind: Add uapi for user to enable | |
| vm_bind_mode | |
| Date: Tue, 17 Jan 2023 23:16:05 -0800 | |
| Message-Id: <20230118071609.17572-20-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Add getparam support for VM_BIND capability version. | |
| Add VM creation time flag to enable vm_bind_mode for the VM. | |
| v2: update kernel-doc | |
| v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND | |
| v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode() | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| --- | |
| drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 ++++++++++++++++++-- | |
| drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 +-- | |
| drivers/gpu/drm/i915/gt/intel_gtt.c | 2 ++ | |
| drivers/gpu/drm/i915/i915_drv.h | 2 ++ | |
| drivers/gpu/drm/i915/i915_getparam.c | 3 +++ | |
| include/uapi/drm/i915_drm.h | 26 ++++++++++++++++++++- | |
| 6 files changed, 56 insertions(+), 5 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| index 9809c58316c2..ba4aca5ff432 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c | |
| @@ -1812,9 +1812,13 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data, | |
| if (!HAS_FULL_PPGTT(i915)) | |
| return -ENODEV; | |
| - if (args->flags) | |
| + if (args->flags & I915_VM_CREATE_FLAGS_UNKNOWN) | |
| return -EINVAL; | |
| + if ((args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) && | |
| + !HAS_VM_BIND(i915)) | |
| + return -EOPNOTSUPP; | |
| + | |
| ppgtt = i915_ppgtt_create(to_gt(i915), 0); | |
| if (IS_ERR(ppgtt)) | |
| return PTR_ERR(ppgtt); | |
| @@ -1827,15 +1831,32 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data, | |
| goto err_put; | |
| } | |
| + if (args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) { | |
| + struct drm_i915_gem_object *obj; | |
| + | |
| + obj = i915_gem_object_create_internal(i915, PAGE_SIZE); | |
| + if (IS_ERR(obj)) { | |
| + err = PTR_ERR(obj); | |
| + goto err_put; | |
| + } | |
| + | |
| + ppgtt->vm.root_obj = obj; | |
| + } | |
| + | |
| err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm, | |
| xa_limit_32b, GFP_KERNEL); | |
| if (err) | |
| - goto err_put; | |
| + goto err_root_obj_put; | |
| GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */ | |
| args->vm_id = id; | |
| return 0; | |
| +err_root_obj_put: | |
| + if (ppgtt->vm.root_obj) { | |
| + i915_gem_object_put(ppgtt->vm.root_obj); | |
| + ppgtt->vm.root_obj = NULL; | |
| + } | |
| err_put: | |
| i915_vm_put(&ppgtt->vm); | |
| return err; | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| index e8b41aa8f8c4..b53aef2853cb 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h | |
| @@ -150,8 +150,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, | |
| */ | |
| static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm) | |
| { | |
| - /* No support to enable vm_bind mode yet */ | |
| - return false; | |
| + return !!vm->root_obj; | |
| } | |
| struct i915_address_space * | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| index 7045b2114df6..2e4c9fabf3b8 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| @@ -180,6 +180,8 @@ int i915_vm_lock_objects(struct i915_address_space *vm, | |
| void i915_address_space_fini(struct i915_address_space *vm) | |
| { | |
| drm_mm_takedown(&vm->mm); | |
| + if (vm->root_obj) | |
| + i915_gem_object_put(vm->root_obj); | |
| GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root)); | |
| mutex_destroy(&vm->vm_bind_lock); | |
| } | |
| diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h | |
| index 48fd82722f12..030ad237158b 100644 | |
| --- a/drivers/gpu/drm/i915/i915_drv.h | |
| +++ b/drivers/gpu/drm/i915/i915_drv.h | |
| @@ -931,4 +931,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, | |
| #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ | |
| GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) | |
| +#define HAS_VM_BIND(i915) (GRAPHICS_VER(i915) >= 12) | |
| + | |
| #endif | |
| diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c | |
| index 61ef2d9cfa62..20c1bf904a65 100644 | |
| --- a/drivers/gpu/drm/i915/i915_getparam.c | |
| +++ b/drivers/gpu/drm/i915/i915_getparam.c | |
| @@ -178,6 +178,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, | |
| case I915_PARAM_OA_TIMESTAMP_FREQUENCY: | |
| value = i915_perf_oa_timestamp_frequency(i915); | |
| break; | |
| + case I915_PARAM_VM_BIND_VERSION: | |
| + value = HAS_VM_BIND(i915); | |
| + break; | |
| default: | |
| drm_dbg(&i915->drm, "Unknown parameter %d\n", param->param); | |
| return -EINVAL; | |
| diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h | |
| index 9846d4323a42..3f27001a2c8d 100644 | |
| --- a/include/uapi/drm/i915_drm.h | |
| +++ b/include/uapi/drm/i915_drm.h | |
| @@ -777,6 +777,22 @@ typedef struct drm_i915_irq_wait { | |
| */ | |
| #define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57 | |
| +/* | |
| + * VM_BIND feature version supported. | |
| + * | |
| + * The following versions of VM_BIND have been defined: | |
| + * | |
| + * 0: No VM_BIND support. | |
| + * | |
| + * 1: In VM_UNBIND calls, the UMD must specify the exact mappings created | |
| + * previously with VM_BIND, the ioctl will not support unbinding multiple | |
| + * mappings or splitting them. Similarly, VM_BIND calls will not replace | |
| + * any existing mappings. | |
| + * | |
| + * See struct drm_i915_gem_vm_bind and struct drm_i915_gem_vm_unbind. | |
| + */ | |
| +#define I915_PARAM_VM_BIND_VERSION 58 | |
| + | |
| /* Must be kept compact -- no holes and well documented */ | |
| /** | |
| @@ -2644,7 +2660,15 @@ struct drm_i915_gem_vm_control { | |
| /** @extensions: Zero-terminated chain of extensions. */ | |
| __u64 extensions; | |
| - /** @flags: reserved for future usage, currently MBZ */ | |
| + /** | |
| + * @flags: Supported flags are, | |
| + * | |
| + * I915_VM_CREATE_FLAGS_USE_VM_BIND: | |
| + * | |
| + * VM created will work in VM_BIND mode. | |
| + */ | |
| +#define I915_VM_CREATE_FLAGS_USE_VM_BIND (1u << 0) | |
| +#define I915_VM_CREATE_FLAGS_UNKNOWN (-(I915_VM_CREATE_FLAGS_USE_VM_BIND << 1)) | |
| __u32 flags; | |
| /** @vm_id: Id of the VM created or to be destroyed */ | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| by smtp.lore.kernel.org (Postfix) with ESMTPS id F2709C004D4 | |
| for <dri-devel@archiver.kernel.org>; Wed, 18 Jan 2023 07:17:08 +0000 (UTC) | |
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| 17 Jan 2023 23:16:15 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 20/23] drm/i915/vm_bind: Render VM_BIND documentation | |
| Date: Tue, 17 Jan 2023 23:16:06 -0800 | |
| Message-Id: <20230118071609.17572-21-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Update i915 documentation to include VM_BIND changes | |
| and render all VM_BIND related documentation. | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| Documentation/gpu/i915.rst | 78 ++++++++++++++++++++++++++++---------- | |
| 1 file changed, 59 insertions(+), 19 deletions(-) | |
| diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst | |
| index 60ea21734902..01429a8f0d6c 100644 | |
| --- a/Documentation/gpu/i915.rst | |
| +++ b/Documentation/gpu/i915.rst | |
| @@ -283,15 +283,18 @@ An Intel GPU has multiple engines. There are several engine types. | |
| The Intel GPU family is a family of integrated GPU's using Unified | |
| Memory Access. For having the GPU "do work", user space will feed the | |
| -GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` | |
| -or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will | |
| -instruct the GPU to perform work (for example rendering) and that work | |
| -needs memory from which to read and memory to which to write. All memory | |
| -is encapsulated within GEM buffer objects (usually created with the ioctl | |
| -`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU | |
| -to create will also list all GEM buffer objects that the batchbuffer reads | |
| -and/or writes. For implementation details of memory management see | |
| -`GEM BO Management Implementation Details`_. | |
| +GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`, | |
| +`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR` or `DRM_IOCTL_I915_GEM_EXECBUFFER3`. | |
| +Most such batchbuffers will instruct the GPU to perform work (for example | |
| +rendering) and that work needs memory from which to read and memory to | |
| +which to write. All memory is encapsulated within GEM buffer objects | |
| +(usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). In vm_bind mode | |
| +(see `VM_BIND mode`_), the batch buffer and all the GEM buffer objects that | |
| +it reads and/or writes should be bound with vm_bind ioctl before submitting | |
| +the batch buffer to GPU. In legacy (non-VM_BIND) mode, an ioctl providing a | |
| +batchbuffer for the GPU to create will also list all GEM buffer objects that | |
| +the batchbuffer reads and/or writes. For implementation details of memory | |
| +management see `GEM BO Management Implementation Details`_. | |
| The i915 driver allows user space to create a context via the ioctl | |
| `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit | |
| @@ -309,8 +312,9 @@ In addition to the ordering guarantees, the kernel will restore GPU | |
| state via HW context when commands are issued to a context, this saves | |
| user space the need to restore (most of atleast) the GPU state at the | |
| start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer | |
| -work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) | |
| -to identify what context to use with the command. | |
| +work can pass that ID (drm_i915_gem_execbuffer3::ctx_id, or in the lower | |
| +bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use | |
| +with the command. | |
| The GPU has its own memory management and address space. The kernel | |
| driver maintains the memory translation table for the GPU. For older | |
| @@ -318,14 +322,14 @@ GPUs (i.e. those before Gen8), there is a single global such translation | |
| table, a global Graphics Translation Table (GTT). For newer generation | |
| GPUs each context has its own translation table, called Per-Process | |
| Graphics Translation Table (PPGTT). Of important note, is that although | |
| -PPGTT is named per-process it is actually per context. When user space | |
| -submits a batchbuffer, the kernel walks the list of GEM buffer objects | |
| -used by the batchbuffer and guarantees that not only is the memory of | |
| -each such GEM buffer object resident but it is also present in the | |
| -(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, | |
| -then it is given an address. Two consequences of this are: the kernel | |
| -needs to edit the batchbuffer submitted to write the correct value of | |
| -the GPU address when a GEM BO is assigned a GPU address and the kernel | |
| +PPGTT is named per-process it is actually per context. In legacy | |
| +(non-vm_bind) mode, when user space submits a batchbuffer, the kernel walks | |
| +the list of GEM buffer objects used by the batchbuffer and guarantees that | |
| +not only is the memory of each such GEM buffer object resident but it is | |
| +also present in the (PP)GTT. If the GEM buffer object is not yet placed in | |
| +the (PP)GTT, then it is given an address. Two consequences of this are: the | |
| +kernel needs to edit the batchbuffer submitted to write the correct value | |
| +of the GPU address when a GEM BO is assigned a GPU address and the kernel | |
| might evict a different GEM BO from the (PP)GTT to make address room | |
| for another GEM BO. Consequently, the ioctls submitting a batchbuffer | |
| for execution also include a list of all locations within buffers that | |
| @@ -407,6 +411,15 @@ objects, which has the goal to make space in gpu virtual address spaces. | |
| .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | |
| :internal: | |
| +VM_BIND mode | |
| +------------ | |
| + | |
| +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| + :doc: VM_BIND/UNBIND ioctls | |
| + | |
| +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| + :internal: | |
| + | |
| Batchbuffer Parsing | |
| ------------------- | |
| @@ -419,11 +432,38 @@ Batchbuffer Parsing | |
| User Batchbuffer Execution | |
| -------------------------- | |
| +Client state | |
| +~~~~~~~~~~~~ | |
| + | |
| .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h | |
| +User command execution | |
| +~~~~~~~~~~~~~~~~~~~~~~ | |
| + | |
| .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | |
| :doc: User command execution | |
| +User command execution in vm_bind mode | |
| +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| + | |
| +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| + :doc: User command execution in vm_bind mode | |
| + | |
| +Common execbuff utilities | |
| +~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| + | |
| +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h | |
| + :internal: | |
| + | |
| +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c | |
| + :internal: | |
| + | |
| +Execbuf3 ioctl path | |
| +~~~~~~~~~~~~~~~~~~~ | |
| + | |
| +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c | |
| + :internal: | |
| + | |
| Scheduling | |
| ---------- | |
| .. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
| From mboxrd@z Thu Jan 1 00:00:00 1970 | |
| Return-Path: <dri-devel-bounces@lists.freedesktop.org> | |
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| 17 Jan 2023 23:16:16 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 21/23] drm/i915/vm_bind: Async vm_unbind support | |
| Date: Tue, 17 Jan 2023 23:16:07 -0800 | |
| Message-Id: <20230118071609.17572-22-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Asynchronously unbind the vma upon vm_unbind call. | |
| Fall back to synchronous unbind if backend doesn't support | |
| async unbind or if async unbind fails. | |
| No need for vm_unbind out fence support as i915 will internally | |
| handle all sequencing and user need not try to sequence any | |
| operation with the unbind completion. | |
| v2: use i915_vma_destroy_async in vm_unbind ioctl | |
| v3: Add force_unbind function variants | |
| Reviewed-by: Matthew Auld <matthew.auld@intel.com> | |
| Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 2 +- | |
| drivers/gpu/drm/i915/i915_vma.c | 49 ++++++++++++++++++- | |
| drivers/gpu/drm/i915/i915_vma.h | 1 + | |
| include/uapi/drm/i915_drm.h | 3 +- | |
| 4 files changed, 51 insertions(+), 4 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| index 1cc0b8a4e0e7..78e7c0642c5f 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| @@ -210,7 +210,7 @@ static int i915_gem_vm_unbind_vma(struct i915_address_space *vm, | |
| */ | |
| obj = vma->obj; | |
| i915_gem_object_lock(obj, NULL); | |
| - i915_vma_destroy(vma); | |
| + i915_vma_destroy_async(vma); | |
| i915_gem_object_unlock(obj); | |
| i915_gem_object_put(obj); | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 59462812ef4e..5b9ae5ebf55c 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -44,6 +44,8 @@ | |
| #include "i915_vma.h" | |
| #include "i915_vma_resource.h" | |
| +static struct dma_fence *__i915_vma_unbind_async(struct i915_vma *vma); | |
| + | |
| static inline void assert_vma_held_evict(const struct i915_vma *vma) | |
| { | |
| /* | |
| @@ -1749,7 +1751,7 @@ void i915_vma_reopen(struct i915_vma *vma) | |
| spin_unlock_irq(>->closed_lock); | |
| } | |
| -static void force_unbind(struct i915_vma *vma) | |
| +static void __force_unbind(struct i915_vma *vma, bool async) | |
| { | |
| if (!drm_mm_node_allocated(&vma->node)) | |
| return; | |
| @@ -1763,10 +1765,26 @@ static void force_unbind(struct i915_vma *vma) | |
| i915_vma_set_purged(vma); | |
| atomic_and(~I915_VMA_PIN_MASK, &vma->flags); | |
| - WARN_ON(__i915_vma_unbind(vma)); | |
| + if (async) { | |
| + struct dma_fence *fence; | |
| + | |
| + fence = __i915_vma_unbind_async(vma); | |
| + if (IS_ERR_OR_NULL(fence)) { | |
| + async = false; | |
| + } else { | |
| + dma_resv_add_fence(vma->obj->base.resv, fence, | |
| + DMA_RESV_USAGE_READ); | |
| + dma_fence_put(fence); | |
| + } | |
| + } | |
| + | |
| + if (!async) | |
| + WARN_ON(__i915_vma_unbind(vma)); | |
| GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); | |
| } | |
| +#define force_unbind(vma) __force_unbind((vma), false) | |
| + | |
| static void release_references(struct i915_vma *vma, struct intel_gt *gt, | |
| bool vm_ddestroy) | |
| { | |
| @@ -1845,6 +1863,33 @@ void i915_vma_destroy(struct i915_vma *vma) | |
| release_references(vma, gt, vm_ddestroy); | |
| } | |
| +void i915_vma_destroy_async(struct i915_vma *vma) | |
| +{ | |
| + bool vm_ddestroy, async = vma->obj->mm.rsgt; | |
| + struct intel_gt *gt; | |
| + | |
| + if (dma_resv_reserve_fences(vma->obj->base.resv, 1)) | |
| + async = false; | |
| + | |
| + mutex_lock(&vma->vm->mutex); | |
| + /* | |
| + * Ensure any asynchronous binding is complete while using | |
| + * async unbind as we will be releasing the vma here. | |
| + */ | |
| + if (async && i915_active_wait(&vma->active)) | |
| + async = false; | |
| + | |
| + __force_unbind(vma, async); | |
| + list_del_init(&vma->vm_link); | |
| + vm_ddestroy = vma->vm_ddestroy; | |
| + vma->vm_ddestroy = false; | |
| + | |
| + /* vma->vm may be freed when releasing vma->vm->mutex. */ | |
| + gt = vma->vm->gt; | |
| + mutex_unlock(&vma->vm->mutex); | |
| + release_references(vma, gt, vm_ddestroy); | |
| +} | |
| + | |
| void i915_vma_parked(struct intel_gt *gt) | |
| { | |
| struct i915_vma *vma, *next; | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h | |
| index d6c05227fb04..8033f5c96efc 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma.h | |
| @@ -319,6 +319,7 @@ void i915_vma_reopen(struct i915_vma *vma); | |
| void i915_vma_destroy_locked(struct i915_vma *vma); | |
| void i915_vma_destroy(struct i915_vma *vma); | |
| +void i915_vma_destroy_async(struct i915_vma *vma); | |
| #define assert_vma_held(vma) dma_resv_assert_held((vma)->obj->base.resv) | |
| diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h | |
| index 3f27001a2c8d..b9167f950327 100644 | |
| --- a/include/uapi/drm/i915_drm.h | |
| +++ b/include/uapi/drm/i915_drm.h | |
| @@ -3993,7 +3993,8 @@ struct drm_i915_gem_vm_bind { | |
| * any error. | |
| * | |
| * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently | |
| - * are not ordered. | |
| + * are not ordered. Furthermore, parts of the VM_UNBIND operation can be done | |
| + * asynchronously. | |
| */ | |
| struct drm_i915_gem_vm_unbind { | |
| /** @vm_id: VM (address space) id to bind */ | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
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| 17 Jan 2023 23:16:16 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 22/23] drm/i915/vm_bind: Properly build persistent map sg | |
| table | |
| Date: Tue, 17 Jan 2023 23:16:08 -0800 | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Properly build the sg table for persistent mapping which can | |
| be partial map of the underlying object. Ensure the sg pages | |
| are properly set for page backed regions. The dump capture | |
| support requires this for page backed regions. | |
| v2: Remove redundant sg_mark_end() call | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| drivers/gpu/drm/i915/i915_vma.c | 113 +++++++++++++++++++++++++++++++- | |
| 1 file changed, 112 insertions(+), 1 deletion(-) | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 5b9ae5ebf55c..2f0994f0ed42 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -1331,6 +1331,113 @@ intel_partial_pages(const struct i915_gtt_view *view, | |
| return ERR_PTR(ret); | |
| } | |
| +static unsigned int | |
| +intel_copy_dma_sg(struct sg_table *src_st, struct sg_table *dst_st, | |
| + u64 offset, u64 length, bool dry_run) | |
| +{ | |
| + struct scatterlist *dst_sg, *src_sg; | |
| + unsigned int i, len, nents = 0; | |
| + | |
| + dst_sg = dst_st->sgl; | |
| + for_each_sgtable_dma_sg(src_st, src_sg, i) { | |
| + if (sg_dma_len(src_sg) <= offset) { | |
| + offset -= sg_dma_len(src_sg); | |
| + continue; | |
| + } | |
| + | |
| + nents++; | |
| + len = min(sg_dma_len(src_sg) - offset, length); | |
| + if (!dry_run) { | |
| + sg_dma_address(dst_sg) = sg_dma_address(src_sg) + offset; | |
| + sg_dma_len(dst_sg) = len; | |
| + dst_sg = sg_next(dst_sg); | |
| + } | |
| + | |
| + length -= len; | |
| + offset = 0; | |
| + if (!length) | |
| + break; | |
| + } | |
| + WARN_ON_ONCE(length); | |
| + | |
| + return nents; | |
| +} | |
| + | |
| +static unsigned int | |
| +intel_copy_sg(struct sg_table *src_st, struct sg_table *dst_st, | |
| + u64 offset, u64 length, bool dry_run) | |
| +{ | |
| + struct scatterlist *dst_sg, *src_sg; | |
| + unsigned int i, len, nents = 0; | |
| + | |
| + dst_sg = dst_st->sgl; | |
| + for_each_sgtable_sg(src_st, src_sg, i) { | |
| + if (src_sg->length <= offset) { | |
| + offset -= src_sg->length; | |
| + continue; | |
| + } | |
| + | |
| + nents++; | |
| + len = min(src_sg->length - offset, length); | |
| + if (!dry_run) { | |
| + unsigned long pfn; | |
| + | |
| + pfn = page_to_pfn(sg_page(src_sg)) + offset / PAGE_SIZE; | |
| + sg_set_page(dst_sg, pfn_to_page(pfn), len, 0); | |
| + dst_sg = sg_next(dst_sg); | |
| + } | |
| + | |
| + length -= len; | |
| + offset = 0; | |
| + if (!length) | |
| + break; | |
| + } | |
| + WARN_ON_ONCE(length); | |
| + | |
| + return nents; | |
| +} | |
| + | |
| +static noinline struct sg_table * | |
| +intel_persistent_partial_pages(const struct i915_gtt_view *view, | |
| + struct drm_i915_gem_object *obj) | |
| +{ | |
| + u64 offset = view->partial.offset << PAGE_SHIFT; | |
| + struct sg_table *st, *obj_st = obj->mm.pages; | |
| + u64 length = view->partial.size << PAGE_SHIFT; | |
| + unsigned int nents; | |
| + int ret = -ENOMEM; | |
| + | |
| + st = kmalloc(sizeof(*st), GFP_KERNEL); | |
| + if (!st) | |
| + goto err_st_alloc; | |
| + | |
| + /* Get required sg_table size */ | |
| + nents = intel_copy_dma_sg(obj_st, st, offset, length, true); | |
| + if (i915_gem_object_has_struct_page(obj)) { | |
| + unsigned int pg_nents; | |
| + | |
| + pg_nents = intel_copy_sg(obj_st, st, offset, length, true); | |
| + if (nents < pg_nents) | |
| + nents = pg_nents; | |
| + } | |
| + | |
| + ret = sg_alloc_table(st, nents, GFP_KERNEL); | |
| + if (ret) | |
| + goto err_sg_alloc; | |
| + | |
| + /* Build sg_table for specified <offset, length> section */ | |
| + intel_copy_dma_sg(obj_st, st, offset, length, false); | |
| + if (i915_gem_object_has_struct_page(obj)) | |
| + intel_copy_sg(obj_st, st, offset, length, false); | |
| + | |
| + return st; | |
| + | |
| +err_sg_alloc: | |
| + kfree(st); | |
| +err_st_alloc: | |
| + return ERR_PTR(ret); | |
| +} | |
| + | |
| static int | |
| __i915_vma_get_pages(struct i915_vma *vma) | |
| { | |
| @@ -1363,7 +1470,11 @@ __i915_vma_get_pages(struct i915_vma *vma) | |
| break; | |
| case I915_GTT_VIEW_PARTIAL: | |
| - pages = intel_partial_pages(&vma->gtt_view, vma->obj); | |
| + if (i915_vma_is_persistent(vma)) | |
| + pages = intel_persistent_partial_pages(&vma->gtt_view, | |
| + vma->obj); | |
| + else | |
| + pages = intel_partial_pages(&vma->gtt_view, vma->obj); | |
| break; | |
| } | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
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| by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; | |
| 17 Jan 2023 23:16:16 -0800 | |
| From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| To: intel-gfx@lists.freedesktop.org, | |
| dri-devel@lists.freedesktop.org | |
| Subject: [PATCH v10 23/23] drm/i915/vm_bind: Support capture of persistent | |
| mappings | |
| Date: Tue, 17 Jan 2023 23:16:09 -0800 | |
| Message-Id: <20230118071609.17572-24-niranjana.vishwanathapura@intel.com> | |
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| Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, | |
| jani.nikula@intel.com, lionel.g.landwerlin@intel.com, | |
| thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, | |
| andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com | |
| Errors-To: dri-devel-bounces@lists.freedesktop.org | |
| Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org> | |
| Support dump capture of persistent mappings upon user request. | |
| Capture of a mapping is requested with the VM_BIND ioctl and | |
| processed during the GPU error handling. They are synchronously | |
| unbound during eviction so that no additional vma resource | |
| reference taking is required in the submission path. Thus, a | |
| list of persistent vmas requiring capture is maintained instead | |
| of a list of vma resources. | |
| v2: enable with CONFIG_DRM_I915_CAPTURE_ERROR, remove gfp | |
| overwrite, add kernel-doc and expand commit message | |
| v3: Ensure vma->resource is valid during capture | |
| Signed-off-by: Brian Welty <brian.welty@intel.com> | |
| Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | |
| --- | |
| .../drm/i915/gem/i915_gem_vm_bind_object.c | 13 +++++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.c | 5 ++ | |
| drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +++ | |
| drivers/gpu/drm/i915/i915_gem.c | 14 ++++- | |
| drivers/gpu/drm/i915/i915_gpu_error.c | 48 ++++++++++++++++++- | |
| drivers/gpu/drm/i915/i915_vma.c | 4 ++ | |
| drivers/gpu/drm/i915/i915_vma_types.h | 4 ++ | |
| include/uapi/drm/i915_drm.h | 9 +++- | |
| 8 files changed, 104 insertions(+), 4 deletions(-) | |
| diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| index 78e7c0642c5f..562a67a988f2 100644 | |
| --- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c | |
| @@ -88,6 +88,12 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj) | |
| { | |
| lockdep_assert_held(&vma->vm->vm_bind_lock); | |
| +#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
| + mutex_lock(&vma->vm->vm_capture_lock); | |
| + if (!list_empty(&vma->vm_capture_link)) | |
| + list_del_init(&vma->vm_capture_link); | |
| + mutex_unlock(&vma->vm->vm_capture_lock); | |
| +#endif | |
| spin_lock(&vma->vm->vm_rebind_lock); | |
| if (!list_empty(&vma->vm_rebind_link)) | |
| list_del_init(&vma->vm_rebind_link); | |
| @@ -357,6 +363,13 @@ static int i915_gem_vm_bind_obj(struct i915_address_space *vm, | |
| continue; | |
| } | |
| +#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
| + if (va->flags & I915_GEM_VM_BIND_CAPTURE) { | |
| + mutex_lock(&vm->vm_capture_lock); | |
| + list_add_tail(&vma->vm_capture_link, &vm->vm_capture_list); | |
| + mutex_unlock(&vm->vm_capture_lock); | |
| + } | |
| +#endif | |
| list_add_tail(&vma->vm_bind_link, &vm->vm_bound_list); | |
| i915_vm_bind_it_insert(vma, &vm->va); | |
| if (!obj->priv_root) | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| index 2e4c9fabf3b8..103ca55222be 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c | |
| @@ -298,6 +298,11 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) | |
| spin_lock_init(&vm->vm_rebind_lock); | |
| spin_lock_init(&vm->userptr_invalidated_lock); | |
| INIT_LIST_HEAD(&vm->userptr_invalidated_list); | |
| + | |
| +#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
| + INIT_LIST_HEAD(&vm->vm_capture_list); | |
| + mutex_init(&vm->vm_capture_lock); | |
| +#endif | |
| } | |
| void *__px_vaddr(struct drm_i915_gem_object *p) | |
| diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| index 620b4e020a9f..7f69e1d4fb5e 100644 | |
| --- a/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h | |
| @@ -281,6 +281,13 @@ struct i915_address_space { | |
| /** @root_obj: root object for dma-resv sharing by private objects */ | |
| struct drm_i915_gem_object *root_obj; | |
| +#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
| + /* @vm_capture_list: list of vm captures */ | |
| + struct list_head vm_capture_list; | |
| + /* @vm_capture_lock: protects vm_capture_list */ | |
| + struct mutex vm_capture_lock; | |
| +#endif | |
| + | |
| /* Global GTT */ | |
| bool is_ggtt:1; | |
| diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c | |
| index 969581e7106f..d97822f203fc 100644 | |
| --- a/drivers/gpu/drm/i915/i915_gem.c | |
| +++ b/drivers/gpu/drm/i915/i915_gem.c | |
| @@ -143,6 +143,8 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj, | |
| while (!ret && (vma = list_first_entry_or_null(&obj->vma.list, | |
| struct i915_vma, | |
| obj_link))) { | |
| + bool sync_unbind = true; | |
| + | |
| list_move_tail(&vma->obj_link, &still_in_list); | |
| if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK)) | |
| continue; | |
| @@ -171,8 +173,18 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj, | |
| * and destroy the vma from under us. | |
| */ | |
| + /* | |
| + * Synchronously unbind persistent mappings with capture | |
| + * request so that vma->resource is valid in the error capture | |
| + * path without needing extra reference taking in execbuf path. | |
| + */ | |
| + if (!mutex_lock_interruptible(&vma->vm->vm_capture_lock)) { | |
| + sync_unbind = !list_empty(&vma->vm_capture_link); | |
| + mutex_unlock(&vma->vm->vm_capture_lock); | |
| + } | |
| + | |
| ret = -EBUSY; | |
| - if (flags & I915_GEM_OBJECT_UNBIND_ASYNC) { | |
| + if (!sync_unbind && (flags & I915_GEM_OBJECT_UNBIND_ASYNC)) { | |
| assert_object_held(vma->obj); | |
| ret = i915_vma_unbind_async(vma, vm_trylock); | |
| } | |
| diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c | |
| index 9d5d5a397b64..5ccd1eaea2a5 100644 | |
| --- a/drivers/gpu/drm/i915/i915_gpu_error.c | |
| +++ b/drivers/gpu/drm/i915/i915_gpu_error.c | |
| @@ -1463,6 +1463,49 @@ capture_vma(struct intel_engine_capture_vma *next, | |
| return next; | |
| } | |
| +static struct intel_engine_capture_vma * | |
| +capture_user_vm(struct intel_engine_capture_vma *capture, | |
| + struct i915_address_space *vm, gfp_t gfp) | |
| +{ | |
| + struct list_head vm_capture_list; | |
| + struct i915_vma *vma, *vn; | |
| + int err; | |
| + | |
| + INIT_LIST_HEAD(&vm_capture_list); | |
| + | |
| + err = mutex_lock_interruptible(&vm->vm_capture_lock); | |
| + if (err) | |
| + return capture; | |
| + | |
| + /* vma->resource should be checked with vm->mutex held */ | |
| + err = mutex_lock_interruptible(&vm->mutex); | |
| + if (err) | |
| + goto skip_user_vm_capture; | |
| + | |
| + list_for_each_entry_safe(vma, vn, &vm->vm_capture_list, | |
| + vm_capture_link) { | |
| + if (drm_WARN_ONCE(&vm->i915->drm, !vma->resource, | |
| + "vma->resource expected!\n")) | |
| + continue; | |
| + | |
| + i915_vma_resource_get(vma->resource); | |
| + list_move_tail(&vma->vm_capture_link, &vm_capture_list); | |
| + } | |
| + mutex_unlock(&vm->mutex); | |
| + | |
| + list_for_each_entry(vma, &vm_capture_list, vm_capture_link) { | |
| + capture = capture_vma_snapshot(capture, vma->resource, | |
| + gfp, "user"); | |
| + i915_vma_resource_put(vma->resource); | |
| + } | |
| + list_splice_tail(&vm_capture_list, &vm->vm_capture_list); | |
| + | |
| +skip_user_vm_capture: | |
| + mutex_unlock(&vm->vm_capture_lock); | |
| + | |
| + return capture; | |
| +} | |
| + | |
| static struct intel_engine_capture_vma * | |
| capture_user(struct intel_engine_capture_vma *capture, | |
| const struct i915_request *rq, | |
| @@ -1470,6 +1513,8 @@ capture_user(struct intel_engine_capture_vma *capture, | |
| { | |
| struct i915_capture_list *c; | |
| + capture = capture_user_vm(capture, rq->context->vm, gfp); | |
| + | |
| for (c = rq->capture_list; c; c = c->next) | |
| capture = capture_vma_snapshot(capture, c->vma_res, gfp, | |
| "user"); | |
| @@ -1537,11 +1582,10 @@ intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_ | |
| static struct intel_engine_capture_vma * | |
| engine_coredump_add_context(struct intel_engine_coredump *ee, | |
| + struct intel_engine_capture_vma *vma, | |
| struct intel_context *ce, | |
| gfp_t gfp) | |
| { | |
| - struct intel_engine_capture_vma *vma = NULL; | |
| - | |
| ee->simulated |= record_context(&ee->context, ce); | |
| if (ee->simulated) | |
| return NULL; | |
| @@ -1562,9 +1606,14 @@ intel_engine_coredump_add_request(struct intel_engine_coredump *ee, | |
| struct i915_request *rq, | |
| gfp_t gfp) | |
| { | |
| - struct intel_engine_capture_vma *vma; | |
| + struct intel_engine_capture_vma *vma = NULL; | |
| - vma = engine_coredump_add_context(ee, rq->context, gfp); | |
| + /* | |
| + * Ensure capture_user_vm which takes vm->mutex gets called first | |
| + * as snapshoting the first vma starts dma fence critical section. | |
| + */ | |
| + vma = capture_user(vma, rq, gfp); | |
| + vma = engine_coredump_add_context(ee, vma, rq->context, gfp); | |
| if (!vma) | |
| return NULL; | |
| @@ -1574,7 +1623,6 @@ intel_engine_coredump_add_request(struct intel_engine_coredump *ee, | |
| * by userspace. | |
| */ | |
| vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); | |
| - vma = capture_user(vma, rq, gfp); | |
| ee->rq_head = rq->head; | |
| ee->rq_post = rq->postfix; | |
| @@ -1635,7 +1683,7 @@ capture_engine(struct intel_engine_cs *engine, | |
| capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); | |
| i915_request_put(rq); | |
| } else if (ce) { | |
| - capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL); | |
| + capture = engine_coredump_add_context(ee, NULL, ce, ATOMIC_MAYFAIL); | |
| } | |
| if (capture) { | |
| diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c | |
| index 2f0994f0ed42..b47715fa773f 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma.c | |
| +++ b/drivers/gpu/drm/i915/i915_vma.c | |
| @@ -248,6 +248,10 @@ vma_create(struct drm_i915_gem_object *obj, | |
| INIT_LIST_HEAD(&vma->non_priv_vm_bind_link); | |
| INIT_LIST_HEAD(&vma->vm_rebind_link); | |
| INIT_LIST_HEAD(&vma->userptr_invalidated_link); | |
| + | |
| +#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
| + INIT_LIST_HEAD(&vma->vm_capture_link); | |
| +#endif | |
| return vma; | |
| err_unlock: | |
| diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h | |
| index 89f9854a6f69..c4fd61d51ce6 100644 | |
| --- a/drivers/gpu/drm/i915/i915_vma_types.h | |
| +++ b/drivers/gpu/drm/i915/i915_vma_types.h | |
| @@ -310,6 +310,10 @@ struct i915_vma { | |
| struct list_head vm_rebind_link; /* Link in vm_rebind_list */ | |
| /** @userptr_invalidated_link: link to the vm->userptr_invalidated_list */ | |
| struct list_head userptr_invalidated_link; | |
| +#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
| + /* @vm_capture_link: link to the captureable VMA list */ | |
| + struct list_head vm_capture_link; | |
| +#endif | |
| /** Timeline fence for vm_bind completion notification */ | |
| struct { | |
| diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h | |
| index b9167f950327..5fde6020e339 100644 | |
| --- a/include/uapi/drm/i915_drm.h | |
| +++ b/include/uapi/drm/i915_drm.h | |
| @@ -3925,12 +3925,17 @@ struct drm_i915_gem_vm_bind { | |
| __u64 length; | |
| /** | |
| - * @flags: Currently reserved, MBZ. | |
| + * @flags: Supported flags are: | |
| + * | |
| + * I915_GEM_VM_BIND_CAPTURE: | |
| + * Capture this mapping in the dump upon GPU error. | |
| + * CONFIG_DRM_I915_CAPTURE_ERROR should be enabled for valid capture. | |
| * | |
| * Note that @fence carries its own flags. | |
| */ | |
| __u64 flags; | |
| -#define __I915_GEM_VM_BIND_UNKNOWN_FLAGS (~0ull) | |
| +#define I915_GEM_VM_BIND_CAPTURE (1ull << 0) | |
| +#define __I915_GEM_VM_BIND_UNKNOWN_FLAGS (-(I915_GEM_VM_BIND_CAPTURE << 1)) | |
| /** @rsvd: Reserved, MBZ */ | |
| __u64 rsvd[2]; | |
| -- | |
| 2.21.0.rc0.32.g243a4c7e27 | |
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