SpiIf.v

module SpiIf(clk,cs,shift,ncs,sck,sdi,sdo,q);
	input clk,cs,shift,sdo;
	output ncs,sck,sdi;
	output [9:0] q;
	reg [9:0] sreg;
	
	assign ncs=~cs;
	assign sdi=1'b1;
	assign sck=cs & clk;
	
	always@(posedge clk) begin
		if((cs==1'b1) && (shift==1'b1))
			sreg={sreg[8:0],sdo};
	end
	assign q=sreg;
endmodule