Kyle McCornack kpmcc

## tictactoe.py
#!/usr/bin/env python3
#
import argparse

class Game(object):

    def __init__(self):
        self.board = [0 for _ in range(9)]
        self.value_dict = {1: "X", 2: "O"}
        self.turn_taker = 1

## index.html
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN">

<html>
<head>
  <meta name="viewport" content=
  "width=device-width, initial-scale=1.0">
  <style type="text/css">
  canvas {
        border: 1px solid #d3d3d3;
        background-color: black;

## rcplacebot.py
#!/usr/bin/env python3

# Using this currently requires a file called 'token.txt'
# with one's Personal Access Token to be able to interact
# with the canvas.

import requests
import os
import time

## FPGA Resources.md

      
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    FPGA Resources

HDLs

These are the languages in which one writes code to describe hardware. I say this instead of calling them programming languages to try and emphasize the distinction between describing hardware and writing code that executes on hardware.
Oftentimes these languages have functionality both for describing hardware, and for simulating or verifying designs. At early stages of learning it is important to understand the intended uses for particular language features. It can be easy to do things that would make sense in software, and are viable for verification, but that do not translate to hardware.
Standard HDLs


## mastermind.go
package main

import (
	"bufio"
	"errors"
	"fmt"
	"math/rand"
	"os"
	"strings"
)

## tree.c

// preprocessor macro - basically copies tree.h and puts
// the contents where the include goes
#include <stdio.h>
#include <stdlib.h>

#include "tree.h"


int print_tree_hello() {

## envelopes.scd
s.boot;

x = {(PinkNoise.ar * 0.3)!2}.play

x.free;

( // These synths pile up and stay active (persistent lifetimes)
x = {
	var sig, env;
	env = Line.kr(1, 0, 1);

## Makefile
# Makefile

# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

VERILOG_SOURCES += $(PWD)/../rtl/complete_day_04.v

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL files
TOPLEVEL = day_04
	#!/usr/bin/env python3
	#
	import argparse

	class Game(object):

	def __init__(self):
	self.board = [0 for _ in range(9)]
	self.value_dict = {1: "X", 2: "O"}
	self.turn_taker = 1
	<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN">

	<html>
	<head>
	<meta name="viewport" content=
	"width=device-width, initial-scale=1.0">
	<style type="text/css">
	canvas {
	border: 1px solid #d3d3d3;
	background-color: black;
	#!/usr/bin/env python3

	# Using this currently requires a file called 'token.txt'
	# with one's Personal Access Token to be able to interact
	# with the canvas.

	import requests
	import os
	import time
	package main

	import (
	"bufio"
	"errors"
	"fmt"
	"math/rand"
	"os"
	"strings"
	)

	// preprocessor macro - basically copies tree.h and puts
	// the contents where the include goes
	#include <stdio.h>
	#include <stdlib.h>

	#include "tree.h"


	int print_tree_hello() {
	s.boot;

	x = {(PinkNoise.ar * 0.3)!2}.play

	x.free;

	( // These synths pile up and stay active (persistent lifetimes)
	x = {
	var sig, env;
	env = Line.kr(1, 0, 1);
	# Makefile

	# defaults
	SIM ?= icarus
	TOPLEVEL_LANG ?= verilog

	VERILOG_SOURCES += $(PWD)/../rtl/complete_day_04.v

	# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL files
	TOPLEVEL = day_04