CS258 Exam 3

CS258_Exam3.py

import numpy as np
# Assume : An instruction generate 16 bytes of data traffic at the memory bus
#          These instrucions are 30% of the total instructions
#          The memory bus is 64 Byte wide
#          The memory bus is 6GHz
#          Miss rate of L1 : 15%
#          Miss rate of L2 : 5%
#          Access time of L1 : 2 cycle
#          Access time of L2 : 20 cycle
#          Access time of memory : 120 cycle
#          Memory stall 20% of the time
#          Assume Processor clock is 2GHz
#          8 Stage pipeline

#parameters
miss_rate_L1 = 0.15
miss_rate_L2 = 0.05
data_access_instr = 0.3
memory_stall = 0.2
# For a single processor and it's memory bank
N = 100 # number of instructions
num_data_access_instr = data_access_instr * N # number of data access instructions
instr_caused_memory_stall = memory_stall * data_access_instr # number of instructions that caused memory stall

requests_to_memory = miss_rate_L1 * miss_rate_L2 * data_access_instr # number of requests to memory

# 80 % of the requests can be served at each cycle
# 80 requests can be served in 5*80 = 400 ns
# 20 - requests_to_memory can be served at 2 + 0.15*(20 - requests_to_memory)= 

total_time_to_process_request = 2.344*100*0.5 # for 100 instructions

total_bytes_requested = 16 * requests_to_memory
# print("total time to process request(ns) : {}".format(total_time_to_process_request))
# print("total bytes requested : {}".format(total_bytes_requested))
# print("Bandwidth used : {} GB/s".format(total_bytes_requested/total_time_to_process_request))

memory_bus_clock = 6 #GHz
memory_bus_width = 64 #Byte
memory_bus_bandwidth = memory_bus_clock * memory_bus_width # GB/s

#print("Max number of chips to utilize the 80% memory bus : {}".format((0.8*memory_bus_bandwidth)/(total_bytes_requested/total_time_to_process_request)))

# accounting queuing delay and requests to other banks
L2_access_time = 20 # cycles
interconnect_bus_delay = 1 # cycle
additional_delay = L2_access_time * interconnect_bus_delay # cycles
#print("additional delay : {}".format(additional_delay))

# Worst case scenario
# FIFO is full 4*additional_delay

total_time_to_process_request = (2 + (0.15*20 + 0.05*(120+4*additional_delay))*0.5)*100 # for 100 instructions
#print("[WORST_CASE]total time to process request(ns) : {}".format(total_time_to_process_request))

# Best case scenario
# FIFO is empty 0*additional_delay
total_time_to_process_request = (2 + (0.15*20 + 0.05*(120+0*additional_delay))*0.5)*100 # for 100 instructions
#print("[BEST_CASE]total time to process request(ns) : {}".format(total_time_to_process_request))

# for uniform distribution of fifo size

fifo_samples = np.random.uniform(0,4,1000)

def fifo_delay(fifo_size):
    return 2 + (0.15*20 + 0.05*(120+fifo_size*additional_delay))*0.5

fifo_delay_samples = np.array([fifo_delay(fifo_size) for fifo_size in fifo_samples])

num_of_chips_req_to_utilize_memory_bus = (0.8*memory_bus_bandwidth)/(total_bytes_requested/fifo_delay_samples)

avg_num_of_chips_req_to_utilize_memory_bus = np.mean(num_of_chips_req_to_utilize_memory_bus)

print("avg_num_of_chips_req_to_utilize_memory_bus : {}".format(avg_num_of_chips_req_to_utilize_memory_bus))