TCL Script for DC Synthesis for AES using minimum sized cells

dc_script_AES_minFeatureSizeCells.tcl

echo "\n---   INITIALIZATION   ---\n"

#cleanup
remove_design -all

######################################
# Set libraries
######################################

set DESIGN "aes_top"
set VERSION "v1.1.a.uniquify"
set RUNNAME "gates_dc_v1.1.a"

# set DESIGN_0 "masked_aes_pkg"
set DESIGN_1 "inverter"
set DESIGN_2 "gf2_mul"
set DESIGN_3 "square_scaler"
set DESIGN_4 "lin_map"
set DESIGN_5 "aes_sbox"
set DESIGN_6 "aes_ctrl_lsfr"
set DESIGN_7 "aes_ctrl_lsfr_23_cycles"
set DESIGN_8 "aes_key_regs"
set DESIGN_9 "aes_state_regs"
set DESIGN_10 "masked_mul"
set DESIGN_11 "mix_columns"
set DESIGN_12 "rcon"
set DESIGN_13 "real_dom_shared_mul_gf2"
set DESIGN_14 "real_dom_shared_mul_gf4"
set DESIGN_15 "shared_mul"
set DESIGN_16 "shared_mul_gf2"
set DESIGN_17 "shared_mul_gf4"

set ENTITIES [list "inverter.vhdl" "gf2_mul.vhdl" "square_scaler.vhdl" "lin_map.vhdl" "aes_sbox.vhdl" "aes_ctrl_lsfr.vhdl" "aes_ctrl_lsfr_23_cycles.vhdl" "aes_key_regs.vhdl" "aes_state_regs.vhdl" "masked_mul.vhdl" "mix_columns.vhdl" "rcon.vhdl" "real_dom_shared_mul_gf2.vhdl" "real_dom_shared_mul_gf4.vhdl" "shared_mul.vhdl" "shared_mul_gf2.vhdl" "shared_mul_gf4.vhdl" "aes_top.vhdl" ]

#Force HDL Compiler to preserve hierarch information, needed for SAIF generation
set power_preserve_rtl_hier_names true

######################################
# Analyze Verilog RTL files
######################################
echo "\n---   ANALYSIS   ---\n"

foreach {i} $ENTITIES {
analyze -format vhdl  ../rtl/$i
}


# ######################################
# Elaborate Design
 ######################################
 
#echo "\n---   ELABORATE DESIGN_0   ---\n"
#elaborate $DESIGN_0 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_1   ---\n"
elaborate $DESIGN_1 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_2   ---\n"
elaborate $DESIGN_2 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_3   ---\n"
elaborate $DESIGN_3 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_4   ---\n"
elaborate $DESIGN_4 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_5   ---\n"
elaborate $DESIGN_5 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_6   ---\n"
elaborate $DESIGN_6 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_7   ---\n"
elaborate $DESIGN_7 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_8   ---\n"
elaborate $DESIGN_8 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_9   ---\n"
elaborate $DESIGN_9 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_10   ---\n"
elaborate $DESIGN_10 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_11   ---\n"
elaborate $DESIGN_11 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_12   ---\n"
elaborate $DESIGN_12 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_13   ---\n"
elaborate $DESIGN_13 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_14   ---\n"
elaborate $DESIGN_14 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_15   ---\n"
elaborate $DESIGN_15 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_16   ---\n"
elaborate $DESIGN_16 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_17   ---\n"
elaborate $DESIGN_17 -architecture BEHAVIORAL -library WORK

echo "\n---   ELABORATE DESIGN_18   ---\n"
elaborate $DESIGN_18 -architecture BEHAVIORAL -library WORK

echo "\n--- COMPILING DESIGN	---\n"
compile -map_effort medium

echo "\n---   ELABORATE DESIGN   ---\n"
elaborate $DESIGN -architecture BEHAVIORAL -library WORK -parameter "PERFECTLY_INTERLEAVED=no,\ EIGHT_STAGED_SBOX=no \ N=0"

#set_dont_touch [get_cells U_DFF*] true
set_dont_touch [get_cells U*] true