Example initial block

example.vhd

entity piecewise_function is
    generic (
        NODE_MAP            :       NodeMapType;
        NODE_ID             :       string;
        NUM_SEGMENTS        :       natural;
        THRESHOLD_SIZE_RES  :       sfixed;
        BIAS_SIZE_RES       :       sfixed;
        GAIN_SIZE_RES       :       sfixed);
    port (
        clk                 : in    std_logic;
        rst                 : in    std_logic;
        en                  : in    std_logic;
        dataIn              : in    sfixed;
        validIn             : in    std_logic;
        dataOut             :   out sfixed;
        validOut            :   out std_logic;
        nodeIf              : inout NodeRecType);
end entity piecewise_function;

architecture rtl of piecewise_function is
    -- ...
begin
    -- ...
    
    initial
        constant COMP_ADDR  : std_logic_vector      := GetComponentAddress(NODE_MAP, NODE_ID);
        variable component  : ComponentType         := CreateComponent(NODE_ID, COMP_ADDR, "Piecewise tranfer function");
        variable reg_map    : SlaveSegmentType      := CreateSlaveSegment(component);
        variable reg        : RegisterType;
    begin
        assert THRESHOLD_SIZE_RES'length <= REG_SIZE report "THRESHOLD too large to fit in register";
        assert BIAS_SIZE_RES'length <= REG_SIZE report "THRESHOLD too large to fit in register";
        assert GAIN_SIZE_RES'length <= REG_SIZE report "THRESHOLD too large to fit in register";
        for i in 0 to NUM_SEGMENTS-1 loop
            reg := CreateRegister(reg_map, "THRESHOLD"&integer'image(i), 3*i+0, THRESHOLD_SIZE_RES'length-1, 0, "Piece "&integer'image(i)&" threshold value");
            RegisterAddMetadata(reg, "FIXED", SfixedFormatString(THRESHOLD_SIZE_RES));
            reg := CreateRegister(reg_map, "BIAS"&integer'image(i), 3*i+1, BIAS_SIZE_RES'length-1, 0, "Piece "&integer'image(i)&" bias value");
            RegisterAddMetadata(reg, "FIXED", SfixedFormatString(BIAS_SIZE_RES));
            reg := CreateRegister(reg_map, "GAIN"&integer'image(i), 3*i+2, GAIN_SIZE_RES'length-1, 0, "Piece "&integer'image(i)&" gain value");
            RegisterAddMetadata(reg, "FIXED", SfixedFormatString(GAIN_SIZE_RES));
        end loop;
    end initial;
end architecture rtl;