D:\kpathak\Core_Root_callee_Save\Core_Root\corerun.exe -p "System.Reflection.Metadata.MetadataUpdater.IsSupported=false" -p "System.Runtime.Serialization.EnableUnsafeBinaryFormatterSerialization=true" D:\kpathak\tests\caller-save\HardwareIntrinsics\HardwareIntrinsics_Arm_r\HardwareIntrinsics_Arm_r.dll Sve_GatherVector_Bases_double_ulong
09:01:49.183 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVector_Bases_double_ulong()
Supported ISAs:
AdvSimd: True
Aes: True
ArmBase: True
Crc32: True
Dp: True
Rdm: False
Sha1: True
Sha256: True
Sve: True
Beginning scenario: RunBasicScenario_UnsafeRead
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunBasicScenario_UnsafeRead failed:
firstOp: (0, 5E-324)
secondOp: (2337981206411, 2337981206811)
result: (0, 2.767806072932817E+254)
; Assembly listing for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong:RunBasicScenario_Load():this (MinOpts)
; Emitting BLENDED_CODE for generic ARM64 - Windows
; MinOpts code
; debuggable code
; fp based frame
; fully interruptible
; No PGO data
; Final local variable assignments
;
; V00 this [V00 ] ( 1, 1 ) ref -> [fp+0x108] do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong>
; V01 loc0 [V01 ] ( 1, 1 ) simd16 -> [fp+0xF0] HFA(simd16) do-not-enreg[S] must-init <System.Numerics.Vector`1[double]>
; V02 loc1 [V02 ] ( 1, 1 ) simd16 -> [fp+0xE0] HFA(simd16) do-not-enreg[S] must-init <System.Numerics.Vector`1[ulong]>
; V03 loc2 [V03 ] ( 1, 1 ) simd16 -> [fp+0xD0] HFA(simd16) do-not-enreg[S] must-init <System.Numerics.Vector`1[double]>
;# V04 OutArgs [V04 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V05 tmp1 [V05 ] ( 1, 1 ) simd16 -> [fp+0xC0] do-not-enreg[S] "impSpillStackEnsure"
; V06 tmp2 [V06 ] ( 1, 1 ) simd16 -> [fp+0xB0] do-not-enreg[S] "impSpillStackEnsure"
; V07 tmp3 [V07 ] ( 1, 1 ) simd16 -> [fp+0xA0] do-not-enreg[S] "impSpillStackEnsure"
; V08 tmp4 [V08 ] ( 1, 1 ) long -> [fp+0x98] do-not-enreg[] "impSpillStackEnsure"
; V09 tmp5 [V09 ] ( 1, 1 ) simd16 -> [fp+0x80] do-not-enreg[S] "impSpillStackEnsure"
; V10 tmp6 [V10 ] ( 1, 1 ) simd16 -> [fp+0x70] do-not-enreg[S] "impSpillStackEnsure"
; V11 tmp7 [V11 ] ( 1, 1 ) long -> [fp+0x68] do-not-enreg[] "impSpillStackEnsure"
; V12 tmp8 [V12 ] ( 1, 1 ) simd16 -> [fp+0x50] do-not-enreg[S] "impSpillStackEnsure"
; V13 tmp9 [V13 ] ( 1, 1 ) simd16 -> [fp+0x40] do-not-enreg[S] "impSpillStackEnsure"
; V14 tmp10 [V14 ] ( 1, 1 ) long -> [fp+0x38] do-not-enreg[] "impSpillStackEnsure"
; V15 tmp11 [V15 ] ( 1, 1 ) ref -> [fp+0x30] do-not-enreg[] must-init class-hnd exact "impSpillStackEnsure" <JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong>
; V16 tmp12 [V16 ] ( 1, 1 ) long -> [fp+0x28] do-not-enreg[] "impSpillStackEnsure"
; V17 tmp13 [V17 ] ( 1, 1 ) long -> [fp+0x20] do-not-enreg[] "impSpillStackEnsure"
; V18 tmp14 [V18 ] ( 1, 1 ) long -> [fp+0x18] do-not-enreg[] "impSpillStackEnsure"
;
; Lcl frame size = 256
G_M53560_IG01: ;; offset=0x0000
stp fp, lr, [sp, #-0x110]!
mov fp, sp
movi v16.16b, #0
add x9, fp, #16
mov x10, #144
stp q16, q16, [x9, #0x20]
stp q16, q16, [x9, #0x40]!
subs x10, x10, #64
bge pc-16 (-4 instructions)
stp xzr, xzr, [x9, #0x20]
str x0, [fp, #0x108] // [V00 this]
;; size=44 bbWeight=1 PerfScore 8.50
G_M53560_IG02: ;; offset=0x002C
movz x0, #0xB3E8
movk x0, #0x235A LSL #16
movk x0, #0x7FFB LSL #32
ldr w0, [x0]
cbz w0, G_M53560_IG04
;; size=20 bbWeight=1 PerfScore 5.50
G_M53560_IG03: ;; offset=0x0040
bl CORINFO_HELP_DBG_IS_JUST_MY_CODE
;; size=4 bbWeight=0.50 PerfScore 0.50
G_M53560_IG04: ;; offset=0x0044
nop
movz x0, #0xB798
movk x0, #0x5642 LSL #16
movk x0, #544 LSL #32
movz x1, #0x5B48 // code for TestLibrary.TestFramework:BeginScenario(System.String)
movk x1, #0x2378 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
nop
ptrue p0.d
mov z16.d, p0/z, #1
str q16, [fp, #0xC0] // [V05 tmp1]
ldr q16, [fp, #0xC0] // [V05 tmp1]
str q16, [fp, #0xF0] // [V01 loc0]
ptrue p0.d
mov z16.d, p0/z, #1
str q16, [fp, #0xB0] // [V06 tmp2]
ldr q16, [fp, #0xB0] // [V06 tmp2]
str q16, [fp, #0xE0] // [V02 loc1]
ldr q16, [fp, #0xF0] // [V01 loc0]
str q16, [fp, #0xA0] // [V07 tmp3]
ldr x0, [fp, #0x108] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x108] // [V00 this]
add x0, x0, #80
movz x1, #0x57B8 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray1Ptr():ulong:this
movk x1, #0x2378 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x98] // [V08 tmp4]
ldr q16, [fp, #0xA0] // [V07 tmp3]
ptrue p0.d
cmpne p0.d, p0/z, z16.d, #0
ldr x0, [fp, #0x98] // [V08 tmp4]
ld1d { z16.d }, p0/z, [x0]
str q16, [fp, #0x80] // [V09 tmp5]
ldr q16, [fp, #0xE0] // [V02 loc1]
str q16, [fp, #0x70] // [V10 tmp6]
ldr x0, [fp, #0x108] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x108] // [V00 this]
add x0, x0, #80
movz x1, #0x57D0 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray2Ptr():ulong:this
movk x1, #0x2378 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x68] // [V11 tmp7]
ldr q16, [fp, #0x70] // [V10 tmp6]
ptrue p0.d
cmpne p0.d, p0/z, z16.d, #0
ldr x0, [fp, #0x68] // [V11 tmp7]
ld1d { z16.d }, p0/z, [x0]
str q16, [fp, #0x50] // [V12 tmp8]
ldr q16, [fp, #0x80] // [V09 tmp5]
ptrue p0.d
cmpne p0.d, p0/z, z16.d, #0
ldr q16, [fp, #0x50] // [V12 tmp8]
ld1d { z16.d }, p0/z, [z16.d]
str q16, [fp, #0x40] // [V13 tmp9]
ldr q16, [fp, #0x40] // [V13 tmp9]
str q16, [fp, #0xD0] // [V03 loc2]
ldr x0, [fp, #0x108] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x108] // [V00 this]
add x0, x0, #80
movz x1, #0x5800 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_outArrayPtr():ulong:this
movk x1, #0x2378 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x38] // [V14 tmp10]
ldr x0, [fp, #0x38] // [V14 tmp10]
ldr q16, [fp, #0xD0] // [V03 loc2]
str q16, [x0]
nop
ldr x0, [fp, #0x108] // [V00 this]
str x0, [fp, #0x30] // [V15 tmp11]
ldr x0, [fp, #0x108] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x108] // [V00 this]
add x0, x0, #80
movz x1, #0x57B8 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray1Ptr():ulong:this
movk x1, #0x2378 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x28] // [V16 tmp12]
ldr x0, [fp, #0x108] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x108] // [V00 this]
add x0, x0, #80
movz x1, #0x57D0 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray2Ptr():ulong:this
movk x1, #0x2378 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x20] // [V17 tmp13]
ldr x0, [fp, #0x108] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x108] // [V00 this]
add x0, x0, #80
movz x1, #0x5800 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_outArrayPtr():ulong:this
movk x1, #0x2378 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x18] // [V18 tmp14]
ldr x0, [fp, #0x30] // [V15 tmp11]
ldr x1, [fp, #0x28] // [V16 tmp12]
ldr x2, [fp, #0x20] // [V17 tmp13]
ldr x3, [fp, #0x18] // [V18 tmp14]
movz x4, #0xB798
movk x4, #0x5642 LSL #16
movk x4, #544 LSL #32
movz x5, #0x59F8 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong:ValidateResult(ulong,ulong,ulong,System.String):this
movk x5, #0x2378 LSL #16
movk x5, #0x7FFB LSL #32
ldr x5, [x5]
blr x5
nop
nop
;; size=496 bbWeight=1 PerfScore 195.50
G_M53560_IG05: ;; offset=0x0234
ldp fp, lr, [sp], #0x110
ret lr
;; size=8 bbWeight=1 PerfScore 2.00
; Total bytes of code 572, prolog size 44, PerfScore 212.00, instruction count 143, allocated bytes for code 572 (MethodHash=30792ec7) for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong:RunBasicScenario_Load():this (MinOpts)
; ============================================================
Beginning scenario: RunBasicScenario_Load
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunBasicScenario_Load failed:
firstOp: (0, 5E-324)
secondOp: (2337981206411, 2337981206811)
result: (0, 2.767806072932817E+254)
Beginning scenario: RunBasicScenario_FalseMask
Beginning scenario: RunBasicScenario_NonFaulting
Beginning scenario: RunReflectionScenario_UnsafeRead
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunReflectionScenario_UnsafeRead failed:
firstOp: (0, 5E-324)
secondOp: (2337981206411, 2337981206811)
result: (0, 2.767806072932817E+254)
Beginning scenario: RunLclVarScenario_UnsafeRead
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunLclVarScenario_UnsafeRead failed:
firstOp: (0, 5E-324)
secondOp: (2337981206411, 2337981206811)
result: (0, 2.767806072932817E+254)
Beginning scenario: RunClassFldScenario
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunClassFldScenario failed:
firstOp: (0, 5E-324)
secondOp: (2337981206411, 2337981206811)
result: (0, 2.767806072932817E+254)
Beginning scenario: RunStructLclFldScenario
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunStructLclFldScenario failed:
firstOp: (5E-324, 5E-324)
secondOp: (2337981206584, 2337981206568)
result: (0.2008336353023702, 0.7613041418158811)
Beginning scenario: RunStructFldScenario
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunStructFldScenario failed:
firstOp: (0, 5E-324)
secondOp: (2337981206629, 2337981206721)
result: (0, 4.387755455581361E-134)
Beginning scenario: ConditionalSelect_ZeroOp
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
Sve.GatherVector<Double>(Double, UInt64, UInt64): ConditionalSelectScenario failed:
maskOp: (NaN, NaN)
firstOp: (0, 5E-324)
secondOp: (2337981206411, 2337981206811)
falseOp: (0, 0)
result: (0, 2.767806072932817E+254)
System.Exception: One or more scenarios did not complete as expected.
at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVector_Bases_double_ulong() in d:\git\runtime2\artifacts\tests\coreclr\obj\windows.arm64.Release\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_r\Sve_r\gen\Sve.GatherVector.Bases.double.ulong.cs:line 82
at Program.<<Main>$>g__TestExecutor191|0_192(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in d:\git\runtime2\src\tests\JIT\HardwareIntrinsics\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 5476
09:01:49.644 Failed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVector_Bases_double_ulong()
Last active
June 22, 2024 16:03
-
-
Save kunalspathak/3f8c38532531f6e0da834857d66b277d to your computer and use it in GitHub Desktop.
GatherVector test failure
D:\kpathak\Core_Root_callee_Save\Core_Root\corerun.exe -p "System.Reflection.Metadata.MetadataUpdater.IsSupported=false" -p "System.Runtime.Serialization.EnableUnsafeBinaryFormatterSerialization=true" D:\kpathak\tests\caller-save\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\HardwareIntrinsics_Arm_ro.dll Sve_GatherVector_Bases_double_ulong
08:59:00.361 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVector_Bases_double_ulong()
Supported ISAs:
AdvSimd: True
Aes: True
ArmBase: True
Crc32: True
Dp: True
Rdm: False
Sha1: True
Sha256: True
Sve: True
Beginning scenario: RunBasicScenario_UnsafeRead
; Assembly listing for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong:RunBasicScenario_Load():this (Tier0)
; Emitting BLENDED_CODE for generic ARM64 - Windows
; Tier0 code
; fp based frame
; partially interruptible
; Final local variable assignments
;
; V00 this [V00 ] ( 1, 1 ) ref -> [fp+0x68] do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong>
; V01 loc0 [V01 ] ( 1, 1 ) simd16 -> [fp+0x50] HFA(simd16) do-not-enreg[S] must-init <System.Numerics.Vector`1[ulong]>
; V02 loc1 [V02 ] ( 1, 1 ) simd16 -> [fp+0x40] HFA(simd16) do-not-enreg[S] must-init <System.Numerics.Vector`1[double]>
;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V04 tmp1 [V04 ] ( 1, 1 ) simd16 -> [fp+0x30] do-not-enreg[S] "non-inline candidate call"
; V05 tmp2 [V05 ] ( 1, 1 ) long -> [fp+0x28] do-not-enreg[] "non-inline candidate call"
; V06 tmp3 [V06 ] ( 1, 1 ) long -> [fp+0x20] do-not-enreg[] "non-inline candidate call"
; V07 tmp4 [V07 ] ( 1, 1 ) long -> [fp+0x18] do-not-enreg[] "argument with side effect"
;
; Lcl frame size = 96
G_M53560_IG01: ;; offset=0x0000
stp fp, lr, [sp, #-0x70]!
mov fp, sp
str xzr, [fp, #0x50] // [V01 loc0]
str xzr, [fp, #0x58] // [V01 loc0+0x08]
str xzr, [fp, #0x40] // [V02 loc1]
str xzr, [fp, #0x48] // [V02 loc1+0x08]
str x0, [fp, #0x68] // [V00 this]
;; size=28 bbWeight=1 PerfScore 6.50
G_M53560_IG02: ;; offset=0x001C
movz x0, #0xB890
movk x0, #0x19AA LSL #16
movk x0, #749 LSL #32
movz x1, #0x5F20 // code for TestLibrary.TestFramework:BeginScenario(System.String)
movk x1, #0x2379 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
ptrue p0.d
mov z16.d, p0/z, #1
str q16, [fp, #0x50] // [V01 loc0]
ldr x0, [fp, #0x68] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x68] // [V00 this]
add x0, x0, #80
movz x1, #0x5B90 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray1Ptr():ulong:this
movk x1, #0x2379 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
ptrue p0.d
mov z16.d, p0/z, #1
ptrue p0.d
cmpne p0.d, p0/z, z16.d, #0
ld1d { z16.d }, p0/z, [x0]
str q16, [fp, #0x30] // [V04 tmp1]
ldr x0, [fp, #0x68] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x68] // [V00 this]
add x0, x0, #80
movz x1, #0x5BA8 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray2Ptr():ulong:this
movk x1, #0x2379 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
ldr q16, [fp, #0x50] // [V01 loc0]
ptrue p0.d
cmpne p0.d, p0/z, z16.d, #0
ld1d { z16.d }, p0/z, [x0]
ldr q17, [fp, #0x30] // [V04 tmp1]
ptrue p0.d
cmpne p0.d, p0/z, z17.d, #0
ld1d { z16.d }, p0/z, [z16.d]
str q16, [fp, #0x40] // [V02 loc1]
ldr x0, [fp, #0x68] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x68] // [V00 this]
add x0, x0, #80
movz x1, #0x5BD8 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_outArrayPtr():ulong:this
movk x1, #0x2379 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
ldr q16, [fp, #0x40] // [V02 loc1]
str q16, [x0]
ldr x0, [fp, #0x68] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x68] // [V00 this]
add x0, x0, #80
movz x1, #0x5B90 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray1Ptr():ulong:this
movk x1, #0x2379 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x28] // [V05 tmp2]
ldr x0, [fp, #0x68] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x68] // [V00 this]
add x0, x0, #80
movz x1, #0x5BA8 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_inArray2Ptr():ulong:this
movk x1, #0x2379 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x20] // [V06 tmp3]
ldr x0, [fp, #0x68] // [V00 this]
ldrsb wzr, [x0]
ldr x0, [fp, #0x68] // [V00 this]
add x0, x0, #80
movz x1, #0x5BD8 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong+DataTable:get_outArrayPtr():ulong:this
movk x1, #0x2379 LSL #16
movk x1, #0x7FFB LSL #32
ldr x1, [x1]
blr x1
str x0, [fp, #0x18] // [V07 tmp4]
ldr x3, [fp, #0x18] // [V07 tmp4]
ldr x1, [fp, #0x28] // [V05 tmp2]
ldr x2, [fp, #0x20] // [V06 tmp3]
ldr x0, [fp, #0x68] // [V00 this]
movz x4, #0xB890
movk x4, #0x19AA LSL #16
movk x4, #749 LSL #32
movz x5, #0x5DD0 // code for JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong:ValidateResult(ulong,ulong,ulong,System.String):this
movk x5, #0x2379 LSL #16
movk x5, #0x7FFB LSL #32
ldr x5, [x5]
blr x5
;; size=388 bbWeight=1 PerfScore 160.00
G_M53560_IG03: ;; offset=0x01A0
ldp fp, lr, [sp], #0x70
ret lr
;; size=8 bbWeight=1 PerfScore 2.00
; Total bytes of code 424, prolog size 24, PerfScore 168.50, instruction count 106, allocated bytes for code 424 (MethodHash=30792ec7) for method JIT.HardwareIntrinsics.Arm._Sve.SveGatherVectorVectorBasesTest__Sve_GatherVector_Bases_double_ulong:RunBasicScenario_Load():this (Tier0)
; ============================================================
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunBasicScenario_FalseMask
Beginning scenario: RunBasicScenario_NonFaulting
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Sve.GatherVector<Double>(Double, UInt64, UInt64): RunStructFldScenario failed:
firstOp: (0, 5E-324)
secondOp: (3217426094748, 3217426095316)
result: (0, 2.762077479708614E-82)
Beginning scenario: ConditionalSelect_ZeroOp
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
System.Exception: One or more scenarios did not complete as expected.
at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVector_Bases_double_ulong() in d:\git\runtime2\artifacts\tests\coreclr\obj\windows.arm64.Release\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.GatherVector.Bases.double.ulong.cs:line 82
at Program.<<Main>$>g__TestExecutor191|0_192(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in d:\git\runtime2\src\tests\JIT\HardwareIntrinsics\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 5476
08:59:00.793 Failed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVector_Bases_double_ulong()
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment