Test TIM5 PWM on a TI8148

test_tim5_pwm.sh

#!/bin/sh
#
# This generates a test PWM that  should be ~ 1.2kHz @ 75% +duty cycle
# on TI8148 boards with the default timer clock source
#

# Parse devmem2 output
get_devmem2() {
    devmem2 $1 w | grep "^Read" | sed -e "s/.*:\s*//"
}

# It doesn't appear that we need to mess with too many clocks
# but keep fclk and iclk in mind if something doesn't work

# Switch pin mux to TIM5_IO, this is on ball G2, EVM J21.13
# Primary mux name is MCA3_AXR1
devmem2 0x481408bc w 0x00000040 || exit 1
# Note: for some reason this doesn't work from Linux and the
# PINCTL/PINCTRL/MUXMODE registers aren't docuemnted in the TRM or datasheet, 
# it appears that they are locked.  Writing instead from u-boot works:
# mw.l 0x481408bc 0x40
devmem2 0x481408bc w || exit 1

# Timer 5 Base Addr = 0x48046000

# Reset Timer (TIOCP_CFG)
devmem2 0x48046004 w 0x1 || exit 1
sleep 0.1 

# Configure PWM Load register (TLDR)
devmem2 0x48046040 w 0xFFFFc000 || exit 2

# Set PWM Match Register (TMAR)
devmem2 0x4804604c w 0xFFFFf000 || exit 3

# Trigger loading of TTCR from TLDR by writing to TTGR
devmem2 0x48046044 w 0x1 || exit 4

# Configure timer and start it
devmem2 0x48046038 w 0x01843 || exit 5

echo "Verify that it's counting by reading the counter register"
echo
echo -ne "First read: \t"
get_devmem2 0x4804603c
echo -ne "Second read: \t"
get_devmem2 0x4804603c