si5351 phase

#include "si5351.h"
#include "Wire.h"

Si5351 si5351;

unsigned  long long n = 600;

bool set_phase90(unsigned long long frequency)
{
  unsigned long long pll_freq = frequency * n;
if(pll_freq > 90000000000)
{
  n = n - 10;
  }
  // Set PLLA to the chosen frequency
  si5351.set_pll(pll_freq, SI5351_PLLA);
  
  // Set CLK0 and CLK1 to use PLLA as the MS source
  si5351.set_ms_source(SI5351_CLK0, SI5351_PLLA);
  si5351.set_ms_source(SI5351_CLK1, SI5351_PLLA);
  
  // Set CLK0 and CLK1 to output 14.1 MHz with a fixed PLL frequency
  si5351.set_freq(frequency, pll_freq, SI5351_CLK0);
  si5351.set_freq(frequency, pll_freq, SI5351_CLK1);

  // Now we can set CLK1 to have a 90 deg phase shift by entering
  // 50 in the CLK1 phase register, since the ratio of the PLL to
  // the clock frequency is 50.
  si5351.set_phase(SI5351_CLK0, 0);
  si5351.set_phase(SI5351_CLK1, n);
  
  // We need to reset the PLL before they will be in phase alignment
  si5351.pll_reset(SI5351_PLLA);
  }