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Last active Apr 6, 2019

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Kendryte K210 / Maix Go memory map

Kendryte K210 / Maix Go memory map

This is a very rough memory map for the Kendryte K210. For some reason this is missing from the data sheet. I've tried to use the same naming when possible.

from       to           description
---------- ----------   ---------------------------------------
0x00000000 0x00000fff   DEBUG
0x00001000 0x00001fff   ROMCPU
0x02000000 0x03ffffff   CLINT (Under CorePlex)
0x0c000000 0x0fffffff   PLIC (Under CorePlex)
0x38000000              UARTHS (Under TileLink)
0x38001000              GPIOHS (Under TileLink)
0x40000000 0x403fffff   General-purpose SRAM MEM0 (non-cached)
0x40400000 0x405fffff   General-purpose SRAM MEM1 (non-cached)
0x40600000 0x407fffff   AI SRAM (non-cached)
0x42000000 0x423fffff   FFT (Under AXI 64-bit)
0x50000000              DMAC (Under AHB 32-bit)
0x50200000              GPIO (Under APB1 32 bit)
0x50210000              UART1 (Under APB1 32 bit)
0x50220000              UART2 (Under APB1 32 bit)
0x50230000              UART3 (Under APB1 32 bit)
0x50240000              SPI (Under APB1 32 bit)
0x50250000              I2S0 (Under APB1 32 bit)
0x50260000              I2S1 (Under APB1 32 bit)
0x50270000              I2S2 (Under APB1 32 bit)
0x50280000              I2C0 (Under APB1 32 bit)
0x50290000              I2C1 (Under APB1 32 bit)
0x502a0000              I2C2 (Under APB1 32 bit)
0x502b0000              FPIOA (Under APB1 32 bit) 
0x502c0000              SHA256 (Under APB1 32 bit)
0x502d0000              TIMER0 (Under APB1 32 bit)
0x502e0000              TIMER1 (Under APB1 32 bit)
0x502f0000              TIMER2 (Under APB1 32 bit)
0x50400000              WDT0 (Under APB2 32 bit)
0x50410000              WDT1 (Under APB2 32 bit)
0x50420000              OTP (Under APB2 32 bit)
0x50430000              DV (Under APB2 32 bit)P
0x50440000              SYSCTL (Under APB2 32 bit)
0x50450000              AES (Under APB2 32 bit)
0x50460000              RTC (Under APB2 32 bit)
0x52000000              SPI0 (Under APB3 32 bit)
0x53000000              SPI1 (Under APB3 32 bit)
0x54000000              SPI3 (Under APB3 32 bit)
0x80000000 0x803fffff   General-purpose SRAM MEM0 (cached)
0x80400000 0x805fffff   General-purpose SRAM MEM1 (cached)
0x80600000 0x807fffff   AI SRAM (cached)
0x88000000 0x8801ffff   ROM


  • LicheeDan_K210_examples/lib/bsp/include/platform.h/platform.h
  • ROM dump

Boot sequence

ROMCPU (0x00001000) seems to be the initial boot vector, from there, there's a jump to the beginning of the main ROM (0x88000000). This ROM implements loading of the flash to memory at 0x80000000 and jumping to it, as well as "ISP" mode for directly uploading a program from the serial port (this is used by for flashing).

ISP mode

From the datasheet:

IO_16 is used for boot mode selection. During power-on reset, pull high to bootfrom FLASH and pull low to enter ISP mode. After reset, IO_0, IO_1, IO_2, and IO_3are JTAG pins. IO_4 and IO_5 are ISP pins

A packet-based protocol over serial (at baudrate 115200) is used to communicate with the device. The following commands are documented to exist in ISP mode (source:

0xC2 NOP

Packets are encoded in so-called SLIP format. This means 0xc0 is used as packet beginning and end marker, the escape sequence 0xdb 0xdc is used to encode 0xc0, and 0xdb 0xdd encodes 0xdb. The first byte of a packet is the command or response code.

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