top.picorv32.debug.v

(* \nmigen.hierarchy  = "top.U$$3" *)
(* generator = "nMigen" *)
module \U$$3 (clk, led);
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire [31:0] \$10 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$12 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$14 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$16 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire [31:0] \$18 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$2 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$20 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$22 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
  wire \$24 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
  wire \$26 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
  wire \$28 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$30 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$32 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$34 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire [3:0] \$35 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire [31:0] \$38 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$4 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$40 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$42 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:67" *)
  wire [31:0] \$44 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:67" *)
  wire [31:0] \$45 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$47 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$49 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$51 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire [3:0] \$52 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire [31:0] \$55 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$57 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$59 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire \$6 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$61 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$63 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$65 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire [31:0] \$67 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$69 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
  wire [3:0] \$7 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$71 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:73" *)
  wire [31:0] \$73 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:73" *)
  wire [31:0] \$74 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$76 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$78 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$80 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire [31:0] \$82 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$84 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
  wire \$86 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$88 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
  wire \$90 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
  wire \$92 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
  wire \$94 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
  wire \$96 ;
  (* src = "/Users/lachlansneff/dev/fpga-test/ice40_pll.py:23" *)
  input clk;
  (* src = "/Users/lachlansneff/dev/fpga-test/top.py:30" *)
  output led;
  reg led;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:36" *)
  wire [31:0] mem_addr;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:60" *)
  reg [7:0] mem_r_addr;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:60" *)
  wire [31:0] mem_r_data;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:39" *)
  reg [31:0] mem_rdata;
  (* init = 1'h0 *)
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:35" *)
  reg mem_ready = 1'h0;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:35" *)
  reg \mem_ready$next ;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:34" *)
  wire mem_valid;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:61" *)
  reg [7:0] mem_w_addr;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:61" *)
  reg [31:0] mem_w_data;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:61" *)
  wire [3:0] mem_w_en;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:37" *)
  wire [31:0] mem_wdata;
  (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:38" *)
  wire [3:0] mem_wstrb;
  (* src = "/Users/lachlansneff/dev/fpga-test/ice40_pll.py:23" *)
  wire rst;
  assign \$10  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) 2'h2;
  assign \$12  = \$10  < (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) 9'h100;
  assign \$14  = \$6  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) \$12 ;
  assign \$16  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) mem_wstrb;
  assign \$18  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) 2'h2;
  assign \$20  = \$18  < (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) 9'h100;
  assign \$22  = \$16  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) \$20 ;
  assign \$24  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *) mem_wstrb;
  assign \$26  = mem_addr == (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *) 32'd3405691568;
  assign \$28  = \$24  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *) \$26 ;
  assign \$2  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) mem_ready;
  assign \$30  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) mem_ready;
  assign \$32  = mem_valid & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) \$30 ;
  assign \$35  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) mem_wstrb;
  assign \$34  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) \$35 ;
  assign \$38  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) 2'h2;
  assign \$40  = \$38  < (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) 9'h100;
  assign \$42  = \$34  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) \$40 ;
  assign \$45  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:67" *) 2'h2;
  assign \$47  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) mem_ready;
  assign \$4  = mem_valid & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) \$2 ;
  assign \$49  = mem_valid & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) \$47 ;
  assign \$52  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) mem_wstrb;
  assign \$51  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) \$52 ;
  assign \$55  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) 2'h2;
  assign \$57  = \$55  < (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) 9'h100;
  assign \$59  = \$51  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) \$57 ;
  assign \$61  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) mem_ready;
  assign \$63  = mem_valid & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) \$61 ;
  assign \$65  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) mem_wstrb;
  assign \$67  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) 2'h2;
  assign \$69  = \$67  < (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) 9'h100;
  assign \$71  = \$65  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) \$69 ;
  assign \$74  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:73" *) 2'h2;
  assign \$76  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) mem_ready;
  assign \$78  = mem_valid & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) \$76 ;
  assign \$7  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) mem_wstrb;
  assign \$80  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) mem_wstrb;
  assign \$82  = mem_addr >>> (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) 2'h2;
  assign \$84  = \$82  < (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) 9'h100;
  assign \$86  = \$80  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *) \$84 ;
  assign \$88  = ~ (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) mem_ready;
  assign \$6  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *) \$7 ;
  assign \$90  = mem_valid & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *) \$88 ;
  assign \$92  = | (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *) mem_wstrb;
  assign \$94  = mem_addr == (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *) 32'd3405691568;
  assign \$96  = \$92  & (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *) \$94 ;
  always @(posedge clk)
      mem_ready <= \mem_ready$next ;
  reg [31:0] mem [255:0];
  initial begin
    mem[0] = 32'd20971631;
    mem[1] = 32'd0;
    mem[2] = 32'd0;
    mem[3] = 32'd0;
    mem[4] = 32'd4194415;
    mem[5] = 32'd407;
    mem[6] = 32'd2126610835;
    mem[7] = 32'd98835;
    mem[8] = 32'd279;
    mem[9] = 32'd1040253203;
    mem[10] = 32'd66611;
    mem[11] = 32'd8388719;
    mem[12] = 32'd4267700335;
    mem[13] = 32'd3322286401;
    mem[14] = 32'd151;
    mem[15] = 32'd117473511;
    mem[16] = 32'd1335;
    mem[17] = 32'd328979;
    mem[18] = 32'd1463;
    mem[19] = 32'd361875;
    mem[20] = 32'd10876771;
    mem[21] = 32'd368675;
    mem[22] = 32'd3991078289;
    mem[23] = 32'd87555749;
    mem[24] = 32'd85131264;
    mem[25] = 32'd95879173;
    mem[26] = 32'd2241003520;
    mem[27] = 32'd4234346501;
    mem[28] = 32'd104267941;
    mem[29] = 32'd101908480;
    mem[30] = 32'd1108609734;
    mem[31] = 32'd93438356;
    mem[32] = 32'd3974301201;
    mem[33] = 32'd9961125;
    mem[34] = 32'd2162622464;
    mem[35] = 32'd288;
    mem[36] = 32'd791;
    mem[37] = 32'd23265383;
    mem[38] = 32'd3405694263;
    mem[39] = 32'd2869232915;
    mem[40] = 32'd3238811133;
    mem[41] = 32'd2156044289;
    mem[42] = 32'd32898;
    mem[43] = 32'd0;
    mem[44] = 32'd0;
    mem[45] = 32'd0;
    mem[46] = 32'd0;
    mem[47] = 32'd0;
    mem[48] = 32'd0;
    mem[49] = 32'd0;
    mem[50] = 32'd0;
    mem[51] = 32'd0;
    mem[52] = 32'd0;
    mem[53] = 32'd0;
    mem[54] = 32'd0;
    mem[55] = 32'd0;
    mem[56] = 32'd0;
    mem[57] = 32'd0;
    mem[58] = 32'd0;
    mem[59] = 32'd0;
    mem[60] = 32'd0;
    mem[61] = 32'd0;
    mem[62] = 32'd0;
    mem[63] = 32'd0;
    mem[64] = 32'd0;
    mem[65] = 32'd0;
    mem[66] = 32'd0;
    mem[67] = 32'd0;
    mem[68] = 32'd0;
    mem[69] = 32'd0;
    mem[70] = 32'd0;
    mem[71] = 32'd0;
    mem[72] = 32'd0;
    mem[73] = 32'd0;
    mem[74] = 32'd0;
    mem[75] = 32'd0;
    mem[76] = 32'd0;
    mem[77] = 32'd0;
    mem[78] = 32'd0;
    mem[79] = 32'd0;
    mem[80] = 32'd0;
    mem[81] = 32'd0;
    mem[82] = 32'd0;
    mem[83] = 32'd0;
    mem[84] = 32'd0;
    mem[85] = 32'd0;
    mem[86] = 32'd0;
    mem[87] = 32'd0;
    mem[88] = 32'd0;
    mem[89] = 32'd0;
    mem[90] = 32'd0;
    mem[91] = 32'd0;
    mem[92] = 32'd0;
    mem[93] = 32'd0;
    mem[94] = 32'd0;
    mem[95] = 32'd0;
    mem[96] = 32'd0;
    mem[97] = 32'd0;
    mem[98] = 32'd0;
    mem[99] = 32'd0;
    mem[100] = 32'd0;
    mem[101] = 32'd0;
    mem[102] = 32'd0;
    mem[103] = 32'd0;
    mem[104] = 32'd0;
    mem[105] = 32'd0;
    mem[106] = 32'd0;
    mem[107] = 32'd0;
    mem[108] = 32'd0;
    mem[109] = 32'd0;
    mem[110] = 32'd0;
    mem[111] = 32'd0;
    mem[112] = 32'd0;
    mem[113] = 32'd0;
    mem[114] = 32'd0;
    mem[115] = 32'd0;
    mem[116] = 32'd0;
    mem[117] = 32'd0;
    mem[118] = 32'd0;
    mem[119] = 32'd0;
    mem[120] = 32'd0;
    mem[121] = 32'd0;
    mem[122] = 32'd0;
    mem[123] = 32'd0;
    mem[124] = 32'd0;
    mem[125] = 32'd0;
    mem[126] = 32'd0;
    mem[127] = 32'd0;
    mem[128] = 32'd0;
    mem[129] = 32'd0;
    mem[130] = 32'd0;
    mem[131] = 32'd0;
    mem[132] = 32'd0;
    mem[133] = 32'd0;
    mem[134] = 32'd0;
    mem[135] = 32'd0;
    mem[136] = 32'd0;
    mem[137] = 32'd0;
    mem[138] = 32'd0;
    mem[139] = 32'd0;
    mem[140] = 32'd0;
    mem[141] = 32'd0;
    mem[142] = 32'd0;
    mem[143] = 32'd0;
    mem[144] = 32'd0;
    mem[145] = 32'd0;
    mem[146] = 32'd0;
    mem[147] = 32'd0;
    mem[148] = 32'd0;
    mem[149] = 32'd0;
    mem[150] = 32'd0;
    mem[151] = 32'd0;
    mem[152] = 32'd0;
    mem[153] = 32'd0;
    mem[154] = 32'd0;
    mem[155] = 32'd0;
    mem[156] = 32'd0;
    mem[157] = 32'd0;
    mem[158] = 32'd0;
    mem[159] = 32'd0;
    mem[160] = 32'd0;
    mem[161] = 32'd0;
    mem[162] = 32'd0;
    mem[163] = 32'd0;
    mem[164] = 32'd0;
    mem[165] = 32'd0;
    mem[166] = 32'd0;
    mem[167] = 32'd0;
    mem[168] = 32'd0;
    mem[169] = 32'd0;
    mem[170] = 32'd0;
    mem[171] = 32'd0;
    mem[172] = 32'd0;
    mem[173] = 32'd0;
    mem[174] = 32'd0;
    mem[175] = 32'd0;
    mem[176] = 32'd0;
    mem[177] = 32'd0;
    mem[178] = 32'd0;
    mem[179] = 32'd0;
    mem[180] = 32'd0;
    mem[181] = 32'd0;
    mem[182] = 32'd0;
    mem[183] = 32'd0;
    mem[184] = 32'd0;
    mem[185] = 32'd0;
    mem[186] = 32'd0;
    mem[187] = 32'd0;
    mem[188] = 32'd0;
    mem[189] = 32'd0;
    mem[190] = 32'd0;
    mem[191] = 32'd0;
    mem[192] = 32'd0;
    mem[193] = 32'd0;
    mem[194] = 32'd0;
    mem[195] = 32'd0;
    mem[196] = 32'd0;
    mem[197] = 32'd0;
    mem[198] = 32'd0;
    mem[199] = 32'd0;
    mem[200] = 32'd0;
    mem[201] = 32'd0;
    mem[202] = 32'd0;
    mem[203] = 32'd0;
    mem[204] = 32'd0;
    mem[205] = 32'd0;
    mem[206] = 32'd0;
    mem[207] = 32'd0;
    mem[208] = 32'd0;
    mem[209] = 32'd0;
    mem[210] = 32'd0;
    mem[211] = 32'd0;
    mem[212] = 32'd0;
    mem[213] = 32'd0;
    mem[214] = 32'd0;
    mem[215] = 32'd0;
    mem[216] = 32'd0;
    mem[217] = 32'd0;
    mem[218] = 32'd0;
    mem[219] = 32'd0;
    mem[220] = 32'd0;
    mem[221] = 32'd0;
    mem[222] = 32'd0;
    mem[223] = 32'd0;
    mem[224] = 32'd0;
    mem[225] = 32'd0;
    mem[226] = 32'd0;
    mem[227] = 32'd0;
    mem[228] = 32'd0;
    mem[229] = 32'd0;
    mem[230] = 32'd0;
    mem[231] = 32'd0;
    mem[232] = 32'd0;
    mem[233] = 32'd0;
    mem[234] = 32'd0;
    mem[235] = 32'd0;
    mem[236] = 32'd0;
    mem[237] = 32'd0;
    mem[238] = 32'd0;
    mem[239] = 32'd0;
    mem[240] = 32'd0;
    mem[241] = 32'd0;
    mem[242] = 32'd0;
    mem[243] = 32'd0;
    mem[244] = 32'd0;
    mem[245] = 32'd0;
    mem[246] = 32'd0;
    mem[247] = 32'd0;
    mem[248] = 32'd0;
    mem[249] = 32'd0;
    mem[250] = 32'd0;
    mem[251] = 32'd0;
    mem[252] = 32'd0;
    mem[253] = 32'd0;
    mem[254] = 32'd0;
    mem[255] = 32'd0;
  end
  reg [7:0] _0_;
  always @(posedge clk) begin
    _0_ <= mem_r_addr;
  end
  assign mem_r_data = mem[_0_];
  picorv32 #(
    .CATCH_ILLINSN(32'd0),
    .CATCH_MISALIGN(32'd0),
    .ENABLE_COUNTERS(32'd0),
    .LATCHED_MEM_RDATA(32'd1),
    .TWO_CYCLE_ALU(32'd1),
    .TWO_STAGE_SHIFT(32'd0)
  ) picorv32 (
    .clk(clk),
    .mem_addr(mem_addr),
    .mem_rdata(mem_rdata),
    .mem_ready(mem_ready),
    .mem_valid(mem_valid),
    .mem_wdata(mem_wdata),
    .mem_wstrb(mem_wstrb),
    .resetn(1'h0)
  );
  always @* begin
    \mem_ready$next  = mem_ready;
    \mem_ready$next  = 1'h0;
    (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
    casez (\$4 )
      /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" */
      1'h1:
        begin
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
          casez (\$14 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" */
            1'h1:
                \mem_ready$next  = 1'h1;
          endcase
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
          casez (\$22 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" */
            1'h1:
                \mem_ready$next  = 1'h1;
          endcase
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
          casez (\$28 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" */
            1'h1:
                \mem_ready$next  = 1'h1;
          endcase
        end
    endcase
    (* src = "/Users/lachlansneff/Library/Python/3.9/lib/python/site-packages/nmigen/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \mem_ready$next  = 1'h0;
    endcase
  end
  always @* begin
    mem_r_addr = 8'h00;
    (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
    casez (\$32 )
      /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" */
      1'h1:
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
          casez (\$42 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" */
            1'h1:
                mem_r_addr = \$44 [7:0];
          endcase
    endcase
  end
  always @* begin
    mem_rdata = 32'd0;
    (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
    casez (\$49 )
      /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" */
      1'h1:
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" *)
          casez (\$59 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:65" */
            1'h1:
                mem_rdata = mem_r_data;
          endcase
    endcase
  end
  always @* begin
    mem_w_addr = 8'h00;
    (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
    casez (\$63 )
      /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" */
      1'h1:
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
          casez (\$71 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" */
            1'h1:
                mem_w_addr = \$73 [7:0];
          endcase
    endcase
  end
  always @* begin
    mem_w_data = 32'd0;
    (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
    casez (\$78 )
      /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" */
      1'h1:
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" *)
          casez (\$86 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:72" */
            1'h1:
              begin
                (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:74" *)
                casez (mem_wstrb[0])
                  /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:74" */
                  1'h1:
                      mem_w_data[7:0] = mem_wdata[7:0];
                endcase
                (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:76" *)
                casez (mem_wstrb[1])
                  /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:76" */
                  1'h1:
                      mem_w_data[15:8] = mem_wdata[15:8];
                endcase
                (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:78" *)
                casez (mem_wstrb[2])
                  /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:78" */
                  1'h1:
                      mem_w_data[23:16] = mem_wdata[23:16];
                endcase
                (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:80" *)
                casez (mem_wstrb[3])
                  /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:80" */
                  1'h1:
                      mem_w_data[31:24] = mem_wdata[31:24];
                endcase
              end
          endcase
    endcase
  end
  always @* begin
    led = 1'h0;
    (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" *)
    casez (\$90 )
      /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:64" */
      1'h1:
          (* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" *)
          casez (\$96 )
            /* src = "/Users/lachlansneff/dev/fpga-test/picorv32.py:86" */
            1'h1:
                led = mem_wdata[0];
          endcase
    endcase
  end
  assign \$44  = \$45 ;
  assign \$73  = \$74 ;
  assign rst = 1'h0;
  assign mem_w_en = 4'h0;
endmodule