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@lategoodbye
Last active August 29, 2015 14:19
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Logical diagram of i.MX23 DC-DC clock domain
ref_xtal |\
------------------------------------------------------------->| \
| \ +----------+
| \ | |
ref_pll |\ | +--------------------> CLK_DCDC |
--------------->| \ +---------+ | / | |
| \ | | | / +----------+
| +------------------> DIV INT |----------->| /
ref_gpmi | / | | |/
--------------->| / +---------+ HW_POWER_MISC_SEL_PLLCLK
|/ HW_POWER_MISC_FREQSEL
HW_POWER_MISC_FREQSEL
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