Nand2Tetris Project 1: Logic Gates

And.hdl

/**
 * And gate:
 * out = 1 if (a == 1 and b == 1)
 *       0 otherwise
 */

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
    Nand(a=a, b=b, out=notaOrb);
    Not(in=notaOrb, out=out);
}

And16.hdl

/**
 * 16-bit bitwise And:
 * for i = 0..15: out[i] = (a[i] and b[i])
 */

CHIP And16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    Nand16(a=a, b=b, out=notaOrb);
    Not16(in=notaOrb, out=out);
}

And16Broadcast.hdl

/**
 * 16-bit broadcasting And:
 * for i = 0..15: out[i] = (a[i] and b)
 */
 
CHIP And16Broadcast {
    IN a[16], b;
    OUT out[16];

    PARTS:
    Nand16Broadcast(a=a, b=b, out=notaOrb);
    Not16(in=notaOrb, out=out);
}

And3.hdl

/**
 * And3 gate:
 * out = 1 if (a == 1 and b == 1 and c == 1)
 *       0 otherwise
 */

CHIP And3 {
    IN a, b, c;
    OUT out;

    PARTS:
    And(a=a, b=b, out=ab);
    And(a=ab, b=c, out=out);
}

DMux.hdl

/**
 * Demultiplexor:
 * {a, b} = {in, 0} if sel == 0
 *          {0, in} if sel == 1
 */

CHIP DMux {
    IN in, sel;
    OUT a, b;

    PARTS:
    Not(in=sel, out=nsel);
    And(a=in, b=nsel, out=a);
    And(a=in, b=sel, out=b);
}

DMux4Way.hdl

/**
 * 4-way demultiplexor:
 * {a, b, c, d} = {in, 0, 0, 0} if sel == 00
 *                {0, in, 0, 0} if sel == 01
 *                {0, 0, in, 0} if sel == 10
 *                {0, 0, 0, in} if sel == 11
 */

CHIP DMux4Way {
    IN in, sel[2];
    OUT a, b, c, d;

    PARTS:
    Not(in=sel[1], out=nsel1);
    And(a=nsel1,  b=in, out=inAB);
    And(a=sel[1], b=in, out=inCD);

    DMux(in=inAB, sel=sel[0], a=a, b=b);
    DMux(in=inCD, sel=sel[0], a=c, b=d);
}

DMux8Way.hdl

/**
 * 8-way demultiplexor:
 * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000
 *                            {0, in, 0, 0, 0, 0, 0, 0} if sel == 001
 *                            etc.
 *                            {0, 0, 0, 0, 0, 0, 0, in} if sel == 111
 */

CHIP DMux8Way {
    IN in, sel[3];
    OUT a, b, c, d, e, f, g, h;

    PARTS:
    Not(in=sel[2], out=nsel2);
    And(a=nsel2,  b=in, out=inABCD);
    And(a=sel[2], b=in, out=inEFGH);

    DMux4Way(in=inABCD, sel=sel[0..1], a=a, b=b, c=c, d=d);
    DMux4Way(in=inEFGH, sel=sel[0..1], a=e, b=f, c=g, d=h);
}

Mux.hdl

/**
 * Multiplexor:
 * out = a if sel == 0
 *       b otherwise
 */

CHIP Mux {
    IN a, b, sel;
    OUT out;

    PARTS:
    Not(in=sel, out=nsel);
    And(a=a, b=nsel, out=x);
    And(a=b, b=sel, out=y);
    Or(a=x, b=y, out=out);
}

Mux16.hdl

/**
 * 16-bit multiplexor:
 * for i = 0..15 out[i] = a[i] if sel == 0
 *                        b[i] if sel == 1
 */

CHIP Mux16 {
    IN a[16], b[16], sel;
    OUT out[16];

    PARTS:
    Not(in=sel, out=nsel);
    And16Broadcast(a=a, b=nsel, out=x);
    And16Broadcast(a=b, b=sel, out=y);
    Or16(a=x, b=y, out=out);
}

Mux4Way16.hdl

/**
 * 4-way 16-bit multiplexor:
 * out = a if sel == 00
 *       b if sel == 01
 *       c if sel == 10
 *       d if sel == 11
 */

CHIP Mux4Way16 {
    IN a[16], b[16], c[16], d[16], sel[2];
    OUT out[16];

    PARTS:
    Mux16(a=a, b=b, sel=sel[0], out=x);
    Mux16(a=c, b=d, sel=sel[0], out=y);
    Mux16(a=x, b=y, sel=sel[1], out=out);
}

Mux8Way16.hdl

/**
 * 8-way 16-bit multiplexor:
 * out = a if sel == 000
 *       b if sel == 001
 *       etc.
 *       h if sel == 111
 */

CHIP Mux8Way16 {
    IN a[16], b[16], c[16], d[16],
       e[16], f[16], g[16], h[16],
       sel[3];
    OUT out[16];

    PARTS:
    Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=x);
    Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=y);
    Mux16(a=x, b=y, sel=sel[2], out=out);
}

Nand16.hdl

/**
 * 16-bit bitwise Nand:
 * for i = 0..15: out[i] = (a[i] nand b[i])
 */
 
CHIP Nand16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    Nand(a=a[0], b=b[0], out=out[0]);
    Nand(a=a[1], b=b[1], out=out[1]);
    Nand(a=a[2], b=b[2], out=out[2]);
    Nand(a=a[3], b=b[3], out=out[3]);
    Nand(a=a[4], b=b[4], out=out[4]);
    Nand(a=a[5], b=b[5], out=out[5]);
    Nand(a=a[6], b=b[6], out=out[6]);
    Nand(a=a[7], b=b[7], out=out[7]);
    Nand(a=a[8], b=b[8], out=out[8]);
    Nand(a=a[9], b=b[9], out=out[9]);
    Nand(a=a[10], b=b[10], out=out[10]);
    Nand(a=a[11], b=b[11], out=out[11]);
    Nand(a=a[12], b=b[12], out=out[12]);
    Nand(a=a[13], b=b[13], out=out[13]);
    Nand(a=a[14], b=b[14], out=out[14]);
    Nand(a=a[15], b=b[15], out=out[15]);
}

Nand16Broadcast.hdl

/**
 * 16-bit broadcasting Nand:
 * for i = 0..15: out[i] = (a[i] nand b)
 */

CHIP Nand16Broadcast {
    IN a[16], b;
    OUT out[16];

    PARTS:
    Nand(a=a[0], b=b, out=out[0]);
    Nand(a=a[1], b=b, out=out[1]);
    Nand(a=a[2], b=b, out=out[2]);
    Nand(a=a[3], b=b, out=out[3]);
    Nand(a=a[4], b=b, out=out[4]);
    Nand(a=a[5], b=b, out=out[5]);
    Nand(a=a[6], b=b, out=out[6]);
    Nand(a=a[7], b=b, out=out[7]);
    Nand(a=a[8], b=b, out=out[8]);
    Nand(a=a[9], b=b, out=out[9]);
    Nand(a=a[10], b=b, out=out[10]);
    Nand(a=a[11], b=b, out=out[11]);
    Nand(a=a[12], b=b, out=out[12]);
    Nand(a=a[13], b=b, out=out[13]);
    Nand(a=a[14], b=b, out=out[14]);
    Nand(a=a[15], b=b, out=out[15]);
}

Not.hdl

/**
 * Not gate:
 * out = not in
 */

CHIP Not {
    IN in;
    OUT out;

    PARTS:
    Nand(a=in, b=in, out=out);
}

Not16.hdl

/**
 * 16-bit Not:
 * for i=0..15: out[i] = not in[i]
 */

CHIP Not16 {
    IN in[16];
    OUT out[16];

    PARTS:
    Nand16(a=in, b=in, out=out);
}

Or.hdl

 /**
 * Or gate:
 * out = 1 if (a == 1 or b == 1)
 *       0 otherwise
 */

CHIP Or {
    IN a, b;
    OUT out;

    PARTS:
    Not(in=a, out=nota);
    Not(in=b, out=notb);
    Nand(a=nota, b=notb, out=out);
}

Or16.hdl

/**
 * 16-bit bitwise Or:
 * for i = 0..15 out[i] = (a[i] or b[i])
 */

CHIP Or16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    Not16(in=a, out=nota);
    Not16(in=b, out=notb);
    Nand16(a=nota, b=notb, out=out);
}

Or8Way.hdl

/**
 * 8-way Or:
 * out = (in[0] or in[1] or ... or in[7])
 */

CHIP Or8Way {
    IN in[8];
    OUT out;

    PARTS:
    Or(a=in[0], b=in[1], out=t1);
    Or(a=in[2], b=t1, out=t2);
    Or(a=in[3], b=t2, out=t3);
    Or(a=in[4], b=t3, out=t4);
    Or(a=in[5], b=t4, out=t5);
    Or(a=in[6], b=t5, out=t6);
    Or(a=in[7], b=t6, out=out);
}

Xor.hdl

/**
 * Exclusive-or gate:
 * out = not (a == b)
 *
 * XOR(A,B) = (A+B) * !(A*B)
 */

CHIP Xor {
    IN a, b;
    OUT out;

    PARTS:
    Nand(a=a, b=b, out=aNandB);
    Or(a=a, b=b, out=aOrB);
    And(a=aNandB, b=aOrB, out=out);
}