Ethan Zheng legendbb

## README.md

      
        
          
            
              
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                j-marjanovic
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              January 3, 2023 00:03
            
              
                Simple example of MyHDL and Verilog co-simulation
              
          
        
      
        
  
      
    Introduction

This code snippet demonstrates a co-simulation of Verilog code and MyHDL code.
The three modules here presents the absolute minimum for a co-simulation.
The counter_top.v is the top level module. It instantiates the counter module
(found in file counter.v), which is the module we would like to evaluate. Also
instantiated are the signals which are feed from and to MyHDL.