ULA screen line timing

ula_screen.md

T-State	Area	Latch	Write
0	left border	mask 1 (border)	latch 0 bits 7 and 6
1	left border	attr 1 (border)	latch 0 bits 5 and 4
2	left border		latch 0 bits 3 and 2
3	left border		latch 0 bits 1 and 0
4	left border		latch 1 bits 7 and 6
5	left border		latch 1 bits 5 and 4
6	left border	mask 0 (border)	latch 1 bits 3 and 2
7	left border	attr 0 (border)	latch 1 bits 1 and 0
8	left border	mask 1 (border)	latch 0 bits 7 and 6
9	left border	attr 1 (border)	latch 0 bits 5 and 4
10	left border		latch 0 bits 3 and 2
11	left border		latch 0 bits 1 and 0
12	left border		latch 1 bits 7 and 6
13	left border		latch 1 bits 5 and 4
14	left border	mask 0 (border)	latch 1 bits 3 and 2
15	left border	attr 0 (border)	latch 1 bits 1 and 0
16	left border	mask 1 (border)	latch 0 bits 7 and 6
17	left border	attr 1 (border)	latch 0 bits 5 and 4
18	left border		latch 0 bits 3 and 2
19	left border		latch 0 bits 1 and 0
20	left border		latch 1 bits 7 and 6
21	left border		latch 1 bits 5 and 4
22	left border	mask 0 (vram)	latch 1 bits 3 and 2
23	left border	attr 0 (vram)	latch 1 bits 1 and 0
24	screen	mask 1 (vram)	latch 0 bits 7 and 6
25	screen	attr 1 (vram)	latch 0 bits 5 and 4
26	screen	(contend)	latch 0 bits 3 and 2
27	screen	(contend)	latch 0 bits 1 and 0
28	screen		latch 1 bits 7 and 6
29	screen		latch 1 bits 5 and 4
30	screen	mask 0 (vram)	latch 1 bits 3 and 2
31	screen	attr 0 (vram)	latch 1 bits 1 and 0
32	screen	mask 1 (vram)	latch 0 bits 7 and 6
33	screen	attr 1 (vram)	latch 0 bits 5 and 4
34	screen	(contend)	latch 0 bits 3 and 2
35	screen	(contend)	latch 0 bits 1 and 0
36	screen		latch 1 bits 7 and 6
37	screen		latch 1 bits 5 and 4
38	screen	mask 0 (vram)	latch 1 bits 3 and 2
39	screen	attr 0 (vram)	latch 1 bits 1 and 0
40	screen	mask 1 (vram)	latch 0 bits 7 and 6
41	screen	attr 1 (vram)	latch 0 bits 5 and 4
42	screen	(contend)	latch 0 bits 3 and 2
43	screen	(contend)	latch 0 bits 1 and 0
44	screen		latch 1 bits 7 and 6
45	screen		latch 1 bits 5 and 4
46	screen	mask 0 (vram)	latch 1 bits 3 and 2
47	screen	attr 0 (vram)	latch 1 bits 1 and 0
48	screen	mask 1 (vram)	latch 0 bits 7 and 6
49	screen	attr 1 (vram)	latch 0 bits 5 and 4
50	screen	(contend)	latch 0 bits 3 and 2
51	screen	(contend)	latch 0 bits 1 and 0
52	screen		latch 1 bits 7 and 6
53	screen		latch 1 bits 5 and 4
54	screen	mask 0 (vram)	latch 1 bits 3 and 2
55	screen	attr 0 (vram)	latch 1 bits 1 and 0
56	screen	mask 1 (vram)	latch 0 bits 7 and 6
57	screen	attr 1 (vram)	latch 0 bits 5 and 4
58	screen	(contend)	latch 0 bits 3 and 2
59	screen	(contend)	latch 0 bits 1 and 0
60	screen		latch 1 bits 7 and 6
61	screen		latch 1 bits 5 and 4
62	screen	mask 0 (vram)	latch 1 bits 3 and 2
63	screen	attr 0 (vram)	latch 1 bits 1 and 0
64	screen	mask 1 (vram)	latch 0 bits 7 and 6
65	screen	attr 1 (vram)	latch 0 bits 5 and 4
66	screen	(contend)	latch 0 bits 3 and 2
67	screen	(contend)	latch 0 bits 1 and 0
68	screen		latch 1 bits 7 and 6
69	screen		latch 1 bits 5 and 4
70	screen	mask 0 (vram)	latch 1 bits 3 and 2
71	screen	attr 0 (vram)	latch 1 bits 1 and 0
72	screen	mask 1 (vram)	latch 0 bits 7 and 6
73	screen	attr 1 (vram)	latch 0 bits 5 and 4
74	screen	(contend)	latch 0 bits 3 and 2
75	screen	(contend)	latch 0 bits 1 and 0
76	screen		latch 1 bits 7 and 6
77	screen		latch 1 bits 5 and 4
78	screen	mask 0 (vram)	latch 1 bits 3 and 2
79	screen	attr 0 (vram)	latch 1 bits 1 and 0
80	screen	mask 1 (vram)	latch 0 bits 7 and 6
81	screen	attr 1 (vram)	latch 0 bits 5 and 4
82	screen	(contend)	latch 0 bits 3 and 2
83	screen	(contend)	latch 0 bits 1 and 0
84	screen		latch 1 bits 7 and 6
85	screen		latch 1 bits 5 and 4
86	screen	mask 0 (vram)	latch 1 bits 3 and 2
87	screen	attr 0 (vram)	latch 1 bits 1 and 0
88	screen	mask 1 (vram)	latch 0 bits 7 and 6
89	screen	attr 1 (vram)	latch 0 bits 5 and 4
90	screen	(contend)	latch 0 bits 3 and 2
91	screen	(contend)	latch 0 bits 1 and 0
92	screen		latch 1 bits 7 and 6
93	screen		latch 1 bits 5 and 4
94	screen	mask 0 (vram)	latch 1 bits 3 and 2
95	screen	attr 0 (vram)	latch 1 bits 1 and 0
96	screen	mask 1 (vram)	latch 0 bits 7 and 6
97	screen	attr 1 (vram)	latch 0 bits 5 and 4
98	screen	(contend)	latch 0 bits 3 and 2
99	screen	(contend)	latch 0 bits 1 and 0
100	screen		latch 1 bits 7 and 6
101	screen		latch 1 bits 5 and 4
102	screen	mask 0 (vram)	latch 1 bits 3 and 2
103	screen	attr 0 (vram)	latch 1 bits 1 and 0
104	screen	mask 1 (vram)	latch 0 bits 7 and 6
105	screen	attr 1 (vram)	latch 0 bits 5 and 4
106	screen	(contend)	latch 0 bits 3 and 2
107	screen	(contend)	latch 0 bits 1 and 0
108	screen		latch 1 bits 7 and 6
109	screen		latch 1 bits 5 and 4
110	screen	mask 0 (vram)	latch 1 bits 3 and 2
111	screen	attr 0 (vram)	latch 1 bits 1 and 0
112	screen	mask 1 (vram)	latch 0 bits 7 and 6
113	screen	attr 1 (vram)	latch 0 bits 5 and 4
114	screen	(contend)	latch 0 bits 3 and 2
115	screen	(contend)	latch 0 bits 1 and 0
116	screen		latch 1 bits 7 and 6
117	screen		latch 1 bits 5 and 4
118	screen	mask 0 (vram)	latch 1 bits 3 and 2
119	screen	attr 0 (vram)	latch 1 bits 1 and 0
120	screen	mask 1 (vram)	latch 0 bits 7 and 6
121	screen	attr 1 (vram)	latch 0 bits 5 and 4
122	screen	(contend)	latch 0 bits 3 and 2
123	screen	(contend)	latch 0 bits 1 and 0
124	screen		latch 1 bits 7 and 6
125	screen		latch 1 bits 5 and 4
126	screen	mask 0 (vram)	latch 1 bits 3 and 2
127	screen	attr 0 (vram)	latch 1 bits 1 and 0
128	screen	mask 1 (vram)	latch 0 bits 7 and 6
129	screen	attr 1 (vram)	latch 0 bits 5 and 4
130	screen	(contend)	latch 0 bits 3 and 2
131	screen	(contend)	latch 0 bits 1 and 0
132	screen		latch 1 bits 7 and 6
133	screen		latch 1 bits 5 and 4
134	screen	mask 0 (vram)	latch 1 bits 3 and 2
135	screen	attr 0 (vram)	latch 1 bits 1 and 0
136	screen	mask 1 (vram)	latch 0 bits 7 and 6
137	screen	attr 1 (vram)	latch 0 bits 5 and 4
138	screen	(contend)	latch 0 bits 3 and 2
139	screen	(contend)	latch 0 bits 1 and 0
140	screen		latch 1 bits 7 and 6
141	screen		latch 1 bits 5 and 4
142	screen	mask 0 (vram)	latch 1 bits 3 and 2
143	screen	attr 0 (vram)	latch 1 bits 1 and 0
144	screen	mask 1 (vram)	latch 0 bits 7 and 6
145	screen	attr 1 (vram)	latch 0 bits 5 and 4
146	screen	(contend)	latch 0 bits 3 and 2
147	screen	(contend)	latch 0 bits 1 and 0
148	screen		latch 1 bits 7 and 6
149	screen		latch 1 bits 5 and 4
150	screen	mask 0 (border)	latch 1 bits 3 and 2
151	screen	attr 0 (border)	latch 1 bits 1 and 0
152	right border	mask 1 (border)	latch 0 bits 7 and 6
153	right border	attr 1 (border)	latch 0 bits 5 and 4
154	right border		latch 0 bits 3 and 2
155	right border		latch 0 bits 1 and 0
156	right border		latch 1 bits 7 and 6
157	right border		latch 1 bits 5 and 4
158	right border	mask 0 (border)	latch 1 bits 3 and 2
159	right border	attr 0 (border)	latch 1 bits 1 and 0
160	right border	mask 1 (border)	latch 0 bits 7 and 6
161	right border	attr 1 (border)	latch 0 bits 5 and 4
162	right border		latch 0 bits 3 and 2
163	right border		latch 0 bits 1 and 0
164	right border		latch 1 bits 7 and 6
165	right border		latch 1 bits 5 and 4
166	right border	mask 0 (border)	latch 1 bits 3 and 2
167	right border	attr 0 (border)	latch 1 bits 1 and 0
168	right border	mask 1 (border)	latch 0 bits 7 and 6
169	right border	attr 1 (border)	latch 0 bits 5 and 4
170	right border		latch 0 bits 3 and 2
171	right border		latch 0 bits 1 and 0
172	right border		latch 1 bits 7 and 6
173	right border		latch 1 bits 5 and 4
174	right border	mask 0 (border)	latch 1 bits 3 and 2
175	right border	attr 0 (border)	latch 1 bits 1 and 0
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