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Reverse-engineered jumper settings for bit-design PCELC V1.3 EGA + ELD graphics card

TL;DR - how to set it up as regular EGA

Set jumpers as follows:

  • J4: Unset
  • J5: 2-3
  • J6: Unset
  • J7: 1-2
  • J8: 1-2 for EGA monitor, 2-3 for CGA/MDA monitor

All other jumpers are only relevant for the ELD output and can be ignored.

Set switches on back of card/bracket:

Set switches 6 to 8 to "ON"/down.

Set switches 1 to 5 as follows:

U = up, D = down

Monitor type Switches
Monochrome (MDA) U D D D U
CGA D D D D D
EGA D U D D U

Dip switch settings

0 means switch is down, 1 means up. This is reversed from the label on the switch which has ON in the down position, but when the switch is down it connects to GND and thus pulls the pin low. We are going with what the CPU sees, hence 1 means up.

Bank 1 (8 switches, accessible via bracket)

  • 1-4: Monitor type (see below)
  • 5: Initial video mode (see below)
  • 6: Set card as secondary display
  • 7: Enable CGA/MDA software emulation
  • 8: ??? (TODO) - should be off

Switches 1-4

These switches choose the monitor type, and possibly some other configuration. There is a bug in the BIOS which will make it hang on boot if an invalid switch combination is set, without any beeps or error indication.

Switches Active output Monitor type
0 0 0 0 DB-9 CGA monitor
1 0 0 0 DB-9 monochrome (MDA) monitor
0 1 0 0 DB-9 EGA monitor
1 1 0 0 DB-9 EGA monitor
0 0 1 0 ELD ?? (B)
1 0 1 0 ELD ?? (A)
0 1 1 0 ELD ?? (B)
1 1 1 0 ELD ?? (A)
0 0 0 1 ELD ?? (B)

Switch 5

This switch chooses between two available video modes, which decides the resolution and font size. (only the initial video mode, software running on the computer can switch to different modes).

What exactly the two modes are depends on three factors:

  • Primary or secondary card? (switch 6)
  • Chosen monitor type (switches 1-4)
  • Another color card present in the system? (i.e. a CGA card)

The card acts as primary if switch 6 is off, and as secondary otherwise. There are only two categories of monitor type:

  • Monitor type A: MDA, EGA, ELD configurations marked with (A)
  • Monitor type B: CGA, ELD configurations marked with (B)

Card is primary card (switch 6 off)

Switch 5 Monitor type 2nd color card present Video mode Equivalent IBM EGA switch settings
0 A no 80x25 text, 8x8 font, mode 3 on on on off
1 A no 80x25 text, 8x14 font, mode 3 off on on off
0 B no 80x25 text, 8x8 font, mode 3 off off off on
1 B no 40x25 text, 8x8 font, mode 1 on off off on
0 A yes ? off on off on
1 A yes ? off on off on
0 B yes ? off on off on
1 B yes ? on on off on

Card is secondary card (switch 6 on)

Switch 5 Monitor type 2nd color card present Video mode Equivalent IBM EGA switch settings
0 A no ? on off on on
1 A no ? off off on on
0 B no ? off on on on
1 B no ? on on on on
0 A yes ? off off on off
1 A yes ? off off on off
0 B yes ? off off on off
1 B yes ? on off off on

Bank 2 (4 switches, not externally accessible)

These switches control the hsync delay for the ELD output. See description of jumper J11 for more info.

Jumper settings

J1

Exact purpose unknown. It allows inverting the clock signal for the LS164 (see J11 for more about that component). Was set to 1-2 when I got the card.

  • 1-2: normal clock
  • 2-3: inverted clock

J2

Exact purpose unknown. It allows inverting the clock signal for the AS04 (flip-flop used to buffer red and hsync signals before sending to ELD output). Since the hsync signal is coming from the LS164 (see J11), I would assume that J1 & J2 need to be set the same way for things to work properly, but it's hard to say. Was set to 1-2 when I got the card.

  • 1-2: normal clock
  • 2-3: inverted clock

J3

Exact purpose unknown. Clock is the same as the one chosen via J2, so it might already be inverted or not depending on how J2 is set. My only guess is that different types of display maybe needed the clock inverted or not? Was set to 2-3 when I got the card.

  • 1-2: normal clock to ELD output
  • 2-3: inverted clock to ELD output

J4

  • Unset: EGA register IO address space at 3xx (default)
  • Set: EGA register IO address space at 2xx

2xx is not supported by the BIOS usually. Presumably this setting would allow running this card in parallel with another video card and directly interacting with the 435/436 via IO commands, if the BIOS ROM is also disabled (J6).

Was not set when I got the card.

J5

Seems to allow using larger BIOS ROMs, with up to 32k instead of 16k. Was set to 2-3 when I got the card.

  • 1-2: 16k address space for BIOS ROM (standard operation of C436)
  • 2-3: 32k address space for BIOS ROM.

The way this works is that 2-3 pulls ADDR14 low on C436 so that it still considers addresses that have that bit set as ROM addresses. The chip itself only enables ROM access for addresses in the range C0000-C3FFF, which is only 16kB. By pulling the address pin low, addresses in range C4000-C4FFF are still seen as C0000-C3FFF by the C436 and thus ROM access is enabled, but since the ROM itself is directly connected to the address lines it sees the actual address. Thus, reading out another 16kB is made possible.

J6

  • Unset: Enable BIOS ROM
  • Set: Disable BIOS ROM

When set, it pulls ADDR14 on C436 high, so that it never sees a valid ROM address. It's looking for addresses in the range C0000-C3FFF, and with bit 14 set we get to C4000 which is outside that range.

Was not set when I got the card.

J7

It seems clear what this is doing, but I'm not sure why you'd want this? Maybe for compatibility reasons with old software? Did the original IBM EGA/CGA behave this way?

Was set to 1-2 when I got the card.

  • 1-2: full video memory address space is accessible
  • 2-3: remap video memory address ranges 0000-3FFF and 8000-8FFFF to 4000-4FFF and C000-CFFF, respectively. 4000-4FFF and C000-CFFF remain unchanged, so that they mirror the remapped address spaces.

J8

This allows connecting the secondary red pin of the DB9 output to either ground or to the secondary red (EGA mode) signal of the C435 chip (with buffering by a bus driver in-between). That means it must be for choosing the monitor type, since MDA/CGA expect that pin to be ground whereas EGA carries a signal there.

The same configuration is not necessary for other pins because the other EGA-specific pins (secondary green, secondary blue) either also carry signals in MDA/CGA, or are not connected.

This was set to 1-2 when I got the card.

  • 1-2: EGA monitor
  • 2-3: CGA/MDA/Hercules monitor

J9

Not clear what exactly the purpose of this is, also see J10.

Was set to 2-3 when I got the card.

Chooses output pins 8+9 on ELD connector:

  • 1-2: pins 4+9 on CN4
  • 2-3: 12v from system bus

J10

Doesn't seem to be fully connected? There's a missing component (nothing soldered in) that the trace goes to. If the component was present, it would go to pins 6+11 on ELD output. So maybe there was some unfinished feature involving the CN4 connector, together with J9? Or maybe this is a leftover from development (i.e. for debugging purposes).

Was not set when I got the card.

  • 1-2: GND from system bus
  • 2-3: pins 3+10 on CN4

J11

The hsync signal for the ELD output can be delayed by up to 7 clock cycles, thanks to the LS164 shift register and LS151 input selector. The delay is configured by setting the input choice pins (A, B, & C) on LS151. The C pin is controlled either by this jumper, or by software when J12 is set.

The A & B pins are configured via the dip switches on DIP2 (the bank of 4 switches). Whether Switches 1 & 2 or 3 & 4 are controlling these pins is determined by software (FCOUT0 of C436, controlled via feature control register).

It's hard to say what exactly this delay is used for, and why there are two sets of switches - perhaps some of the monitors that this card can drive have support for multiple resolutions, and this allows having preset settings for two different resolutions?

Was set to 2-3 when I got the card.

  • 1-2: Dip2 delay selection range 4-7
  • 2-3: Dip2 delay selection range 0-3

J12

  • Unset: Dip2 delay selection controlled by J11
  • Set: Dip2 delay selection controlled by software (FCOUT1 of C436, controlled via feature control register). See J11 for more info

Was not set when I got the card.

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