TIM5 Test.c

/*
 * This file is part of the libopencm3 project.
 *
 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
 * Copyright (C) 2011 Damjan Marion <damjan.marion@gmail.com>
 * Copyright (C) 2011 Mark Panajotovic <marko@electrontube.org>
 * Copyright (C) 2017 Piotr Esden-Tempski <piotr@esden.net>
 *
 * This library is free software: you can redistribute it and/or modify
 * it under the terms of the GNU Lesser General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public License
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/gpio.h>
#include <libopencm3/stm32/timer.h>
#include <libopencm3/cm3/nvic.h>


#define PWM_INPUT_IRQ_PRIO 2

volatile uint32_t period = 0;
volatile uint32_t duty = 0;


void tim5_isr(void) {
  uint32_t irq_flags = TIM5_SR;
  if ((TIM5_SR & TIM_SR_CC1IF) != 0) {
	timer_clear_flag(TIM5, TIM_SR_CC1IF);
	period = TIM5_CCR2;
  }
  if ((TIM5_SR & TIM_SR_CC2IF) != 0) {
    timer_clear_flag(TIM5, TIM_SR_CC2IF);
	duty = TIM5_CCR2;
  }
  if ((TIM5_SR & TIM_SR_UIF) != 0) {
    timer_clear_flag(TIM5, TIM_SR_UIF);
    // FIXME clear overflow interrupt but what else ?
  }
}

/* Set STM32 to 168 MHz. */
static void clock_setup(void)
{
	rcc_clock_setup_hse_3v3(&rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_168MHZ]);

	/* Enable GPIOA clock. */
	rcc_periph_clock_enable(RCC_GPIOA);
	//rcc_periph_clock_enable(RCC_TIM5);
}

static void gpio_setup(void)
{
	/* Set GPIO8 (in GPIO port A) to 'output push-pull'. */
	gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO8);

	gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO0);

	//gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO3);
}

#define numpoints 1024
uint32_t cnt[numpoints] = {0};
uint16_t ptr = 0;

int main(void)
{
	int i;

	clock_setup();
	gpio_setup();

	/* Set two LEDs for wigwag effect when toggling. */
	gpio_set(GPIOA, GPIO8);

	rcc_periph_clock_enable(RCC_TIM5);
	//rcc_periph_clock_enable(RCC_AFIO);
	
	timer_reset(TIM5);
	timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
	timer_set_period(TIM5, 0xFFFFFFFF);
	timer_set_prescaler(TIM5, 0);
	timer_enable_counter(TIM5);

	/* GPIO configuration as input capture for timer */
	//gpio_setup_pin_af(PWM_INPUT1_GPIO_PORT, PWM_INPUT1_GPIO_PIN, PWM_INPUT1_GPIO_AF, FALSE);
	gpio_set_af(GPIOA,GPIO_AF2,GPIO0);
	//AFIO_MAPR |= GPIO_AF2;
	
	/** TIM configuration: Input Capture mode
	 *  Two IC signals are mapped to the same TI input
	 */
	timer_ic_set_input(TIM5, TIM_IC1, TIM_IC_IN_TI1);
	timer_ic_set_input(TIM5, TIM_IC2, TIM_IC_IN_TI1);

	timer_ic_set_polarity(TIM5, TIM_IC1, TIM_IC_FALLING);
	timer_ic_set_polarity(TIM5, TIM_IC2, TIM_IC_RISING);

	/* Select the valid trigger input */
	timer_slave_set_trigger(TIM5, TIM_SMCR_TS_TI1F_ED);
	/* Configure the slave mode controller in reset mode */
	timer_slave_set_mode(TIM5, TIM_SMCR_SMS_RM);

	/* Enable timer Interrupt(s). */
	nvic_set_priority(NVIC_TIM5_IRQ, 0);
	nvic_enable_irq(NVIC_TIM5_IRQ);

	//nvic_set_priority(PWM_INPUT1_IRQ2, PWM_INPUT_IRQ_PRIO);
	//nvic_enable_irq(PWM_INPUT1_IRQ2);


	/* Enable the Capture/Compare and Update interrupt requests. */
	timer_enable_irq(TIM5, (TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_UIE));

	/* Enable capture channel. */
	timer_ic_enable(TIM5, TIM_IC1);
	timer_ic_enable(TIM5, TIM_IC2);

	/* Blink the LEDs (PA8) on the board. */
	while (1) {
		/* Toggle LEDs. */
		gpio_toggle(GPIOA, GPIO8);
		for (i = 0; i < 6000000; i++) { /* Wait a bit. */
			__asm__("nop");
			cnt[ptr] = timer_get_counter(TIM5);
			if (ptr++ >= numpoints)
				ptr = 0;
			period = TIM5_CCR1;
		}
	}

	return 0;
}