Latch4bit.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Latch4bit is
	Port (	D : in STD_LOGIC_VECTOR(3 downto 0);
			E : in STD_LOGIC;
			Q : out STD_LOGIC_VECTOR(3 downto 0));
end Latch4bit;

architecture Behavioral of Latch4bit is
begin
	process (E, D)
	begin
		if (E = '1') then
			Q <= D;
		end if;
	end process;
end Behavioral;