Counter2bit.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter2bit is
	Port (	Up, CLR : in STD_LOGIC;
			Q : out STD_LOGIC_VECTOR(1 downto 0));
end Counter2bit;

architecture Behavioral of Counter2bit is
signal tmp: std_logic_vector(1 downto 0);
begin
	process (Up, CLR)
	begin
		if (CLR='1') then
			tmp <= "00";
		elsif (Up'event and Up='1') then
			tmp <= tmp + 1;
		end if;
	end process;
	Q <= tmp;
end Behavioral;