Mux4to1.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux4to1 is
	Port (	S : in STD_LOGIC;
			A : in STD_LOGIC_VECTOR(3 downto 0);
			B : in STD_LOGIC_VECTOR(3 downto 0);
			Y : out STD_LOGIC_VECTOR(3 downto 0));
end Mux4to1;

architecture Behavioral of Mux4to1 is
begin
	Mux1: process (S, A, B)
	begin
		if (S = '0') then
			Y <= A;
		else
			Y <= B;
		end if;
	end process;
end Behavioral;