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linuxgemini/libnfc-brcm.conf

Created July 1, 2020 10:57
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Angler libnfc configurations
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libnfc-brcm.conf
###################### Start of libnfc-brcm.conf #######################
###############################################################################
# Application options
APPL_TRACE_LEVEL=0x01
PROTOCOL_TRACE_LEVEL=0x00000000
###############################################################################
# performance measurement
# Change this setting to control how often USERIAL log the performance (throughput)
# data on read/write/poll
# defailt is to log performance dara for every 100 read or write
#REPORT_PERFORMANCE_MEASURE=100
###############################################################################
# File used for NFA storage
NFA_STORAGE="/data/nfc"
###############################################################################
# Snooze Mode Settings
#
# By default snooze mode is enabled. Set SNOOZE_MODE_CFG byte[0] to 0
# to disable.
#
# If SNOOZE_MODE_CFG is not provided, the default settings are used:
# They are as follows:
# 8 Sleep Mode (0=Disabled 1=UART 8=SPI/I2C)
# 0 Idle Threshold Host
# 0 Idle Threshold HC
# 0 NFC Wake active mode (0=ActiveLow 1=ActiveHigh)
# 1 Host Wake active mode (0=ActiveLow 1=ActiveHigh)
#
#SNOOZE_MODE_CFG={08:00:00:00:01}
###############################################################################
# Insert a delay in milliseconds after NFC_WAKE and before write to NFCC
#NFC_WAKE_DELAY=20
###############################################################################
# Various Delay settings (in ms) used in USERIAL
# POWER_ON_DELAY
# Delay after turning on chip, before writing to transport (default 300)
# PRE_POWER_OFF_DELAY
# Delay after deasserting NFC-Wake before turn off chip (default 0)
# POST_POWER_OFF_DELAY
# Delay after turning off chip, before USERIAL_close returns (default 0)
#
#POWER_ON_DELAY=300
#PRE_POWER_OFF_DELAY=0
#POST_POWER_OFF_DELAY=0
###############################################################################
# Maximum time (ms) to wait for RESET NTF after setting REG_PU to high
# The default is 1000.
#NFCC_ENABLE_TIMEOUT=0
###############################################################################
# LPTD mode configuration
# byte[0] is the length of the remaining bytes in this value
# if set to 0, LPTD params will NOT be sent to NFCC (i.e. disabled).
# byte[1] is the param id it should be set to B9.
# byte[2] is the length of the LPTD parameters
# byte[3] indicates if LPTD is enabled
# if set to 0, LPTD will be disabled (parameters will still be sent).
# byte[4-n] are the LPTD parameters.
# By default, LPTD is enabled and default settings are used.
# See nfc_hal_dm_cfg.c for defaults
#LPTD_CFG={23:B9:21:01:02:FF:FF:04:A0:0F:40:00:80:02:02:10:00:00:00:31:0C:30:00:00:00:00:00:00:00:00:00:00:00:00:00:00}
###############################################################################
# Startup Configuration (100 bytes maximum)
#
# For the 0xCA parameter, byte[9] (marked by 'AA') is for UICC0, and byte[10] (marked by BB) is
# for UICC1. The values are defined as:
# 0 : UICCx only supports ISO_DEP in low power mode.
# 2 : UICCx only supports Mifare in low power mode.
# 3 : UICCx supports both ISO_DEP and Mifare in low power mode.
#
# AA BB
#NFA_DM_START_UP_CFG={1F:CB:01:01:A5:01:01:CA:14:00:00:00:00:06:E8:03:00:00:00:00:00:00:00:00:00:00:00:00:00:80:01:01}
###############################################################################
# Startup Vendor Specific Configuration (100 bytes maximum);
# byte[0] TLV total len = 0x5
# byte[1] NCI_MTS_CMD|NCI_GID_PROP = 0x2f
# byte[2] NCI_MSG_FRAME_LOG = 0x9
# byte[3] 2
# byte[4] 0=turn off RF frame logging; 1=turn on
# byte[5] 0=turn off SWP frame logging; 1=turn on
# NFA_DM_START_UP_VSC_CFG={05:2F:09:02:01:01}
###############################################################################
# Antenna Configuration - This data is used when setting 0xC8 config item
# at startup (before discovery is started). If not used, no value is sent.
#
# The settings for this value are documented here:
# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
# Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
# This document is maintained by Paul Forshaw.
#
# The values marked as ?? should be tweaked per antenna or customer/app:
# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
# array[0] = 0x20 is length of the payload from array[1] to the end
# array[1] = 0xC8 is PREINIT_DSP_CFG
#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
###############################################################################
# Configure crystal frequency when internal LPO can't detect the frequency.
#XTAL_FREQUENCY=0
###############################################################################
# Configure the default Destination Gate used by HCI (the default is 4, which
# is the ETSI loopback gate.
NFA_HCI_DEFAULT_DEST_GATE=0xF0
###############################################################################
# Configure the single default SE to use. The default is to use the first
# SE that is detected by the stack. This value might be used when the phone
# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
# one of them (e.g. 0xF4).
#ACTIVE_SE=0xF3
###############################################################################
# Configure the default NfcA/IsoDep techology and protocol route. Can be
# either a secure element (e.g. 0xF4) or the host (0x00)
#DEFAULT_ISODEP_ROUTE=0x00
###############################################################################
# Configure the NFC Extras to open and use a static pipe. If the value is
# not set or set to 0, then the default is use a dynamic pipe based on a
# destination gate (see NFA_HCI_DEFAULT_DEST_GATE). Note there is a value
# for each UICC (where F3="UICC0" and F4="UICC1")
#NFA_HCI_STATIC_PIPE_ID_F3=0x70
#NFA_HCI_STATIC_PIPE_ID_01=0x19
NFA_HCI_STATIC_PIPE_ID_C0=0x19
###############################################################################
# When disconnecting from Oberthur secure element, perform a warm-reset of
# the secure element to deselect the applet.
# The default hex value of the command is 0x3. If this variable is undefined,
# then this feature is not used.
#OBERTHUR_WARM_RESET_COMMAND=0x03
###############################################################################
# Force UICC to only listen to the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F
UICC_LISTEN_TECH_MASK=0x07
###############################################################################
# Force HOST listen feature enable or disable.
# 0: Disable
# 1: Enable
HOST_LISTEN_ENABLE=0x01
###############################################################################
# Enabling/Disabling Forward functionality
# Disable 0x00
# Enable 0x01
NXP_FWD_FUNCTIONALITY_ENABLE=0x00
###############################################################################
# Allow UICC to be powered off if there is no traffic.
# Timeout is in ms. If set to 0, then UICC will not be powered off.
#UICC_IDLE_TIMEOUT=30000
UICC_IDLE_TIMEOUT=0
###############################################################################
# AID for Empty Select command
# If specified, this AID will be substituted when an Empty SELECT command is
# detected. The first byte is the length of the AID. Maximum length is 16.
AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00}
###############################################################################
# Maximum Number of Credits to be allowed by the NFCC
# This value overrides what the NFCC specifices allowing the host to have
# the control to work-around transport limitations. If this value does
# not exist or is set to 0, the NFCC will provide the number of credits.
MAX_RF_DATA_CREDITS=1
###############################################################################
# This setting allows you to disable registering the T4t Virtual SE that causes
# the NFCC to send PPSE requests to the DH.
# The default setting is enabled (i.e. T4t Virtual SE is registered).
#REGISTER_VIRTUAL_SE=1
###############################################################################
# When screen is turned off, specify the desired power state of the controller.
# 0: power-off-sleep state; DEFAULT
# 1: full-power state
# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used)
SCREEN_OFF_POWER_STATE=1
###############################################################################
# Firmware patch file
# If the value is not set then patch download is disabled.
#FW_PATCH="/vendor/firmware/bcm2079x_firmware.ncd"
###############################################################################
# Firmware pre-patch file (sent before the above patch file)
# If the value is not set then pre-patch is not used.
#FW_PRE_PATCH="/vendor/firmware/bcm2079x_pre_firmware.ncd"
###############################################################################
# Firmware patch format
# 1 = HCD
# 2 = NCD (default)
#NFA_CONFIG_FORMAT=2
###############################################################################
# SPD Debug mode
# If set to 1, any failure of downloading a patch will trigger a hard-stop
#SPD_DEBUG=0
###############################################################################
# SPD Max Retry Count
# The number of attempts to download a patch before giving up (defualt is 3).
# Note, this resets after a power-cycle.
#SPD_MAX_RETRY_COUNT=3
###############################################################################
# transport driver
#
# TRANSPORT_DRIVER=<driver>
#
# where <driver> can be, for example:
# "/dev/ttyS" (UART)
# "/dev/bcmi2cnfc" (I2C)
# "hwtun" (HW Tunnel)
# "/dev/bcmspinfc" (SPI)
# "/dev/btusb0" (BT USB)
#TRANSPORT_DRIVER="/dev/bcm2079x-i2c"
###############################################################################
# power control driver
# Specify a kernel driver that support ioctl commands to control NFC_EN and
# NFC_WAKE gpio signals.
#
# POWER_CONTRL_DRIVER=<driver>
# where <driver> can be, for example:
# "/dev/nfcpower"
# "/dev/bcmi2cnfc" (I2C)
# "/dev/bcmspinfc" (SPI)
# i2c and spi driver may be used to control NFC_EN and NFC_WAKE signal
#POWER_CONTROL_DRIVER="/dev/bcm2079x-i2c"
###############################################################################
# I2C transport driver options
# Mako does not support 10-bit I2C addresses
# Revert to 7-bit address
#BCMI2CNFC_ADDRESS=0x77
###############################################################################
# I2C transport driver try to read multiple packets in read() if data is available
# remove the comment below to enable this feature
#READ_MULTIPLE_PACKETS=1
###############################################################################
# SPI transport driver options
#SPI_NEGOTIATION={0A:F0:00:01:00:00:00:FF:FF:00:00}
###############################################################################
# UART transport driver options
#
# PORT=1,2,3,...
# BAUD=115200, 19200, 9600, 4800,
# DATABITS=8, 7, 6, 5
# PARITY="even" | "odd" | "none"
# STOPBITS="0" | "1" | "1.5" | "2"
#UART_PORT=2
#UART_BAUD=115200
#UART_DATABITS=8
#UART_PARITY="none"
#UART_STOPBITS="1"
###############################################################################
# Insert a delay in microseconds per byte after a write to NFCC.
# after writing a block of data to the NFCC, delay this an amopunt of time before
# writing next block of data. the delay is calculated as below
# NFC_WRITE_DELAY * (number of byte written) / 1000 milliseconds
# e.g. after 259 bytes is written, delay (259 * 20 / 1000) 5 ms before next write
#NFC_WRITE_DELAY=20
###############################################################################
# Maximum Number of Credits to be allowed by the NFCC
# This value overrides what the NFCC specifices allowing the host to have
# the control to work-around transport limitations. If this value does
# not exist or is set to 0, the NFCC will provide the number of credits.
MAX_RF_DATA_CREDITS=1
###############################################################################
# Default poll duration (in ms)
# The defualt is 500ms if not set (see nfc_target.h)
#NFA_DM_DISC_DURATION_POLL=333
###############################################################################
# Antenna Configuration - This data is used when setting 0xC8 config item
# at startup (before discovery is started). If not used, no value is sent.
#
# The settings for this value are documented here:
# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
# Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
# This document is maintained by Paul Forshaw.
#
# The values marked as ?? should be tweaked per antenna or customer/app:
# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
# array[0] = 0x20 is length of the payload from array[1] to the end
# array[1] = 0xC8 is PREINIT_DSP_CFG
#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
###############################################################################
# Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1.
# 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
# 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
# 2 NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate
# 3 NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0
# 4 NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3
#PRESENCE_CHECK_ALGORITHM=0
PRESENCE_CHECK_ALGORITHM=1
###############################################################################
# Force tag polling for the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B |
# NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 |
# NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO |
# NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE.
#
# Notable bits:
# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */
# NFA_TECHNOLOGY_MASK_B 0x02 /* NFC Technology B */
# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */
# NFA_TECHNOLOGY_MASK_ISO15693 0x08 /* Proprietary Technology */
# NFA_TECHNOLOGY_MASK_KOVIO 0x20 /* Proprietary Technology */
# NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */
# NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */
POLLING_TECH_MASK=0xEF
###############################################################################
# Force P2P to only listen for the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F |
# NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE
#
# Notable bits:
# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */
# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */
# NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */
# NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */
P2P_LISTEN_TECH_MASK=0xC5
PRESERVE_STORAGE=0x01
###############################################################################
# Override the stack default for NFA_EE_MAX_EE_SUPPORTED set in nfc_target.h.
# The value is set to 3 by default as it assumes we will discover 0xF2,
# 0xF3, and 0xF4. If a platform will exclude and SE, this value can be reduced
# so that the stack will not wait any longer than necessary.
# Maximum EE supported number
# NXP PN547C2 0x02
# NXP PN65T 0x03
# NXP PN548C2 0x02
# NXP PN66T 0x03
NFA_MAX_EE_SUPPORTED=0x02
###############################################################################
# NCI Hal Module name
NCI_HAL_MODULE="nfc_nci"
##############################################################################
# Deactivate notification wait time out in seconds used in ETSI Reader mode
# 0 - Infinite wait
#NFA_DM_DISC_NTF_TIMEOUT=0
###############################################################################
# AID_MATCHING constants
# AID_MATCHING_EXACT_ONLY 0x00
# AID_MATCHING_EXACT_OR_PREFIX 0x01
# AID_MATCHING_PREFIX_ONLY 0x02
AID_MATCHING_MODE=0x01
###############################################################################
# Preferred Secure Element for Technology based routing
# eSE 0x01
# UICC 0x02
NXP_PRFD_TECH_SE=0x02
###############################################################################
# Default Secure Element route id
DEFAULT_OFFHOST_ROUTE=0x02
###############################################################################
# Vendor Specific Proprietary Protocol & Discovery Configuration
# Set to 0xFF if unsupported
# byte[0] NCI_PROTOCOL_18092_ACTIVE
# byte[1] NCI_PROTOCOL_B_PRIME
# byte[2] NCI_PROTOCOL_DUAL
# byte[3] NCI_PROTOCOL_15693
# byte[4] NCI_PROTOCOL_KOVIO
# byte[5] NCI_PROTOCOL_MIFARE
# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
NFA_PROPRIETARY_CFG={05:FF:FF:06:81:80:70:FF:FF}
###############################################################################
# Bail out mode
# If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
NFA_POLL_BAIL_OUT_MODE=0x01
Raw
libnfc-nci.conf
###############################################################################
# Application options
NFC_DEBUG_ENABLED=0
###############################################################################
# File used for NFA storage
NFA_STORAGE="/data/nfc"
###############################################################################
# Force UICC to only listen to the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F
UICC_LISTEN_TECH_MASK=0x07
###############################################################################
# Forcing HOST to listen for a selected protocol
# 0x00 : Disable Host Listen
# 0x01 : Enable Host to Listen (A) for ISO-DEP tech A
# 0x02 : Enable Host to Listen (B) for ISO-DEP tech B
# 0x04 : Enable Host to Listen (F) for T3T Tag Type Protocol tech F
# 0x07 : Enable Host to Listen (ABF)for ISO-DEP tech AB & T3T Tag Type Protocol tech F
HOST_LISTEN_TECH_MASK=0x07
###############################################################################
# AID for Empty Select command
# If specified, this AID will be substituted when an Empty SELECT command is
# detected. The first byte is the length of the AID. Maximum length is 16.
AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00}
###############################################################################
# When screen is turned off, specify the desired power state of the controller.
# 0: power-off-sleep state; DEFAULT
# 1: full-power state
# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used)
SCREEN_OFF_POWER_STATE=1
###############################################################################
# Force tag polling for the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B |
# NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 |
# NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO |
# NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE.
#
# Notable bits:
# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */
# NFA_TECHNOLOGY_MASK_B 0x02 /* NFC Technology B */
# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */
# NFA_TECHNOLOGY_MASK_ISO15693 0x08 /* Proprietary Technology */
# NFA_TECHNOLOGY_MASK_KOVIO 0x20 /* Proprietary Technology */
# NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */
# NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */
POLLING_TECH_MASK=0xEF
###############################################################################
# Force P2P to only listen for the following technology(s).
# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F |
# NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE
#
# Notable bits:
# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */
# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */
# NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */
# NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */
P2P_LISTEN_TECH_MASK=0xC5
PRESERVE_STORAGE=0x01
###############################################################################
# Override the stack default for NFA_EE_MAX_EE_SUPPORTED set in nfc_target.h.
# The value is set to 3 by default as it assumes we will discover 0xF2,
# 0xF3, and 0xF4. If a platform will exclude and SE, this value can be reduced
# so that the stack will not wait any longer than necessary.
# Maximum EE supported number
# NXP PN547C2 0x02
# NXP PN65T 0x03
# NXP PN548C2 0x02
# NXP PN66T 0x03
NFA_MAX_EE_SUPPORTED=0x02
###############################################################################
# AID_MATCHING constants
# AID_MATCHING_EXACT_ONLY 0x00
# AID_MATCHING_EXACT_OR_PREFIX 0x01
# AID_MATCHING_PREFIX_ONLY 0x02
AID_MATCHING_MODE=0x01
Raw
libnfc-nxp.conf
#FW_VERSION=ALMSL F 10.01.16
#DEVICE_MANUFACTURER=NXP
#DEVICE_MODEL=N
## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn54x)
## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn54x)
###############################################################################
# File location for Firmware
#FW_STORAGE="/vendor/firmware/libpn548ad_fw.so"
###############################################################################
# Chip type
# PN547C2 - 0x01
# PN65T - 0x02
# PN548C2 - 0x03
# PN66T - 0x04
NXP_NFC_CHIP=0x03
###############################################################################
# Application options
# Logging Levels
# NXPLOG_DEFAULT_LOGLEVEL 0x01
# ANDROID_LOG_DEBUG 0x03
# ANDROID_LOG_WARN 0x02
# ANDROID_LOG_ERROR 0x01
# ANDROID_LOG_SILENT 0x00
#
NXPLOG_EXTNS_LOGLEVEL=0x01
NXPLOG_NCIHAL_LOGLEVEL=0x01
NXPLOG_NCIX_LOGLEVEL=0x01
NXPLOG_NCIR_LOGLEVEL=0x01
NXPLOG_FWDNLD_LOGLEVEL=0x01
NXPLOG_TML_LOGLEVEL=0x01
#NFC_DEBUG_ENABLED=0
###############################################################################
# Nfc Device Node name
NXP_NFC_DEV_NODE="/dev/pn54x"
###############################################################################
# System clock source selection configuration
# CLK_SRC_XTAL - 0x01
# CLK_SRC_PLL - 0x02
NXP_SYS_CLK_SRC_SEL=0x02
###############################################################################
# System clock frequency selection configuration for PLL
# CLK_FREQ_13MHZ - 0x01
# CLK_FREQ_19_2MHZ - 0x02
# CLK_FREQ_24MHZ - 0x03
# CLK_FREQ_26MHZ - 0x04
# CLK_FREQ_38_4MHZ - 0x05
# CLK_FREQ_52MHZ - 0x06
NXP_SYS_CLK_FREQ_SEL=0x02
###############################################################################
# The timeout value to be used for clock request acknowledgment
# min value = 0x01 (1.33 ms) to max = 0x06 (2.98 ms)
NXP_SYS_CLOCK_TO_CFG=0x01
###############################################################################
# I2C fragmentation
# Disabled - 0x00
# Enabled - 0x01
NXP_I2C_FRAGMENTATION_ENABLED=0x00
###############################################################################
# Timeout in secs to get NFCEE Discover notification
NXP_DEFAULT_NFCEE_TIMEOUT=0x06
###############################################################################
# Enable SWP full power mode when phone is power off
NXP_SWP_FULL_PWR_ON=0x00
###############################################################################
# Default SE Options
# No secure element - 0x00
# eSE - 0x01
# UICC - 0x02
# Multi SE - 0x03
NXP_DEFAULT_SE=0x02
###############################################################################
# Set the default AID route Location :
# This settings will be used when application does not set this parameter
# Host - 0x00
# eSE - 0x01
# UICC - 0x02
DEFAULT_AID_ROUTE=0x02
###############################################################################
# Set the Mifare Desfire route Location :
# This settings will be used when application does not set this parameter
# Host - 0x00
# eSE - 0x01
# UICC - 0x02
DEFAULT_DESFIRE_ROUTE=0x02
###############################################################################
# Set the Mifare CLT route Location :
# This settings will be used when application does not set this parameter
# Host - 0x00
# eSE - 0x01
# UICC - 0x02
DEFAULT_MIFARE_CLT_ROUTE=0x02
###############################################################################
#Set the default Felica T3T System Code OffHost route Location :
# host 0x00
# UICC 0x02
# UICC2 0x03
DEFAULT_SYS_CODE_ROUTE=0x02
###############################################################################
# AID Matching platform options (for Lollipop)
# Supporting Prefix and Full match for both Host and Off-Host - 0x01
# Supporting Prefix match for Off-Host and Full match for Host - 0x02
AID_MATCHING_PLATFORM=0x01
###############################################################################
# Vzw Feature enable
# Disabled - 0x00
# Enabled - 0x01
VZW_FEATURE_ENABLE=0x01
###############################################################################
# Off-Host Payment CE when Screen is off or locked
# Disabled - 0x00
# Enabled - 0x01
NXP_CE_ROUTE_STRICT_DISABLE=0x01
###############################################################################
# SWP Reader feature
# Timeout in seconds
NXP_SWP_RD_START_TIMEOUT=0x0A
NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
###############################################################################
# Extension for Mifare reader enable
# Disabled - 0x00
# Enabled - 0x01
MIFARE_READER_ENABLE=0x01
###############################################################################
# Firmware file type
#.so file 0x01
#.bin file 0x02
NXP_FW_TYPE=0x01
###############################################################################
# SWP Switch timeout in milliseconds
# Allowed range is 0x00 to 0x3C (0 to 60 ms)
# No Timeout - 0x00
# 10 ms Timeout - 0x0A
NXP_SWP_SWITCH_TIMEOUT=0x0A
###############################################################################
# CHINA_TIANJIN_RF_SETTING
# Disabled - 0x00
# Enabled - 0x01
NXP_CHINA_TIANJIN_RF_ENABLED=0x01
###############################################################################
# NXP TVDD configurations settings
# Allow NFCC to configure the external TVDD
# Three configurations (0x01, 0x02 and 0x03) are supported
# Only one shall be selected (hardware dependancy)
# Config 1: VUP connected to VBAT
# Config 2: VUP connected to external 5V
# Config 3: TVDD connected to external 5V
NXP_EXT_TVDD_CFG=0x02
NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00}
NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 64, 01}
NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A}
###############################################################################
# NXP proprietary settings
NXP_ACT_PROP_EXTN={2F, 02, 00}
###############################################################################
# NFC forum profile settings
NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
###############################################################################
# NFCC Configuration Control
# Don't allow NFCC to manage RF Config 0x00
# Allow NFCC to manage RF Config 0x01
NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
###############################################################################
# Standby enable settings
# Disabled - 0x00
# Enabled - 0x01
NXP_CORE_STANDBY={2F, 00, 01, 01}
###############################################################################
# Mifare Classic Key settings
#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
# A0, 52, 06, D3, F7, D3, F7, D3, F7,
# A0, 53, 06, FF, FF, FF, FF, FF, FF,
# A0, 54, 06, 00, 00, 00, 00, 00, 00}
###############################################################################
# Core configuration RF Field notification filter
# Disabled - 0x00
# Enabled - 0x01
NXP_CORE_RF_FIELD={20, 02, 05, 01, A0, 62, 01, 01}
###############################################################################
# NXP RF ALMSL configuration settings for FW VERSION = 10.01.16
#
# A0, 0D, 03, 00, 47, 02 RF_CLIF_CFG_BOOT CLIF_ANA_AGC_REG
# A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG
# A0, 0D, 06, 00, FF, 05, 04, 06, 00 RF_CLIF_CFG_BOOT SMU_PMU_REG (0x40024010)
# A0, 0D, 03, 04, 43, 20 RF_CLIF_CFG_INITIATOR CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 06, 04, 35, F4, 01, F4, 01 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG
# A0, 0D, 06, 04, FF, 05, 00, 00, 00 RF_CLIF_CFG_INITIATOR SMU_PMU_REG (0x40024010)
# A0, 0D, 06, 06, 44, A3, 90, 03, 00 RF_CLIF_CFG_TARGET CLIF_ANA_RX_REG
# A0, 0D, 06, 06, 34, F7, 7F, 00, 10 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 06, 33, 07, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 06, 30, C8, 00, 64, 00 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 06, 2F, AF, 05, 80, 17 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 03, 06, 43, 20 RF_CLIF_CFG_TARGET CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 06, 41, 40 RF_CLIF_CFG_TARGET CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
# A0, 0D, 03, 06, 16, 00 RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 06, 15, 00 RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 06, 35, 00, 02, 00, 02 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG
# A0, 0D, 03, 06, 3F, 04 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG
# A0, 0D, 03, 06, 80, 03 RF_CLIF_CFG_TARGET CLIF_SPARE_REG
# A0, 0D, 06, 06, FF, 05, 00, 00, 00 RF_CLIF_CFG_TARGET SMU_PMU_REG (0x40024010)
# A0, 0D, 03, 07, 3F, 00 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG
# A0, 0D, 06, 18, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 18, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 1C, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 1C, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 20, 4A, 00, 00, 00, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 20, 42, 88, 10, FF, FF RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 20, 16, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 20, 15, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 22, 44, 22, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG
# A0, 0D, 06, 22, 2D, 50, 44, 0C, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 32, 03, 40, 3D RF_CLIF_CFG_BR_106_I_TXA CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 32, 16, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 32, 15, 01 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 32, 0D, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 32, 14, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 32, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 34, 34, 00, 00, EC, 03 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 34, 33, 0F, 01, 01, 70 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG0_REG
# A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
# A0, 0D, 06, 38, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 38, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 38, 16, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 38, 15, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 3A, 44, 26, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 3A, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 3A, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 3C, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 3C, 16, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 3C, 15, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 3E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 3E, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 3E, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 40, 42, F0, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 40, 0D, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 40, 14, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 40, 4A, 12, 07, 00, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 40, 16, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 40, 15, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 42, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 42, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 42, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 42, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG0_REG
# A0, 0D, 04, 46, 44, 26, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 44, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 44, 16, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 44, 15, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 4A, 44, 21, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 48, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 48, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 48, 16, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 48, 15, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 4E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 4C, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 4C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 4C, 16, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 4C, 15, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 52, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 52, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 50, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 50, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 50, 16, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 50, 15, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 54, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 54, 16, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 54, 15, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 5A, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 5A, 16, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 5A, 15, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 98, 2F, CF, 05, 80, 17 RF_CLIF_CFG_GTM_B CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 9A, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_FELICA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 30, 44, 12, 90, 03, 00 RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 6C, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 70, 2F, 8F, 05, 80, 12 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 70, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 03, 70, 2E, 40 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_CM_CONFIG_REG
# A0, 0D, 03, 70, 45, 30 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 70, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 74, 2F, 6F, 05, 80, 12 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 74, 30, D5, 00, 40, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 74, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 78, 2F, 3F, 07, 80, C1 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 78, 30, 50, 00, 10, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 78, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 7C, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 7C, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 80, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 80, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 80, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 84, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 84, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 84, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 88, 2F, B1, 05, 80, 17 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 88, 30, A8, 00, 64, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 88, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 03, 10, 43, 20 RF_CLIF_CFG_T_ACTIVE CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 06, 6A, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 6A, 16, 00 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 6A, 15, 01 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 8C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 8C, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 8C, 16, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 8C, 15, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 92, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 92, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 92, 16, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 92, 15, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 24, 41, 40 RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 28, 41, 40 RF_CLIF_CFG_TECHNO_T_TXB CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 8A, 41, 40 RF_CLIF_CFG_BR_212_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 90, 41, 40 RF_CLIF_CFG_BR_424_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 06, 0A, 30, C8, 00, 64, 00 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 0A, 2F, AF, 05, 80, 17 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 03, 0A, 48, 10 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
# A0, 0D, 06, 0A, 44, A3, 90, 03, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_RX_REG
# A0, 0D, 06, 0A, 34, 26, 65, E5, 03 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 0A, 33, 0F, 01, 00, 70 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG0_REG
#
# *** ALMSL FW VERSION = 10.01.16 ***
NXP_RF_CONF_BLK_1={
20, 02, F8, 20,
A0, 0D, 03, 00, 47, 02,
A0, 0D, 03, 00, 40, 03,
A0, 0D, 06, 00, FF, 05, 04, 06, 00,
A0, 0D, 03, 04, 43, 20,
A0, 0D, 06, 04, 35, F4, 01, F4, 01,
A0, 0D, 06, 04, FF, 05, 00, 00, 00,
A0, 0D, 06, 06, 44, A3, 90, 03, 00,
A0, 0D, 06, 06, 34, F7, 7F, 00, 10,
A0, 0D, 06, 06, 33, 07, 40, 00, 00,
A0, 0D, 06, 06, 30, C8, 00, 64, 00,
A0, 0D, 06, 06, 2F, AF, 05, 80, 17,
A0, 0D, 06, 06, 03, 00, 71, 00, 20,
A0, 0D, 03, 06, 43, 20,
A0, 0D, 06, 06, 42, 00, 00, F2, F2,
A0, 0D, 03, 06, 41, 40,
A0, 0D, 03, 06, 37, 08,
A0, 0D, 03, 06, 16, 00,
A0, 0D, 03, 06, 15, 00,
A0, 0D, 06, 06, 35, 00, 02, 00, 02,
A0, 0D, 03, 06, 3F, 04,
A0, 0D, 03, 06, 80, 03,
A0, 0D, 06, 06, FF, 05, 00, 00, 00,
A0, 0D, 03, 07, 3F, 00,
A0, 0D, 06, 18, 34, 00, 00, E1, 03,
A0, 0D, 06, 18, 33, 0F, 83, 00, 00,
A0, 0D, 06, 1C, 34, 00, 00, E1, 03,
A0, 0D, 06, 1C, 33, 0F, 83, 00, 00,
A0, 0D, 06, 20, 4A, 00, 00, 00, 00,
A0, 0D, 06, 20, 42, 88, 10, FF, FF,
A0, 0D, 03, 20, 16, 00,
A0, 0D, 03, 20, 15, 00,
A0, 0D, 04, 22, 44, 22, 00
}
NXP_RF_CONF_BLK_2={
20, 02, FB, 20,
A0, 0D, 06, 22, 2D, 50, 44, 0C, 00,
A0, 0D, 04, 32, 03, 40, 3D,
A0, 0D, 06, 32, 42, F8, 10, FF, FF,
A0, 0D, 03, 32, 16, 00,
A0, 0D, 03, 32, 15, 01,
A0, 0D, 03, 32, 0D, 22,
A0, 0D, 03, 32, 14, 22,
A0, 0D, 06, 32, 4A, 33, 07, 00, 08,
A0, 0D, 06, 34, 2D, 24, C7, 0C, 00,
A0, 0D, 06, 34, 34, 00, 00, EC, 03,
A0, 0D, 06, 34, 33, 0F, 01, 01, 70,
A0, 0D, 04, 34, 44, 22, 00,
A0, 0D, 06, 38, 4A, 33, 07, 00, 08,
A0, 0D, 06, 38, 42, 68, 10, FF, FF,
A0, 0D, 03, 38, 16, 00,
A0, 0D, 03, 38, 15, 00,
A0, 0D, 04, 3A, 44, 26, 00,
A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 3A, 34, 00, 00, E1, 03,
A0, 0D, 06, 3A, 33, 0B, 83, 00, 00,
A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B,
A0, 0D, 06, 3C, 42, 68, 10, FF, FF,
A0, 0D, 03, 3C, 16, 00,
A0, 0D, 03, 3C, 15, 00,
A0, 0D, 04, 3E, 44, 26, 00,
A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 3E, 34, 00, 00, E1, 03,
A0, 0D, 06, 3E, 33, 0B, 83, 00, 00,
A0, 0D, 06, 40, 42, F0, 10, FF, FF,
A0, 0D, 03, 40, 0D, 02,
A0, 0D, 03, 40, 14, 02,
A0, 0D, 06, 40, 4A, 12, 07, 00, 00
}
NXP_RF_CONF_BLK_3={
20, 02, F7, 20,
A0, 0D, 03, 40, 16, 00,
A0, 0D, 03, 40, 15, 00,
A0, 0D, 04, 42, 44, 26, 00,
A0, 0D, 06, 42, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 42, 34, 00, 00, E1, 03,
A0, 0D, 06, 42, 33, 0B, 83, 00, 00,
A0, 0D, 04, 46, 44, 26, 00,
A0, 0D, 06, 46, 2D, 15, 25, 0D, 00,
A0, 0D, 06, 44, 4A, 21, 07, 00, 07,
A0, 0D, 06, 44, 42, 88, 10, FF, FF,
A0, 0D, 03, 44, 16, 00,
A0, 0D, 03, 44, 15, 00,
A0, 0D, 04, 4A, 44, 21, 00,
A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00,
A0, 0D, 06, 48, 4A, 21, 07, 00, 07,
A0, 0D, 06, 48, 42, 88, 10, FF, FF,
A0, 0D, 03, 48, 16, 00,
A0, 0D, 03, 48, 15, 00,
A0, 0D, 04, 4E, 44, 26, 00,
A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00,
A0, 0D, 06, 4C, 4A, 21, 07, 00, 07,
A0, 0D, 06, 4C, 42, 88, 10, FF, FF,
A0, 0D, 03, 4C, 16, 00,
A0, 0D, 03, 4C, 15, 00,
A0, 0D, 04, 52, 44, 26, 00,
A0, 0D, 06, 52, 2D, 15, 25, 0D, 00,
A0, 0D, 06, 50, 42, 90, 10, FF, FF,
A0, 0D, 06, 50, 4A, 21, 07, 00, 07,
A0, 0D, 03, 50, 16, 00,
A0, 0D, 03, 50, 15, 00,
A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00,
A0, 0D, 04, 56, 44, 22, 00
}
NXP_RF_CONF_BLK_4={
20, 02, FB, 1E,
A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00,
A0, 0D, 04, 5C, 44, 26, 00,
A0, 0D, 06, 54, 42, 88, 10, FF, FF,
A0, 0D, 06, 54, 4A, 33, 07, 01, 07,
A0, 0D, 03, 54, 16, 00,
A0, 0D, 03, 54, 15, 00,
A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
A0, 0D, 06, 5A, 4A, 31, 07, 01, 07,
A0, 0D, 03, 5A, 16, 00,
A0, 0D, 03, 5A, 15, 00,
A0, 0D, 06, 98, 2F, CF, 05, 80, 17,
A0, 0D, 06, 98, 42, 00, 00, F2, F2,
A0, 0D, 06, 9A, 42, 00, 00, FF, FF,
A0, 0D, 06, 30, 44, 12, 90, 03, 00,
A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
A0, 0D, 06, 6C, 30, CF, 00, 08, 00,
A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C,
A0, 0D, 06, 70, 2F, 8F, 05, 80, 12,
A0, 0D, 06, 70, 30, CF, 00, 08, 00,
A0, 0D, 03, 70, 2E, 40,
A0, 0D, 03, 70, 45, 30,
A0, 0D, 06, 70, 44, A3, 90, 03, 00,
A0, 0D, 06, 74, 2F, 6F, 05, 80, 12,
A0, 0D, 06, 74, 30, D5, 00, 40, 00,
A0, 0D, 06, 74, 44, A3, 90, 03, 00,
A0, 0D, 06, 78, 2F, 3F, 07, 80, C1,
A0, 0D, 06, 78, 30, 50, 00, 10, 00,
A0, 0D, 06, 78, 44, A3, 90, 03, 00,
A0, 0D, 06, 7C, 2F, CF, 05, 80, 17,
A0, 0D, 06, 7C, 30, C8, 00, 64, 00
}
NXP_RF_CONF_BLK_5={
20, 02, F7, 1F,
A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
A0, 0D, 06, 80, 2F, CF, 05, 80, 17,
A0, 0D, 06, 80, 30, C8, 00, 64, 00,
A0, 0D, 06, 80, 44, A3, 90, 03, 00,
A0, 0D, 06, 84, 2F, CF, 05, 80, 17,
A0, 0D, 06, 84, 30, C8, 00, 64, 00,
A0, 0D, 06, 84, 44, A3, 90, 03, 00,
A0, 0D, 06, 88, 2F, B1, 05, 80, 17,
A0, 0D, 06, 88, 30, A8, 00, 64, 00,
A0, 0D, 06, 88, 44, A3, 90, 03, 00,
A0, 0D, 06, 8E, 44, 12, 90, 03, 00,
A0, 0D, 06, 94, 44, 12, 90, 03, 00,
A0, 0D, 03, 10, 43, 20,
A0, 0D, 06, 6A, 42, F8, 10, FF, FF,
A0, 0D, 03, 6A, 16, 00,
A0, 0D, 03, 6A, 15, 01,
A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F,
A0, 0D, 06, 8C, 42, 88, 10, FF, FF,
A0, 0D, 06, 8C, 4A, 33, 07, 01, 07,
A0, 0D, 03, 8C, 16, 00,
A0, 0D, 03, 8C, 15, 00,
A0, 0D, 06, 92, 42, 90, 10, FF, FF,
A0, 0D, 06, 92, 4A, 31, 07, 01, 07,
A0, 0D, 03, 92, 16, 00,
A0, 0D, 03, 92, 15, 00,
A0, 0D, 03, 24, 41, 40,
A0, 0D, 06, 24, 42, 00, 00, F2, F2,
A0, 0D, 03, 28, 41, 40,
A0, 0D, 03, 8A, 41, 40,
A0, 0D, 03, 90, 41, 40,
A0, 0D, 06, 0A, 30, C8, 00, 64, 00
}
NXP_RF_CONF_BLK_6={
20, 02, 53, 07,
A0, 0D, 06, 0A, 2F, AF, 05, 80, 17,
A0, 0D, 03, 0A, 48, 10,
A0, 0D, 06, 0A, 44, A3, 90, 03, 00,
A0, 0D, 06, 0A, 34, 26, 65, E5, 03,
A0, 0D, 06, 0A, 33, 0F, 01, 00, 70,
A0, 1D, 11, 53, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00
}
###############################################################################
# Core configuration extensions
# It includes
# A002 - Disable/Enable Clock Request
# A009 - Time-out before standby
# A012 - NFCEE interface 2 configuration
# A040 - Low Power Card Detector Enable
# A041 - Low Power Card Detector Threshold
# A042 - Low Power Card Detector Sampling
# A043 - Low Power Card Detector Hybrid
# A05E - Send RID automatically in Jewel Reader mode
# A061 - Retry after LPCD
# A096 - Notify all AIDs
# A0DD - Retry on SWP2 interface
# A0EC - Disable/Enable SWP1 interface
# A0ED - Disable/Enable SWP2 interface
# A0F2 - SVDD_PWR_REQ enable
NXP_CORE_CONF_EXTN={20, 02, 3A, 0E,
A0, 02, 01, 01,
A0, 09, 02, E8, 03,
A0, 12, 01, 00,
A0, 40, 01, 01,
A0, 41, 01, 05,
A0, 42, 01, 0F,
A0, 43, 01, 03,
A0, 5E, 01, 01,
A0, 61, 01, 53,
A0, 96, 01, 01,
A0, DD, 01, 2D,
A0, EC, 01, 00,
A0, ED, 01, 00,
A0, F2, 01, 00
}
###############################################################################
# Core configuration settings
# It includes
# 18 - Poll Mode NFC-F: PF_BIT_RATE
# 21 - Poll Mode ISO-DEP: PI_BIT_RATE
# 28 - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
# 30 - Lis. Mode NFC-A: LA_BIT_FRAME_SDD
# 31 - Lis. Mode NFC-A: LA_PLATFORM_CONFIG
# 33 - Lis. Mode NFC-A: LA_NFCID1
# 50 - Lis. Mode NFC-F: LF_PROTOCOL_TYPE
# 54 - Lis. Mode NFC-F: LF_CON_BITR_F
# 5B - Lis. Mode ISO-DEP: LI_BIT_RATE
# 60 - Lis. Mode NFC-DEP: LN_WT
# 80 - Other Param.: RF_FIELD_INFO
# 81 - Other Param.: RF_NFCEE_ACTION
# 82 - Other Param.: NFCDEP_OP
NXP_CORE_CONF={20, 02, 2B, 0D,
18, 01, 01,
21, 01, 00,
28, 01, 00,
30, 01, 08,
31, 01, 03,
33, 04, 01, 02, 03, 04,
50, 01, 02,
54, 01, 06,
5B, 01, 00,
60, 01, 0E,
80, 01, 01,
81, 01, 01,
82, 01, 0E
}
###############################################################################
# Max transceive length for ISO_DEP (THIS IS NOT AVALIABLE ON OREO UPSTREAM)
ISO_DEP_MAX_TRANSCEIVE=0xFEFF
###############################################################################
# Vendor Specific Proprietary Protocol & Discovery Configuration
# Set to 0xFF if unsupported
# byte[0] NCI_PROTOCOL_18092_ACTIVE
# byte[1] NCI_PROTOCOL_B_PRIME
# byte[2] NCI_PROTOCOL_DUAL
# byte[3] NCI_PROTOCOL_15693
# byte[4] NCI_PROTOCOL_KOVIO
# byte[5] NCI_PROTOCOL_MIFARE
# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
NFA_PROPRIETARY_CFG={05, FF, FF, 06, 81, 80, 70, FF, FF}
###############################################################################
# Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1.
# 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
# 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
# 2 NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate
# 3 NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0
# 4 NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3
PRESENCE_CHECK_ALGORITHM=1
###############################################################################
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