Works (THIS TIME I MEAN IT!!)

gistfile1.v

## clockgen.v
module clockgen(
  output reg clk_enable,
  input clk_src, 
  input [31:0] clk_division);
  
  reg [31:0] clk_accumulator;
    
  initial begin
    clk_accumulator = 0;
    clk_enable = 0;
  end
  
  always @(posedge clk_src) begin
    // FIXME: This accumulation takes wall time to finish.
    clk_accumulator <= clk_accumulator + 1;
    
    clk_enable <= 0;
    if (clk_accumulator == clk_division) begin
      clk_accumulator <= 0;
      clk_enable <= 1;
    end
  end
endmodule

## tx_uart.v
module tx_uart(
  output reg tx,
  input tx_enable,
  input clock_enabled,
  input clock, 
  input [7:0] data);

  parameter IDLE = 0;
  parameter SEND_START_BIT = 1;
  parameter SEND_DATA = 2;
  parameter SEND_STOP_BIT = 3;
  
  /* States:
   * Idle
   * Send Start bit
   * Send Data
   * Send Stop bit
   
   IDLE -> SEND_START_BIT -> SEND_DATA -> SEND_STOP_BIT -> IDLE
  */
  reg [2:0] currentState;
  // Data to send out. Latch onto this when leaving the IDLE state.
  reg [7:0] sendingData;
  
  reg [0:8] i; // loop control variable
  
  initial begin
    currentState = IDLE;
  end
  
  always @(posedge clock) begin
    if (clock_enabled == 1) begin
      case (currentState)
        IDLE: begin
          if(tx_enable) begin
            sendingData <= data;
            currentState <= SEND_START_BIT;
          end 
          else begin
            tx <= 1;
          end
        end
        SEND_START_BIT: begin
          i <= 0;
          tx <= 0; 
          currentState <= SEND_DATA;
        end
        SEND_DATA: begin
          tx <= sendingData[i];
          i <= i + 1;
          if (i == 7)
            currentState <= SEND_STOP_BIT;
        end
        SEND_STOP_BIT: begin
          tx <= 1;
          currentState <= tx_enable ? SEND_START_BIT : IDLE;
        end
      endcase
    end
  end
  
endmodule

## uart.v
module uart(
  output reg tx,
  input tx_enable, 
  input clock); 
  /* , 
  input [7:0] data);
  */
  
  parameter [7:0] data = {1'b0,
                  1'b1,
                  1'b0,
                  1'b1,
                  1'b0,
                  1'b1,
                  1'b0,
                  1'b1};
  
  //parameter [7:0] data = {1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1,1'b0};
  
  parameter CLOCK_DIVISION = 50000000 / 9600;
  wire tx_out, clk_enabled;
  
  assign data_r = data;
  clockgen clk(clk_enabled, clock, CLOCK_DIVISION);
  tx_uart txmit(tx_out, tx_enable, clk_enabled, clock, data);
  
  always @(tx_out) begin
    tx <= tx_out;
  end
  
  
endmodule