litghost

diff --git a/util/syn_yosys.sh b/util/syn_yosys.sh
index 4bebe42d..273f802c 100755
--- a/util/syn_yosys.sh
+++ b/util/syn_yosys.sh
@@ -18,12 +18,12 @@
 # use fusesoc to generate files and file list
 #-------------------------------------------------------------------------
 \rm -Rf build
-fusesoc --cores-root .. run --target=sim --setup --build formal > /dev/null 2>&1
+fusesoc --cores-root .. run --target=sim --setup --build lowrisc:systems:top_earlgrey:0.1

litghost

sqlite> SELECT phy_tile.name, wire_in_tile.name 
   ...> FROM wire
   ...> INNER JOIN phy_tile ON phy_tile.pkey = wire.phy_tile_pkey
   ...> INNER JOIN wire_in_tile ON wire_in_tile.pkey = wire.wire_in_tile_pkey
   ...> WHERE
   ...>   wire.node_pkey = (
   ...>     SELECT node_pkey FROM wire
   ...>     INNER JOIN phy_tile ON phy_tile.pkey = wire.phy_tile_pkey
   ...>     INNER JOIN wire_in_tile ON wire_in_tile.pkey = wire.wire_in_tile_pkey
   ...>     WHERE

litghost

sqlite> SELECT phy_tile.name, wire_in_tile.name 
   ...> FROM wire
   ...> INNER JOIN phy_tile ON phy_tile.pkey = wire.phy_tile_pkey
   ...> INNER JOIN wire_in_tile ON wire_in_tile.pkey = wire.wire_in_tile_pkey
   ...> WHERE
   ...>   wire.node_pkey = (
   ...>     SELECT node_pkey FROM wire
   ...>     INNER JOIN phy_tile ON phy_tile.pkey = wire.phy_tile_pkey
   ...>     INNER JOIN wire_in_tile ON wire_in_tile.pkey = wire.wire_in_tile_pkey
   ...>     WHERE

litghost

import argparse
import lxml.etree as etree
from scipy.spatial import KDTree
import pickle
import sys

def main():
    sys.setrecursionlimit(10000)

    parser = argparse.ArgumentParser(description="Sort rr node ids by geometric location.")

litghost

      <direct name="AFF.PASS" input="SLICE_FF.D[0]" output="SLICE_FF.Q[0]">       
        <meta name="fasm_mux">                                                 
          SLICE_FF.Q[0] : AFF.ZRST,AFF.ZINI,LATCH                                 
        </meta>                                                                                                                                                                                                    
      </direct>

litghost

(* blackbox *)
module STUB(
    input IN,
    output OUT
);

  assign OUT = IN;

endmodule

litghost

module test();

(* TEST="" *) parameter A = 0;

endmodule

litghost

create_project -force -part xc7a35tcpg236-1 design design

read_verilog /usr/local/google/home/keithrothman/cat_x/symbiflow-arch-defs-real-route-timing/build/xc7/tests/counter/counter_basys3/artix7-xc7a50t-basys3-roi-virt-xc7a50t-basys3-test/top_bit.v
synth_design -top top
source /usr/local/google/home/keithrothman/cat_x/symbiflow-arch-defs-real-route-timing/build/xc7/tests/counter/counter_basys3/artix7-xc7a50t-basys3-roi-virt-xc7a50t-basys3-test/top_bit.v.tcl


create_clock -period 10.0 -name clk -waveform {0.000 5.0} [get_ports clk]

litghost

,BLK_SY-GND,,,BLK_SY-INPAD,,,BLK_SY-OUTPAD,,,BLK_SY-VCC,,,BLK_TI-BRAM_L,,,BLK_TI-CLBLL_L,,,BLK_TI-CLBLL_R,,,BLK_TI-CLBLM_L,,,BLK_TI-CLBLM_R,,,EMPTY,,
,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack,ff_pack,no_ff_pack,round_robin_ff_pack
7-carry_stress_init0_depth_10_dummy_artix7_xc7a50t-basys3_test,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,3,3,3,0,0,0,0,0,0,0,0,0
7-carry_stress_init0_depth_11_dummy_artix7_xc7a50t-basys3_test,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,3,3,3,0,0,0,0,0,0,0,0,0
7-carry_stress_init0_depth_12_dummy_artix7_xc7a50t-basys3_test,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,3,3,3,0,0,0,0,0,0,0,0,0
7-carry_stress_init0_depth_13_dummy_artix7_xc7a50t-basys3_test,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,4,4,4,0,0,0,0,0

litghost

CLBLL_R_X17Y131.SLICEL_X0.ALUT.INIT[63:32]=32'b11111111111111111111111111111111
CLBLL_R_X17Y131.SLICEL_X0.BLUT.INIT[63:32]=32'b10101010101010101010101010101010
CLBLL_R_X17Y131.SLICEL_X0.CLUT.INIT[63:32]=32'b11001100110011001100110011001100
CLBLL_R_X17Y131.SLICEL_X0.DLUT.INIT[31:0]=32'b11001100110011001100110011001100
CLBLL_R_X17Y131.SLICEL_X0.DLUT.INIT[63:32]=32'b11001100110011001100110011001100
CLBLL_R_X17Y131.SLICEL_X0.CEUSEDMUX
CLBLL_R_X17Y131.SLICEL_X0.SRUSEDMUX
CLBLL_R_X17Y131.SLICEL_X0.CEUSEDMUX
CLBLL_R_X17Y131.SLICEL_X0.SRUSEDMUX
CLBLL_R_X17Y131.SLICEL_X0.DOUTMUX.D5Q