-
-
Save lmore377/5b880c8be8bf33e408f3099396f84344 to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| /dts-v1/; | |
| / { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| model = "Askey RT4230W-D187/REV6"; | |
| compatible = "askey,rt4230w-d187-rev6\0qcom,ipq8064"; | |
| interrupt-parent = <0x01>; | |
| chosen { | |
| bootargs-append = " console=ttyMSM0,115200n8"; | |
| }; | |
| aliases { | |
| mdio-gpio0 = "/soc/mdio"; | |
| ethernet0 = "/soc/ethernet@37000000"; | |
| ethernet1 = "/soc/ethernet@37200000"; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00 0x00>; | |
| }; | |
| cpus { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cpu@0 { | |
| compatible = "qcom,krait"; | |
| enable-method = "qcom,kpss-acc-v1"; | |
| device_type = "cpu"; | |
| reg = <0x00>; | |
| next-level-cache = <0x02>; | |
| qcom,acc = <0x03>; | |
| qcom,saw = <0x04>; | |
| clocks = <0x05 0x00>; | |
| clock-names = "cpu"; | |
| core-supply = <0x06>; | |
| qcom,imem = <0x07>; | |
| operating-points-0-0 = <0x1a5248 0x1343a4 0x155cc0 0x11edd8 0xf4240 0x10c8e0 0xc3500 0x100590 0x927c0 0xf4240 0x5dc00 0xee098>; | |
| operating-points-0-1 = <0x1a5248 0x12b128 0x155cc0 0x118c30 0xf4240 0x106738 0xc3500 0xfa3e8 0x927c0 0xee098 0x5dc00 0xe7ef0>; | |
| operating-points-0-2 = <0x1a5248 0x124f80 0x155cc0 0x112a88 0xf4240 0x100590 0xc3500 0xf4240 0x927c0 0xe7ef0 0x5dc00 0xe1d48>; | |
| operating-points-0-3 = <0x1a5248 0x11edd8 0x155cc0 0x10c8e0 0xf4240 0xfa3e8 0xc3500 0xee098 0x927c0 0xe1d48 0x5dc00 0xdbba0>; | |
| clock-latency = <0x186a0>; | |
| voltage-tolerance = <0x05>; | |
| cpu_fab_threshold = <0x3b9aca00>; | |
| cooling-min-state = <0x00>; | |
| cooling-max-state = <0x0a>; | |
| #cooling-cells = <0x02>; | |
| operating-points-0-4 = <0x1a5248 0x118c30 0x155cc0 0x106738 0xf4240 0xf4240 0xc3500 0xe7ef0 0x927c0 0xdbba0 0x5dc00 0xd59f8>; | |
| operating-points-0-5 = <0x1a5248 0x10c8e0 0x155cc0 0xfa3e8 0xf4240 0xe7ef0 0xc3500 0xdbba0 0x927c0 0xcf850 0x5dc00 0xc96a8>; | |
| operating-points-0-6 = <0x1a5248 0x100590 0x155cc0 0xee098 0xf4240 0xdbba0 0xc3500 0xcf850 0x927c0 0xc3500 0x5dc00 0xbd358>; | |
| }; | |
| cpu@1 { | |
| compatible = "qcom,krait"; | |
| enable-method = "qcom,kpss-acc-v1"; | |
| device_type = "cpu"; | |
| reg = <0x01>; | |
| next-level-cache = <0x02>; | |
| qcom,acc = <0x08>; | |
| qcom,saw = <0x09>; | |
| core-supply = <0x0a>; | |
| clocks = <0x05 0x01>; | |
| clock-names = "cpu"; | |
| qcom,imem = <0x07>; | |
| operating-points-0-0 = <0x1a5248 0x1343a4 0x155cc0 0x11edd8 0xf4240 0x10c8e0 0xc3500 0x100590 0x927c0 0xf4240 0x5dc00 0xee098>; | |
| operating-points-0-1 = <0x1a5248 0x12b128 0x155cc0 0x118c30 0xf4240 0x106738 0xc3500 0xfa3e8 0x927c0 0xee098 0x5dc00 0xe7ef0>; | |
| operating-points-0-2 = <0x1a5248 0x124f80 0x155cc0 0x112a88 0xf4240 0x100590 0xc3500 0xf4240 0x927c0 0xe7ef0 0x5dc00 0xe1d48>; | |
| operating-points-0-3 = <0x1a5248 0x11edd8 0x155cc0 0x10c8e0 0xf4240 0xfa3e8 0xc3500 0xee098 0x927c0 0xe1d48 0x5dc00 0xdbba0>; | |
| clock-latency = <0x186a0>; | |
| cpu_fab_threshold = <0x3b9aca00>; | |
| cooling-min-state = <0x00>; | |
| cooling-max-state = <0x0a>; | |
| #cooling-cells = <0x02>; | |
| operating-points-0-4 = <0x1a5248 0x118c30 0x155cc0 0x106738 0xf4240 0xf4240 0xc3500 0xe7ef0 0x927c0 0xdbba0 0x5dc00 0xd59f8>; | |
| operating-points-0-5 = <0x1a5248 0x10c8e0 0x155cc0 0xfa3e8 0xf4240 0xe7ef0 0xc3500 0xdbba0 0x927c0 0xcf850 0x5dc00 0xc96a8>; | |
| operating-points-0-6 = <0x1a5248 0x100590 0x155cc0 0xee098 0xf4240 0xdbba0 0xc3500 0xcf850 0x927c0 0xc3500 0x5dc00 0xbd358>; | |
| }; | |
| l2-cache { | |
| compatible = "cache"; | |
| cache-level = <0x02>; | |
| clocks = <0x05 0x04>; | |
| clock-names = "cache"; | |
| vdd_dig-supply = <0x0b>; | |
| cache-points-kHz = <0x124f80 0x118c30 0x124f80 0xf4240 0x10c8e0 0x927c0 0x5dc00 0x10c8e0 0x5dc00>; | |
| linux,phandle = <0x02>; | |
| phandle = <0x02>; | |
| }; | |
| }; | |
| cpu-pmu { | |
| compatible = "qcom,krait-pmu"; | |
| interrupts = <0x01 0x0a 0x304>; | |
| }; | |
| clock-controller { | |
| compatible = "qcom,krait-cc-v1"; | |
| #clock-cells = <0x01>; | |
| linux,phandle = <0x05>; | |
| phandle = <0x05>; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| nss@40000000 { | |
| reg = <0x40000000 0x1000000>; | |
| no-map; | |
| }; | |
| smem@41000000 { | |
| reg = <0x41000000 0x200000>; | |
| no-map; | |
| }; | |
| wifi_dump@44000000 { | |
| reg = <0x44000000 0x600000>; | |
| no-map; | |
| }; | |
| wigig_dump@44400000 { | |
| reg = <0x44400000 0x200000>; | |
| no-map; | |
| }; | |
| rsvd@41200000 { | |
| reg = <0x41200000 0x300000>; | |
| no-map; | |
| }; | |
| }; | |
| clocks { | |
| sleep_clk { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x8000>; | |
| #clock-cells = <0x00>; | |
| linux,phandle = <0x14>; | |
| phandle = <0x14>; | |
| }; | |
| }; | |
| nss-common { | |
| compatible = "qcom,nss-common"; | |
| reg = <0x3000000 0x1000>; | |
| reg-names = "nss_fpb_base"; | |
| clocks = <0x0c 0x11b 0x0c 0x11a 0x0d 0x0e>; | |
| clock-names = "nss-core-clk\0nss-tcm-clk\0nss-fab0-clk\0nss-fab0-clk"; | |
| nss_core-supply = <0x0f>; | |
| nss_core_vdd_nominal = <0x10c8e0>; | |
| nss_core_vdd_high = <0x118c30>; | |
| nss_core_threshold_freq = <0x2bb0b140>; | |
| }; | |
| fab-scaling { | |
| compatible = "qcom,fab-scaling"; | |
| clocks = <0x10 0x11>; | |
| clock-names = "apps-fab-clk\0ddr-fab-clk"; | |
| fab_freq_high = <0x1fc4ef40>; | |
| fab_freq_nominal = <0x17d78400>; | |
| }; | |
| soc { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| compatible = "simple-bus"; | |
| nss@40000000 { | |
| compatible = "qcom,nss"; | |
| qcom,low-frequency = <0x68e7780>; | |
| qcom,mid-frequency = <0x23c34600>; | |
| qcom,max-frequency = <0x2faf0800>; | |
| interrupts = <0x00 0xd5 0x04 0x00 0xe8 0x04>; | |
| reg = <0x36000000 0x1000 0x39000000 0x10000>; | |
| reg-names = "nphys\0vphys"; | |
| clocks = <0x0c 0x11b 0x0c 0x119 0x0c 0x11a 0x0d 0x0e>; | |
| clock-names = "nss-core-clk\0nss-tcm-src\0nss-tcm-clk\0nss-fab0-clk\0nss-fab1-clk"; | |
| resets = <0x0c 0x73 0x0c 0x74 0x0c 0x75 0x0c 0x76>; | |
| reset-names = "clkrst-clamp\0clamp\0ahb\0axi"; | |
| qcom,id = <0x00>; | |
| qcom,num-irq = <0x02>; | |
| qcom,num-queue = <0x02>; | |
| qcom,load-addr = <0x40000000>; | |
| qcom,turbo-frequency; | |
| qcom,ipv4-enabled; | |
| qcom,ipv6-enabled; | |
| qcom,l2tpv2-enabled; | |
| qcom,gre-enabled; | |
| qcom,map-t-enabled; | |
| qcom,pptp-enabled; | |
| qcom,portid-enabled; | |
| qcom,shaping-enabled; | |
| qcom,tun6rd-enabled; | |
| qcom,tunipip6-enabled; | |
| qcom,wlan-dataplane-offload-enabled; | |
| qcom,wlanredirect-enabled; | |
| }; | |
| nss@40800000 { | |
| compatible = "qcom,nss"; | |
| qcom,low-frequency = <0x68e7780>; | |
| qcom,mid-frequency = <0x23c34600>; | |
| qcom,max-frequency = <0x2faf0800>; | |
| interrupts = <0x00 0xd6 0x04 0x00 0xe9 0x04>; | |
| reg = <0x36400000 0x1000 0x39010000 0x10000>; | |
| reg-names = "nphys\0vphys"; | |
| resets = <0x0c 0x77 0x0c 0x78 0x0c 0x79 0x0c 0x7a>; | |
| reset-names = "clkrst-clamp\0clamp\0ahb\0axi"; | |
| qcom,id = <0x01>; | |
| qcom,num-irq = <0x02>; | |
| qcom,load-addr = <0x40800000>; | |
| qcom,num-queue = <0x02>; | |
| qcom,turbo-frequency; | |
| qcom,capwap-enabled; | |
| qcom,crypto-enabled; | |
| qcom,dtls-enabled; | |
| qcom,ipsec-enabled; | |
| }; | |
| memory@700000 { | |
| compatible = "qcom,imem-ipq8064\0syscon"; | |
| reg = <0x700000 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges = <0x00 0x700000 0x1000>; | |
| linux,phandle = <0x07>; | |
| phandle = <0x07>; | |
| }; | |
| rpm@108000 { | |
| compatible = "qcom,rpm-ipq8064"; | |
| reg = <0x108000 0x1000>; | |
| qcom,ipc = <0x12 0x08 0x02>; | |
| interrupts = <0x00 0x13 0x00 0x00 0x15 0x00 0x00 0x16 0x00>; | |
| interrupt-names = "ack\0err\0wakeup"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| pinctrl-0 = <0x13>; | |
| pinctrl-names = "default"; | |
| smb208-s1a { | |
| compatible = "qcom,rpm-smb208"; | |
| reg = <0x88>; | |
| regulator-min-microvolt = <0x100590>; | |
| regulator-max-microvolt = <0x118c30>; | |
| qcom,switch-mode-frequency = <0x124f80>; | |
| linux,phandle = <0x0b>; | |
| phandle = <0x0b>; | |
| }; | |
| smb208-s1b { | |
| compatible = "qcom,rpm-smb208"; | |
| reg = <0x89>; | |
| regulator-min-microvolt = <0x100590>; | |
| regulator-max-microvolt = <0x118c30>; | |
| qcom,switch-mode-frequency = <0x124f80>; | |
| linux,phandle = <0x0f>; | |
| phandle = <0x0f>; | |
| }; | |
| smb208-s2a { | |
| compatible = "qcom,rpm-smb208"; | |
| reg = <0x8a>; | |
| regulator-min-microvolt = <0xc3500>; | |
| regulator-max-microvolt = <0x137478>; | |
| qcom,switch-mode-frequency = <0x124f80>; | |
| linux,phandle = <0x06>; | |
| phandle = <0x06>; | |
| }; | |
| smb208-s2b { | |
| compatible = "qcom,rpm-smb208"; | |
| reg = <0x8b>; | |
| regulator-min-microvolt = <0xc3500>; | |
| regulator-max-microvolt = <0x137478>; | |
| qcom,switch-mode-frequency = <0x124f80>; | |
| linux,phandle = <0x0a>; | |
| phandle = <0x0a>; | |
| }; | |
| cxo-clk { | |
| #clock-cells = <0x00>; | |
| compatible = "qcom,rpm-clk"; | |
| reg = <0x09>; | |
| qcom,rpm-clk-name = "cxo"; | |
| qcom,rpm-clk-freq = <0x17d7840>; | |
| qcom,rpm-clk-active-only; | |
| }; | |
| pxo-clk { | |
| #clock-cells = <0x00>; | |
| compatible = "qcom,rpm-clk"; | |
| reg = <0x7b>; | |
| qcom,rpm-clk-name = "pxo"; | |
| qcom,rpm-clk-freq = <0x17d7840>; | |
| qcom,rpm-clk-active-only; | |
| }; | |
| ebi1-clk { | |
| #clock-cells = <0x00>; | |
| compatible = "qcom,rpm-clk"; | |
| reg = <0x0c>; | |
| qcom,rpm-clk-name = "ebi1"; | |
| qcom,rpm-clk-freq = <0x1fc4ef40>; | |
| qcom,rpm-clk-active-only; | |
| linux,phandle = <0x11>; | |
| phandle = <0x11>; | |
| }; | |
| apps-fabric-clk { | |
| #clock-cells = <0x00>; | |
| compatible = "qcom,rpm-clk"; | |
| reg = <0x02>; | |
| qcom,rpm-clk-name = "apps-fabric"; | |
| qcom,rpm-clk-freq = <0x1fc4ef40>; | |
| qcom,rpm-clk-active-only; | |
| linux,phandle = <0x10>; | |
| phandle = <0x10>; | |
| }; | |
| nss-fabric0-clk { | |
| #clock-cells = <0x00>; | |
| compatible = "qcom,rpm-clk"; | |
| reg = <0x86>; | |
| qcom,rpm-clk-name = "nss-fabric0"; | |
| qcom,rpm-clk-freq = <0x1fc4ef40>; | |
| qcom,rpm-clk-active-only; | |
| linux,phandle = <0x0d>; | |
| phandle = <0x0d>; | |
| }; | |
| nss-fabric1-clk { | |
| #clock-cells = <0x00>; | |
| compatible = "qcom,rpm-clk"; | |
| reg = <0x87>; | |
| qcom,rpm-clk-name = "nss-fabric1"; | |
| qcom,rpm-clk-freq = <0xfe277a0>; | |
| qcom,rpm-clk-active-only; | |
| linux,phandle = <0x0e>; | |
| phandle = <0x0e>; | |
| }; | |
| }; | |
| rpm_log@10c0c8 { | |
| compatible = "qcom,rpm_log"; | |
| reg = <0x10c0c8 0x2000>; | |
| reg-names = "rpm_log_base_addr"; | |
| reg-offsets = <0x80 0xa0>; | |
| rpm_log_len = <0x1800>; | |
| }; | |
| pinmux@800000 { | |
| compatible = "qcom,ipq8064-pinctrl"; | |
| reg = <0x800000 0x4000>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| interrupts = <0x00 0x10 0x04>; | |
| linux,phandle = <0x16>; | |
| phandle = <0x16>; | |
| rpm_i2c_pinmux { | |
| linux,phandle = <0x13>; | |
| phandle = <0x13>; | |
| mux { | |
| pins = "gpio12\0gpio13"; | |
| function = "gsbi4"; | |
| drive-strength = <0x0c>; | |
| bias-disable; | |
| }; | |
| }; | |
| pcie1_pinmux { | |
| linux,phandle = <0x19>; | |
| phandle = <0x19>; | |
| mux { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pcie2_pinmux { | |
| linux,phandle = <0x1a>; | |
| phandle = <0x1a>; | |
| mux { | |
| pins = "gpio48"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_pins { | |
| linux,phandle = <0x15>; | |
| phandle = <0x15>; | |
| mux { | |
| pins = "gpio18\0gpio19\0gpio21"; | |
| function = "gsbi5"; | |
| drive-strength = <0x0a>; | |
| bias-none; | |
| }; | |
| cs { | |
| pins = "gpio20"; | |
| drive-strength = <0x0c>; | |
| }; | |
| }; | |
| nand_pins { | |
| linux,phandle = <0x1b>; | |
| phandle = <0x1b>; | |
| mux { | |
| pins = "gpio34\0gpio35\0gpio36\0gpio37\0gpio38\0gpio39\0gpio40\0gpio41\0gpio42\0gpio43\0gpio44\0gpio45\0gpio46\0gpio47"; | |
| function = "nand"; | |
| drive-strength = <0x0a>; | |
| bias-disable; | |
| }; | |
| pullups { | |
| pins = "gpio39"; | |
| bias-pull-up; | |
| }; | |
| hold { | |
| pins = "gpio40\0gpio41\0gpio42\0gpio43\0gpio44\0gpio45\0gpio46\0gpio47"; | |
| bias-bus-hold; | |
| }; | |
| }; | |
| mdio0_pins { | |
| linux,phandle = <0x24>; | |
| phandle = <0x24>; | |
| mux { | |
| pins = "gpio0\0gpio1"; | |
| function = "gpio"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| led_pinmux { | |
| linux,phandle = <0x23>; | |
| phandle = <0x23>; | |
| mux { | |
| pins = "gpio22\0gpio23\0gpio24"; | |
| drive-strength = <0x02>; | |
| bias-none; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@2000000 { | |
| compatible = "qcom,msm-qgic2"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x03>; | |
| reg = <0x2000000 0x1000 0x2002000 0x1000>; | |
| linux,phandle = <0x01>; | |
| phandle = <0x01>; | |
| }; | |
| timer@200a000 { | |
| compatible = "qcom,kpss-timer\0qcom,msm-timer"; | |
| interrupts = <0x01 0x01 0x301 0x01 0x02 0x301 0x01 0x03 0x301>; | |
| reg = <0x200a000 0x100>; | |
| clock-frequency = <0x17d7840 0x8000>; | |
| cpu-offset = <0x80000>; | |
| }; | |
| watchdog@208a038 { | |
| compatible = "qcom,kpss-wdt-ipq8064"; | |
| reg = <0x208a038 0x40>; | |
| clocks = <0x14>; | |
| timeout-sec = <0x0a>; | |
| }; | |
| clock-controller@2088000 { | |
| compatible = "qcom,kpss-acc-v1"; | |
| reg = <0x2088000 0x1000 0x2008000 0x1000>; | |
| clock-output-names = "acpu0_aux"; | |
| linux,phandle = <0x03>; | |
| phandle = <0x03>; | |
| }; | |
| clock-controller@2098000 { | |
| compatible = "qcom,kpss-acc-v1"; | |
| reg = <0x2098000 0x1000 0x2008000 0x1000>; | |
| clock-output-names = "acpu1_aux"; | |
| linux,phandle = <0x08>; | |
| phandle = <0x08>; | |
| }; | |
| clock-controller@2011000 { | |
| compatible = "qcom,kpss-gcc\0syscon"; | |
| reg = <0x2011000 0x1000>; | |
| clock-output-names = "acpu_l2_aux"; | |
| linux,phandle = <0x12>; | |
| phandle = <0x12>; | |
| }; | |
| regulator@2089000 { | |
| compatible = "qcom,saw2"; | |
| reg = <0x2089000 0x1000 0x2009000 0x1000>; | |
| regulator; | |
| linux,phandle = <0x04>; | |
| phandle = <0x04>; | |
| }; | |
| regulator@2099000 { | |
| compatible = "qcom,saw2"; | |
| reg = <0x2099000 0x1000 0x2009000 0x1000>; | |
| regulator; | |
| linux,phandle = <0x09>; | |
| phandle = <0x09>; | |
| }; | |
| gsbi@12440000 { | |
| compatible = "qcom,gsbi-v1.0.0"; | |
| reg = <0x12440000 0x1000>; | |
| clocks = <0x0c 0x7f>; | |
| clock-names = "iface"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| status = "disabled"; | |
| i2c@12460000 { | |
| compatible = "qcom,i2c-qup-v1.1.1"; | |
| reg = <0x12460000 0x1000>; | |
| interrupts = <0x00 0xc2 0x00>; | |
| clocks = <0x0c 0x87 0x0c 0x7f>; | |
| clock-names = "core\0iface"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| }; | |
| gsbi@12480000 { | |
| compatible = "qcom,gsbi-v1.0.0"; | |
| reg = <0x12480000 0x100>; | |
| clocks = <0x0c 0x80>; | |
| clock-names = "iface"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| status = "disabled"; | |
| serial@12490000 { | |
| compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm"; | |
| reg = <0x12490000 0x1000 0x12480000 0x1000>; | |
| interrupts = <0x00 0xc3 0x00>; | |
| clocks = <0x0c 0x97 0x0c 0x80>; | |
| clock-names = "core\0iface"; | |
| status = "disabled"; | |
| }; | |
| hs_uart@12490000 { | |
| compatible = "qcom,msm-hsuart-v13"; | |
| reg = <0x12490000 0x1000 0x12480000 0x1000>; | |
| interrupts = <0x00 0xc3 0x00>; | |
| clocks = <0x0c 0x97 0x0c 0x80>; | |
| clock-names = "core\0iface"; | |
| status = "disabled"; | |
| }; | |
| i2c@124a0000 { | |
| compatible = "qcom,i2c-qup-v1.1.1"; | |
| reg = <0x124a0000 0x1000>; | |
| interrupts = <0x00 0xc4 0x00>; | |
| clocks = <0x0c 0x89 0x0c 0x80>; | |
| clock-names = "core\0iface"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| }; | |
| gsbi@16300000 { | |
| compatible = "qcom,gsbi-v1.0.0"; | |
| reg = <0x16300000 0x100>; | |
| clocks = <0x0c 0x82>; | |
| clock-names = "iface"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| status = "ok"; | |
| qcom,mode = <0x06>; | |
| serial@16340000 { | |
| compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm"; | |
| reg = <0x16340000 0x1000 0x16300000 0x1000>; | |
| interrupts = <0x00 0x98 0x00>; | |
| clocks = <0x0c 0x9b 0x0c 0x82>; | |
| clock-names = "core\0iface"; | |
| status = "ok"; | |
| }; | |
| i2c@16380000 { | |
| compatible = "qcom,i2c-qup-v1.1.1"; | |
| reg = <0x16380000 0x1000>; | |
| interrupts = <0x00 0x99 0x00>; | |
| clocks = <0x0c 0x8d 0x0c 0x82>; | |
| clock-names = "core\0iface"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| }; | |
| gsbi@1a200000 { | |
| compatible = "qcom,gsbi-v1.0.0"; | |
| reg = <0x1a200000 0x100>; | |
| clocks = <0x0c 0x83>; | |
| clock-names = "iface"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| status = "ok"; | |
| qcom,mode = <0x03>; | |
| serial@1a240000 { | |
| compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm"; | |
| reg = <0x1a240000 0x1000 0x1a200000 0x1000>; | |
| interrupts = <0x00 0x9a 0x00>; | |
| clocks = <0x0c 0x9d 0x0c 0x83>; | |
| clock-names = "core\0iface"; | |
| status = "disabled"; | |
| }; | |
| i2c@1a280000 { | |
| compatible = "qcom,i2c-qup-v1.1.1"; | |
| reg = <0x1a280000 0x1000>; | |
| interrupts = <0x00 0x9b 0x00>; | |
| clocks = <0x0c 0x8f 0x0c 0x83>; | |
| clock-names = "core\0iface"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| spi@1a280000 { | |
| compatible = "qcom,spi-qup-v1.1.1"; | |
| reg = <0x1a280000 0x1000>; | |
| interrupts = <0x00 0x9b 0x00>; | |
| clocks = <0x0c 0x8f 0x0c 0x83>; | |
| clock-names = "core\0iface"; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-0 = <0x15>; | |
| pinctrl-names = "default"; | |
| cs-gpios = <0x16 0x14 0x00>; | |
| dmas = <0x17 0x06 0x09 0x17 0x05 0x0a>; | |
| dma-names = "rx\0tx"; | |
| m25p80@0 { | |
| compatible = "s25fl256s1"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| spi-max-frequency = <0x2faf080>; | |
| reg = <0x00>; | |
| m25p,fast-read; | |
| }; | |
| }; | |
| }; | |
| sata-phy@1b400000 { | |
| compatible = "qcom,ipq806x-sata-phy"; | |
| reg = <0x1b400000 0x200>; | |
| clocks = <0x0c 0xbb>; | |
| clock-names = "cfg"; | |
| #phy-cells = <0x00>; | |
| status = "ok"; | |
| tx_preemph_gen3 = <0x15>; | |
| rx_eq = <0x04>; | |
| mpll = <0xa0>; | |
| term_off = <0x07>; | |
| linux,phandle = <0x18>; | |
| phandle = <0x18>; | |
| }; | |
| sata@29000000 { | |
| compatible = "qcom,ipq806x-ahci"; | |
| reg = <0x29000000 0x180>; | |
| interrupts = <0x00 0xd1 0x00>; | |
| clocks = <0x0c 0x32 0x0c 0xb5 0x0c 0xba 0x0c 0xb6 0x0c 0xb7 0x0c 0xb8>; | |
| clock-names = "slave_face\0iface\0core\0src\0rxoob\0pmalive"; | |
| assigned-clocks = <0x0c 0xb7 0x0c 0xb8>; | |
| assigned-clock-rates = <0x5f5e100 0x5f5e100>; | |
| portmap = <0x01>; | |
| phys = <0x18>; | |
| phy-names = "sata-phy"; | |
| status = "ok"; | |
| }; | |
| qcom,ssbi@500000 { | |
| compatible = "qcom,ssbi"; | |
| reg = <0x500000 0x1000>; | |
| qcom,controller-type = "pmic-arbiter"; | |
| }; | |
| tsens-ipq806x { | |
| compatible = "qcom,ipq806x-tsens"; | |
| reg = <0x900000 0x3678 0x700000 0x420>; | |
| reg-names = "tsens_physical\0tsens_eeprom_physical"; | |
| interrupts = <0x00 0xb2 0x00>; | |
| qcom,sensors = <0x0b>; | |
| qcom,tsens_factor = <0x3e8>; | |
| qcom,slope = <0x498 0x498 0x482 0x498 0x457 0x46c 0x46c 0x4af 0x46c 0x4af 0x46c>; | |
| }; | |
| qcom,msm-thermal { | |
| compatible = "qcom,msm-thermal"; | |
| qcom,sensor-id = <0x00>; | |
| qcom,poll-ms = <0xfa>; | |
| qcom,limit-temp = <0x69>; | |
| qcom,temp-hysteresis = <0x0a>; | |
| qcom,freq-step = <0x02>; | |
| qcom,core-limit-temp = <0x73>; | |
| qcom,core-temp-hysteresis = <0x0a>; | |
| qcom,core-control-mask = <0x0e>; | |
| }; | |
| clock-controller@900000 { | |
| compatible = "qcom,gcc-ipq8064"; | |
| reg = <0x900000 0x4000>; | |
| #clock-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| linux,phandle = <0x0c>; | |
| phandle = <0x0c>; | |
| }; | |
| pci@1b500000 { | |
| compatible = "qcom,pcie-ipq8064-v2"; | |
| reg = <0x1b500000 0x1000 0x1b502000 0x80 0x1b600000 0x100>; | |
| reg-names = "base\0elbi\0parf"; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| device_type = "pci"; | |
| interrupts = <0x00 0x23 0x00 0x00 0x24 0x00 0x00 0x25 0x00 0x00 0x26 0x00 0x00 0x27 0x00>; | |
| resets = <0x0c 0x1b 0x0c 0x1a 0x0c 0x19 0x0c 0x18 0x0c 0x17 0x0c 0x16>; | |
| reset-names = "axi\0ahb\0por\0pci\0phy\0ext"; | |
| clocks = <0x0c 0x29 0x0c 0x2b 0x0c 0x2c 0x0c 0xf7 0x0c 0xf8 0x0c 0x2a>; | |
| clock-names = "core\0iface\0phy\0alt_src\0alt_clk\0aux"; | |
| status = "ok"; | |
| force_gen1 = <0x00>; | |
| reset-gpio = <0x16 0x03 0x00>; | |
| pinctrl-0 = <0x19>; | |
| pinctrl-names = "default"; | |
| ranges = <0x00 0x00 0x00 0xff00000 0x00 0x100000 0x81000000 0x00 0x00 0xfe00000 0x00 0x100000 0x82000000 0x00 0x00 0x8000000 0x00 0x7e00000>; | |
| pcie@0 { | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| #interrupt-cells = <0x01>; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x03>; | |
| device_type = "pci"; | |
| ath10k@0,0 { | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| device_type = "pci"; | |
| qcom,mtd-name = "0:ART"; | |
| qcom,cal-offset = <0x1000>; | |
| qcom,cal-len = <0x2f20>; | |
| }; | |
| }; | |
| }; | |
| pci@1b700000 { | |
| compatible = "qcom,pcie-ipq8064-v2"; | |
| reg = <0x1b700000 0x1000 0x1b702000 0x80 0x1b800000 0x100>; | |
| reg-names = "base\0elbi\0parf"; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| device_type = "pci"; | |
| interrupts = <0x00 0x39 0x00 0x00 0x3a 0x00 0x00 0x3b 0x00 0x00 0x3c 0x00 0x00 0x3d 0x00>; | |
| resets = <0x0c 0x5b 0x0c 0x5a 0x0c 0x59 0x0c 0x58 0x0c 0x57 0x0c 0x56>; | |
| reset-names = "axi\0ahb\0por\0pci\0phy\0ext"; | |
| clocks = <0x0c 0xf9 0x0c 0xfb 0x0c 0xfc 0x0c 0xfd 0x0c 0xfe 0x0c 0xfa>; | |
| clock-names = "core\0iface\0phy\0alt_src\0alt_clk\0aux"; | |
| status = "ok"; | |
| force_gen1 = <0x01>; | |
| reset-gpio = <0x16 0x30 0x00>; | |
| pinctrl-0 = <0x1a>; | |
| pinctrl-names = "default"; | |
| ranges = <0x00 0x00 0x00 0x31f00000 0x00 0x100000 0x81000000 0x00 0x00 0x31e00000 0x00 0x100000 0x82000000 0x00 0x00 0x2e000000 0x00 0x3e00000>; | |
| pcie@0 { | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| #interrupt-cells = <0x01>; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x03>; | |
| device_type = "pci"; | |
| ath10k@0,0 { | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| device_type = "pci"; | |
| qcom,mtd-name = "0:ART"; | |
| qcom,cal-offset = <0x5000>; | |
| qcom,cal-len = <0x2f20>; | |
| }; | |
| }; | |
| }; | |
| pci@1b900000 { | |
| compatible = "qcom,pcie-ipq8064-v2"; | |
| reg = <0x1b900000 0x1000 0x1b902000 0x80 0x1ba00000 0x100>; | |
| reg-names = "base\0elbi\0parf"; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| device_type = "pci"; | |
| interrupts = <0x00 0x47 0x00 0x00 0x48 0x00 0x00 0x49 0x00 0x00 0x4a 0x00 0x00 0x4b 0x00>; | |
| resets = <0x0c 0x63 0x0c 0x62 0x0c 0x61 0x0c 0x60 0x0c 0x5f 0x0c 0x5e>; | |
| reset-names = "axi\0ahb\0por\0pci\0phy\0ext"; | |
| clocks = <0x0c 0xff 0x0c 0x101 0x0c 0x102 0x0c 0x103 0x0c 0x104 0x0c 0x100>; | |
| clock-names = "core\0iface\0phy\0alt_src\0alt_clk\0aux"; | |
| status = "disabled"; | |
| force_gen1 = <0x00>; | |
| }; | |
| dma@18300000 { | |
| compatible = "qcom,adm"; | |
| reg = <0x18300000 0x100000>; | |
| interrupts = <0x00 0xaa 0x00>; | |
| #dma-cells = <0x02>; | |
| clocks = <0x0c 0x25 0x0c 0x26>; | |
| clock-names = "core\0iface"; | |
| resets = <0x0c 0x0d 0x0c 0x0c 0x0c 0x0b 0x0c 0x0a 0x0c 0x09>; | |
| reset-names = "clk\0pbus\0c0\0c1\0c2"; | |
| qcom,ee = <0x00>; | |
| status = "ok"; | |
| linux,phandle = <0x17>; | |
| phandle = <0x17>; | |
| }; | |
| nand@0x1ac00000 { | |
| compatible = "qcom,qcom_nand"; | |
| reg = <0x1ac00000 0x800>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| clocks = <0x0c 0x105>; | |
| clock-names = "core_clk"; | |
| status = "ok"; | |
| pinctrl-0 = <0x1b>; | |
| pinctrl-names = "default"; | |
| }; | |
| tcsr@1a400000 { | |
| compatible = "qcom,tcsr"; | |
| reg = <0x1a400000 0x100>; | |
| status = "ok"; | |
| qcom,usb-ctrl-select = <0x03>; | |
| }; | |
| phy@100f8800 { | |
| compatible = "qcom,dwc3-hsphy\0qcom,dwc3-hsphy-ipq8064"; | |
| reg = <0x100f8800 0x30>; | |
| clocks = <0x0c 0x109>; | |
| clock-names = "utmi"; | |
| status = "ok"; | |
| linux,phandle = <0x1e>; | |
| phandle = <0x1e>; | |
| }; | |
| phy@100f8830 { | |
| compatible = "qcom,dwc3-ssphy\0qcom,dwc3-ssphy-ipq8064"; | |
| reg = <0x100f8830 0x30>; | |
| clocks = <0x0c 0x10c>; | |
| clock-names = "ref"; | |
| status = "ok"; | |
| rx_eq = <0x02>; | |
| tx_deamp_3_5db = <0x20>; | |
| mpll = <0xa0>; | |
| linux,phandle = <0x1f>; | |
| phandle = <0x1f>; | |
| }; | |
| phy@110f8800 { | |
| compatible = "qcom,dwc3-hsphy\0qcom,dwc3-hsphy-ipq8064"; | |
| reg = <0x110f8800 0x30>; | |
| clocks = <0x0c 0x108>; | |
| clock-names = "utmi"; | |
| status = "ok"; | |
| linux,phandle = <0x1c>; | |
| phandle = <0x1c>; | |
| }; | |
| phy@110f8830 { | |
| compatible = "qcom,dwc3-ssphy\0qcom,dwc3-ssphy-ipq8064"; | |
| reg = <0x110f8830 0x30>; | |
| clocks = <0x0c 0x10b>; | |
| clock-names = "ref"; | |
| status = "ok"; | |
| rx_eq = <0x02>; | |
| tx_deamp_3_5db = <0x20>; | |
| mpll = <0xa0>; | |
| linux,phandle = <0x1d>; | |
| phandle = <0x1d>; | |
| }; | |
| usb30@0 { | |
| compatible = "qcom,dwc3"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| clocks = <0x0c 0x10b>; | |
| clock-names = "core"; | |
| ranges; | |
| status = "ok"; | |
| resets = <0x0c 0x67>; | |
| reset-names = "usb30_mstr_rst"; | |
| dwc3@11000000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x11000000 0xcd00>; | |
| interrupts = <0x00 0x6e 0x04>; | |
| usb-phy = <0x1c 0x1d>; | |
| phy-names = "usb2-phy\0usb3-phy"; | |
| tx-fifo-resize; | |
| dr_mode = "host"; | |
| dis_u3_susphy_quirk; | |
| usb3_dev_reset_quirk; | |
| }; | |
| }; | |
| usb30@1 { | |
| compatible = "qcom,dwc3"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| clocks = <0x0c 0x10c>; | |
| clock-names = "core"; | |
| ranges; | |
| status = "ok"; | |
| dwc3@10000000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x10000000 0xcd00>; | |
| interrupts = <0x00 0xcd 0x04>; | |
| usb-phy = <0x1e 0x1f>; | |
| phy-names = "usb2-phy\0usb3-phy"; | |
| tx-fifo-resize; | |
| dr_mode = "host"; | |
| dis_u3_susphy_quirk; | |
| usb3_dev_reset_quirk; | |
| }; | |
| }; | |
| rng@1a500000 { | |
| compatible = "qcom,prng"; | |
| reg = <0x1a500000 0x200>; | |
| clocks = <0x0c 0xd2>; | |
| clock-names = "core"; | |
| }; | |
| qcom,msm-imem@2A03F000 { | |
| compatible = "qcom,msm-imem"; | |
| reg = <0x2a03f000 0x1000>; | |
| ranges = <0x00 0x2a03f000 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| download_mode@0 { | |
| compatible = "qcom,msm-imem-download_mode"; | |
| reg = <0x00 0x08>; | |
| }; | |
| restart_reason@65c { | |
| compatible = "qcom,msm-imem-restart_reason"; | |
| reg = <0x65c 0x04>; | |
| }; | |
| l2_dump_offset@14 { | |
| compatible = "qcom,msm-imem-l2_dump_offset"; | |
| reg = <0x14 0x08>; | |
| }; | |
| }; | |
| qcom,restart_reason { | |
| compatible = "qcom,restart_reason"; | |
| }; | |
| qcom,cache_dump { | |
| compatible = "qcom,cache_dump"; | |
| qcom,l1-dump-size = <0x100000>; | |
| qcom,l2-dump-size = <0x200000>; | |
| }; | |
| vsdcc-regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "SDCC Power"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-always-on; | |
| linux,phandle = <0x20>; | |
| phandle = <0x20>; | |
| }; | |
| dma@12402000 { | |
| compatible = "qcom,bam-v1.3.0"; | |
| reg = <0x12402000 0x8000>; | |
| interrupts = <0x00 0x62 0x00>; | |
| clocks = <0x0c 0x62>; | |
| clock-names = "bam_clk"; | |
| #dma-cells = <0x01>; | |
| qcom,ee = <0x00>; | |
| linux,phandle = <0x21>; | |
| phandle = <0x21>; | |
| }; | |
| dma@12182000 { | |
| compatible = "qcom,bam-v1.3.0"; | |
| reg = <0x12182000 0x8000>; | |
| interrupts = <0x00 0x60 0x00>; | |
| clocks = <0x0c 0x64>; | |
| clock-names = "bam_clk"; | |
| #dma-cells = <0x01>; | |
| qcom,ee = <0x00>; | |
| linux,phandle = <0x22>; | |
| phandle = <0x22>; | |
| }; | |
| amba { | |
| compatible = "arm,amba-bus"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| sdcc@12400000 { | |
| status = "disabled"; | |
| compatible = "arm,pl18x\0arm,primecell"; | |
| arm,primecell-periphid = <0x51180>; | |
| reg = <0x12400000 0x2000>; | |
| interrupts = <0x00 0x68 0x04>; | |
| interrupt-names = "cmd_irq"; | |
| clocks = <0x0c 0x67 0x0c 0x62>; | |
| clock-names = "mclk\0apb_pclk"; | |
| bus-width = <0x08>; | |
| max-frequency = <0x5b8d800>; | |
| non-removable; | |
| cap-sd-highspeed; | |
| cap-mmc-highspeed; | |
| mmc-ddr-1_8v; | |
| vmmc-supply = <0x20>; | |
| dmas = <0x21 0x02 0x21 0x01>; | |
| dma-names = "tx\0rx"; | |
| }; | |
| sdcc@12180000 { | |
| compatible = "arm,pl18x\0arm,primecell"; | |
| arm,primecell-periphid = <0x51180>; | |
| status = "disabled"; | |
| reg = <0x12180000 0x2000>; | |
| interrupts = <0x00 0x66 0x04>; | |
| interrupt-names = "cmd_irq"; | |
| clocks = <0x0c 0x6b 0x0c 0x64>; | |
| clock-names = "mclk\0apb_pclk"; | |
| bus-width = <0x08>; | |
| cap-sd-highspeed; | |
| cap-mmc-highspeed; | |
| max-frequency = <0xb71b000>; | |
| #mmc-ddr-1_8v; | |
| sd-uhs-sdr104; | |
| sd-uhs-ddr50; | |
| vqmmc-supply = <0x20>; | |
| dmas = <0x22 0x02 0x22 0x01>; | |
| dma-names = "tx\0rx"; | |
| }; | |
| }; | |
| gpio_keys { | |
| compatible = "gpio-keys"; | |
| button@1 { | |
| label = "reset"; | |
| linux,code = <0x198>; | |
| gpios = <0x16 0x36 0x01>; | |
| linux,input-type = <0x01>; | |
| debounce-interval = <0x3c>; | |
| }; | |
| button@2 { | |
| label = "wps"; | |
| linux,code = <0x211>; | |
| gpios = <0x16 0x44 0x01>; | |
| linux,input-type = <0x01>; | |
| debounce-interval = <0x3c>; | |
| }; | |
| }; | |
| gpio_leds { | |
| compatible = "gpio-leds"; | |
| pinctrl-0 = <0x23>; | |
| ln1 { | |
| gpios = <0x16 0x16 0x00>; | |
| label = "ln1"; | |
| default-state = "off"; | |
| }; | |
| ln2 { | |
| gpios = <0x16 0x17 0x00>; | |
| label = "ln2"; | |
| default-state = "off"; | |
| }; | |
| ln3 { | |
| gpios = <0x16 0x18 0x00>; | |
| label = "ln3"; | |
| default-state = "on"; | |
| }; | |
| }; | |
| mdio { | |
| compatible = "virtual,mdio-gpio"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| gpios = <0x16 0x01 0x00 0x16 0x00 0x00>; | |
| pinctrl-0 = <0x24>; | |
| pinctrl-names = "default"; | |
| linux,phandle = <0x25>; | |
| phandle = <0x25>; | |
| ethernet-phy@0 { | |
| device_type = "ethernet-phy"; | |
| reg = <0x04>; | |
| qca,ar8327-initvals = <0x04 0x7600000 0x08 0x1000000 0x0c 0x80 0xe4 0xaa545 0xe0 0xc74164de 0x7c 0x4e 0x94 0x4e 0x50 0xcf02cf02 0x54 0xc832c832>; | |
| }; | |
| ethernet-phy@4 { | |
| device_type = "ethernet-phy"; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| nss-gmac-common { | |
| compatible = "qcom,nss-gmac-common"; | |
| reg = <0x3000000 0xffff 0x1bb00000 0xffff 0x900000 0x4000>; | |
| reg-names = "nss_reg_base\0qsgmii_reg_base\0clk_ctl_base"; | |
| }; | |
| ethernet@37000000 { | |
| device_type = "network"; | |
| compatible = "qcom,nss-gmac"; | |
| reg = <0x37000000 0x200000>; | |
| interrupts = <0x00 0xdc 0x04>; | |
| phy-mode = "rgmii"; | |
| qcom,id = <0x00>; | |
| qcom,pcs-chanid = <0x00>; | |
| qcom,phy-mdio-addr = <0x00>; | |
| qcom,poll-required = <0x01>; | |
| qcom,rgmii-delay = <0x01>; | |
| qcom,emulation = <0x00>; | |
| qcom,forced-speed = <0x3e8>; | |
| qcom,forced-duplex = <0x01>; | |
| qcom,socver = <0x00>; | |
| local-mac-address = [00 00 00 00 00 00]; | |
| mdiobus = <0x25>; | |
| }; | |
| ethernet@37200000 { | |
| device_type = "network"; | |
| compatible = "qcom,nss-gmac"; | |
| reg = <0x37200000 0x200000>; | |
| interrupts = <0x00 0xdf 0x04>; | |
| phy-mode = "sgmii"; | |
| qcom,id = <0x01>; | |
| qcom,pcs-chanid = <0x01>; | |
| qcom,phy-mdio-addr = <0x04>; | |
| qcom,poll-required = <0x00>; | |
| qcom,rgmii-delay = <0x00>; | |
| qcom,emulation = <0x00>; | |
| qcom,forced-speed = <0x3e8>; | |
| qcom,forced-duplex = <0x01>; | |
| qcom,socver = <0x00>; | |
| local-mac-address = [00 00 00 00 00 00]; | |
| mdiobus = <0x25>; | |
| }; | |
| crypto@38000000 { | |
| compatible = "qcom,nss-crypto"; | |
| reg-names = "crypto_pbase\0bam_base"; | |
| reg = <0x38000000 0x20000 0x38004000 0x22000>; | |
| resets = <0x0c 0x9d 0x0c 0xa1>; | |
| reset-names = "rst_eng\0rst_ahb"; | |
| clocks = <0x0c 0xed 0x0c 0xeb 0x0c 0xec>; | |
| clock-names = "ce5_core\0ce5_aclk\0ce5_hclk"; | |
| qcom,ee = <0x00>; | |
| }; | |
| crypto@38400000 { | |
| compatible = "qcom,nss-crypto"; | |
| reg-names = "crypto_pbase\0bam_base"; | |
| reg = <0x38400000 0x20000 0x38404000 0x22000>; | |
| resets = <0x0c 0x9e>; | |
| reset-names = "rst_eng"; | |
| qcom,ee = <0x00>; | |
| }; | |
| crypto@38800000 { | |
| compatible = "qcom,nss-crypto"; | |
| reg-names = "crypto_pbase\0bam_base"; | |
| reg = <0x38800000 0x20000 0x38804000 0x22000>; | |
| resets = <0x0c 0x9f>; | |
| reset-names = "rst_eng"; | |
| qcom,ee = <0x00>; | |
| }; | |
| crypto@38C00000 { | |
| compatible = "qcom,nss-crypto"; | |
| reg-names = "crypto_pbase\0bam_base"; | |
| reg = <0x38c00000 0x20000 0x38c04000 0x22000>; | |
| resets = <0x0c 0xa0>; | |
| reset-names = "rst_eng"; | |
| qcom,ee = <0x00>; | |
| }; | |
| }; | |
| }; |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment