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@lnsp
Created January 27, 2017 16:37
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VHDL Code testen

Schritt 1: GHDL und GtkWave installieren

Schritt 2: Testbench erstellen

Beispiel: Zu testende Entity

library ieee;
use ieee.std_logic_1164.all;

-- alarm automat
entity alarm is
  port (clk, start: in std_logic;
        alarm_sound: out std_logic);
end alarm;

architecture automat of alarm is
  signal z: std_logic_vector(2 downto 0) := "000";
begin
  alarm_sound <= '1' when z = "100" else '0';
  process(clk)
  begin
    if rising_edge(clk) then
   	  case z is
        when "000" =>
          if start = '1' then
            z <= "001";
          end if;
        when "001" =>
          z <= "010";
        when "010" =>
          z <= "011";
        when "011" =>
          z <= "100";
        when "100" =>
          if start = '0' then
            z <= "000";
          end if;
        when others =>
          z <= "000";
      end case;
    end if;
  end process;
end automat;

Beispiel: Testbenchcode

-- Testbench fuer alarm

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity alarm_tb is
end entity;

architecture verhalten of alarm_tb is
	component alarm is
		port (start, clk: in std_logic;
			  alarm_sound: out std_logic);
	end component;

	signal clk: std_logic := '0';
	signal start: std_logic := '0';
	signal alarm_sound: std_logic := '0';
begin
	clk <= not clk after 500 ms;
	start <= '1', '0' after 10 sec;

	dut: alarm port map (
		clk => clk,
		start => start,
		alarm_sound => alarm_sound
	);
end architecture;

Schritt 3: VHDL Dateien kompilieren

# Entities importieren
$ ghdl -i alarm.vhdl testbench.vhdl
# Entity kompilieren
$ ghdl -m alarm_tb

Schritt 4: Waveform erstellen und mit GTKWave öffnen

# Waveform erstellen
$ ./alarm_tb --stop-time=1min --vcd=alarm_tb.vcd
# Mit GTKWave öffnen
$ gtkwave alarm_tb.vcd

Schritt 5: Das Werk betrachten!

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