Smoothie 2 Debug Toolchain for FT232H

readme.md

These are instructions for setting up a toolchain for flashing and debugging a LPC4330 using an FTDI C232HM cable (FT232H chipset) with OpenOCD and GDB.

Links

Smoothie v2 Firmware

• https://github.com/Smoothieware/Smoothie2

FTDI Cable

• http://www.ftdichip.com/Products/Cables/USBMPSSE.htm
• http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_C232HM_MPSSE_CABLE.PDF

OpenOCD

• http://openocd.org/getting-openocd/

Toolchain Setup

• connect the ftdi device to the jtag port of the target board
  • red: 5V
  • orange: tck
  • yellow: tdi
  • green: tdo
  • brown: tms
  • grey: gpioL0 (reserved for srst)
  • black: gnd
• clone the Smoothie2 firmware to a folder and follow its readme to install the build environment and gdb
• download and install openocd as is appropriate for your operating system
• download the .cfg files attached to this gist in a place where they will be available to openocd
• run openocd with the command line openocd -f ft232h.cfg -f lpc4330_spifi_generic.cfg adding appropriate directories for each file
• in a separate terminal start a Smoothie2 build environment with gcc4mbed/BuildShell and run gdb with the appropriate elf file arm-none-eabi-gdb -n LPC4330_M4/Smoothie2.elf
• tell gdb to connect to open ocd with target remote localhost:3333
• if all went well you should now be connected and can start running commands

Flashing to SPIFI

• connect the toolchain as described above and run (in gdb terminal) monitor reset halt
• run (in gdb terminal) monitor flash write_image erase Smoothie2.bin 0x14000000

Getting a Backtrace

• connect the toolchain to the target and run (in gdb) monitor halt
• simplest way I have atm is to then run target remote localhost:3333 again to get it to refresh now that the chip is halted
• run bt to get the backtrace

ft232h.cfg

interface ftdi
ftdi_vid_pid 0x0403 0x6014

ftdi_layout_init 0x0c08 0x0f1b
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

adapter_khz 1000

transport select jtag

gdb_memory_map disable

lpc4330_spifi_generic.cfg

# based on board/lpc4350_spifi_generic.cfg from OpenOCD

set CHIPNAME lpc4330

source [find lpc43xx.cfg]

#A large working area greatly reduces flash write times
set _WORKAREASIZE 0x2000

$_CHIPNAME.m4 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE

#Configure the flash bank; 0x14000000 is the base address for
#lpc43xx/lpc18xx family micros.
flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4

lpc43xx.cfg

# based on target/lpc4350.cfg from OpenOCD
# Cortex-M0 core is disabled intentionally as it causes problems during debugging

#adapter_khz 500

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME lpc43xx
}

#
# M4 JTAG mode TAP
#
if { [info exists M4_JTAG_TAPID] } {
	set _M4_JTAG_TAPID $M4_JTAG_TAPID
} else {
	set _M4_JTAG_TAPID 0x4ba00477
}

#
# M4 SWD mode TAP
#
if { [info exists M4_SWD_TAPID] } {
	set _M4_SWD_TAPID $M4_SWD_TAPID
} else {
	set _M4_SWD_TAPID 0x2ba01477
}

#
# M0 TAP
#
if { [info exists M0_JTAG_TAPID] } {
	set _M0_JTAG_TAPID $M0_JTAG_TAPID
} else {
	set _M0_JTAG_TAPID 0x0ba01477
}

jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
				-expected-id $_M4_JTAG_TAPID

jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
				-expected-id $_M0_JTAG_TAPID

target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
#target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0

# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq

#$_CHIPNAME.m4 configure -event reset-assert {}