Skip to content

Instantly share code, notes, and snippets.

@logxen
Created April 20, 2022 22:31
Show Gist options
  • Save logxen/f5b572116bf1f0f57116c8763b939940 to your computer and use it in GitHub Desktop.
Save logxen/f5b572116bf1f0f57116c8763b939940 to your computer and use it in GitHub Desktop.
nandy isa 0
nandy isa 0
by logxen
* operations *
00WRRWRR dual reg mov (A <- B)
01WRRWRR dual reg nand (A <- A nand B; Z <- A nand B == 0)
10WRRCCC single reg op
000 mov 0 (RRR <- 0)
001 mov 1 (RRR <- 1)
010 store (mem[ar] <- RRR)
011 load (RRR <- mem[ar])
11? *rsv
11DDDDDD jez
W 0 is bit register bank, 1 is byte register bank
RR register number
CCC single reg op code
DDDDDD 6 bit signed jump offset
* registers *
000 bit reg r0
001 bit reg r1
010 bit reg r2
011 bit reg r3
100 byte reg r4
101 byte reg r5
110 byte reg r6
111 byte reg r7 ar
* conditions *
Z set to the opposite of the result of the nand op
* asm *
nop 0x00
mov 0x00
nand 0x40
mov0 0x80
mov1 0x81
store 0x82
load 0x83
jez 0xC0
* conventions *
jmp:
mov1 r3
nand r3 r3
jez OFFSET
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment