AR# 50826 Zynq-7000 Example Design - Cache coherent CDMA transfers from block RAM to OCM https://www.xilinx.com/support/answers/50826.html

AR50826.c

//AR# 50826 Zynq-7000 Example Design - Cache coherent CDMA transfers from block RAM to OCM 
//https://www.xilinx.com/support/answers/50826.html
//comment added
//modified Xil_SetTlbAttributes parameter
#include <xil_printf.h>
#include <xil_cache.h>
#include <stdlib.h>
#include <stdio.h>
#include <xuartps.h>
#include "xil_mmu.h"


#define CDMA_BASE_ADDR     0x60000000
#define MY_SIZE_BYTE    64

/* Write to memory location or register */
#define X_mWriteReg(BASE_ADDRESS, RegOffset, data) \
           *(unsigned int *)(BASE_ADDRESS + RegOffset) = ((unsigned int) data);
/* Read from memory location or register */
#define X_mReadReg(BASE_ADDRESS, RegOffset) \
           *(unsigned int *)(BASE_ADDRESS + RegOffset);

int main()
{
    char * srcDMA = (char *) 0x80000000; // from BRAM
    char * srcCPU = (char *) 0x70000000; // from BRAM
    char * dstDMA = (char *) 0xFFFF8000; // to OCM
    char * dstCPU = (char *) 0xFFFF8000; // to OCM

    volatile unsigned int i;
    volatile int value;
    unsigned int addresList[] = {0x0,0x18,0x20,0x28,0x4};

    /* C=1, B=1 disable cache*/
    /*comment out Xil_SetTlbAttributes because we use Xil_DCacheInvalidateRange*/
    //Xil_SetTlbAttributes(0xFFF00000,0x14c0e);
    xil_printf("\n\rHello World");
    xil_printf("\n\rsrcCPU addr = 0x%x",(unsigned int)srcCPU);
    xil_printf("\n\rsrcDMA addr = 0x%x",(unsigned int)srcDMA);
    xil_printf("\n\rdst addr = 0x%x",(unsigned int)dstCPU);

    value = X_mReadReg(0xF8000910,0x0);
    xil_printf("\n\r0x%x = 0x%x",0xF8000910,value);
    value = X_mReadReg(0xF8F00000,0x0);
    xil_printf("\n\r0x%x = 0x%x",0xF8000000,value);
    value = X_mReadReg(0xF8F00040,0x0);
    xil_printf("\n\r0x%x = 0x%x",0xF8000040,value);
    value = X_mReadReg(0xF8F00044,0x0);
    xil_printf("\n\r0x%x = 0x%x",0xF8000044,value);

    /*set data to BRAM and OCM*/
    for (i=0; i<MY_SIZE_BYTE; i++){
        srcCPU[i] = i+1;
        dstCPU[i] = 0xCD;
    }

    /*show data before CDMA data transfer*/
    xil_printf("\n\r ... src memory");
    for (i=0; i<MY_SIZE_BYTE; i++){
        xil_printf("\n\r0x%08x = 0x%08x",(unsigned int)(srcCPU+i),srcCPU[i]);
    }

    xil_printf("\n\r ... dst memory");
    for (i=0; i<MY_SIZE_BYTE; i++){
        xil_printf("\n\r0x%08x = 0x%08x",(unsigned int)(dstCPU+i),dstCPU[i]);
    }

    /*show default CDMA status*/
    xil_printf("\n\r ... default status");
    value = X_mReadReg( CDMA_BASE_ADDR, 0x4);
    xil_printf("\n\r0x%08x = 0x%08x",CDMA_BASE_ADDR+0x4,value);

    //control CDMA by write CDMA control register
    xil_printf("\n\r ... programming");
    /*enable Error Interrupt and Complete Interrupt*/
    X_mWriteReg(CDMA_BASE_ADDR,0x0,0x00005000);
    value = X_mReadReg( CDMA_BASE_ADDR, 0x0);
    xil_printf("\n\r0x%08x = 0x%08x",CDMA_BASE_ADDR+0x0,value);
    /*set source address*/
    X_mWriteReg(CDMA_BASE_ADDR,0x18,(unsigned int)srcDMA);
    value = X_mReadReg( CDMA_BASE_ADDR, 0x18);
    xil_printf("\n\r0x%08x = 0x%08x",CDMA_BASE_ADDR+0x18,value);
    /*set destination address*/
    X_mWriteReg(CDMA_BASE_ADDR,0x20,(unsigned int)dstDMA);
    value = X_mReadReg( CDMA_BASE_ADDR, 0x20);
    xil_printf("\n\r0x%08x = 0x%08x",CDMA_BASE_ADDR+0x20,value);
    /*set data transfer size*/
    X_mWriteReg(CDMA_BASE_ADDR,0x28,0x00000040);
    value = X_mReadReg( CDMA_BASE_ADDR, 0x28);
    xil_printf("\n\r0x%08x = 0x%08x",CDMA_BASE_ADDR+0x28,value);

    /*show CDMA status*/
    xil_printf("\n\r ... polling");
    for (i=0; i<5; i++){
        value = X_mReadReg( CDMA_BASE_ADDR, 0x4);
        xil_printf("\n\r0x%08x = 0x%08x",CDMA_BASE_ADDR+0x4,value);
    }
    /*show CDMA control register*/
    xil_printf("\n\r ... registers");
    for (i=0; i<4; i++){
        value = X_mReadReg( CDMA_BASE_ADDR, addresList[i]);
        xil_printf("\n\r0x%08x = 0x%08x",CDMA_BASE_ADDR+addresList[i],value);
    }

    //cache of dstCPU must be disabled
    Xil_DCacheInvalidateRange(dstCPU, 64*8);

    //show data transfer is successfully completed
    xil_printf("\n\r ... src memory");
    for (i=0; i<MY_SIZE_BYTE; i++){
        xil_printf("\n\r0x%08x = 0x%02x",(unsigned int)(srcCPU+i),srcCPU[i]);
    }

    xil_printf("\n\r ... dst memory");
    for (i=0; i<MY_SIZE_BYTE; i++){
        xil_printf("\n\r0x%08x = 0x%02x",(unsigned int)(dstCPU+i),dstCPU[i]);
    }

    return 0;
}