test.cpp

test.cpp

#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include <hls_math.h>
#include <math.h>

 //--- struct for image flowing through AXI4-Stream
template<int D>
struct im_axis{
	ap_uint<D>       data;
	ap_uint<1>       user;
	ap_uint<1>       last;
};
typedef im_axis<16> yuyv_image;
typedef im_axis<8> yonly_image;

#define WIDTH 1920
#define HEIGHT 1080

void yuyvy(hls::stream<yuyv_image>& axis_in, hls::stream<yonly_image> & axis_out, unsigned char& val){
	#pragma HLS INTERFACE axis port=axis_in
	#pragma HLS INTERFACE axis port=axis_out
	#pragma HLS INTERFACE s_axilite port=val bundle=CONTROL_BUS// clock=s_axi_aclk
	#pragma HLS INTERFACE ap_ctrl_none port=return
	im_axis<16> axis_reader; // for read AXI4-Stream
	im_axis<8> axis_writer; // for write AXI4-Stream
	bool sof = false;              // Start of Frame
	bool eol = false;              // End of Line

	// wait for the user signal to be asserted
	while (!sof) {
		#pragma HLS PIPELINE II=1
		#pragma HLS LOOP_TRIPCOUNT avg=0 max=0

		axis_in >> axis_reader;
		sof = axis_reader.user.to_int();
	}

	// image proc loop
	for(int yi = 0; yi < HEIGHT; yi++) {
		eol = false;
		for(int xi = 0; xi < WIDTH; xi++) {
			#pragma HLS PIPELINE II=1
			#pragma HLS LOOP_FLATTEN off

			// get pix until the last signal to be asserted
			if(sof || eol) {
				// when frame is started (first pix have already latched)
				// or
				// when WIDTH param set more than actual frame size
				sof = false;
				eol = axis_reader.last.to_int();
			}
			else {
				axis_in >> axis_reader;
				eol = axis_reader.last.to_int();
			}

			axis_writer.data = std::max((int)((axis_reader.data & 0xFF00) >> 8), (int)val);
			// assert user signal at start of frame
			if (xi == 0 && yi == 0) {
				axis_writer.user = 1;
			}else {
				axis_writer.user = 0;
			}

			// assert last signal at end of line
			if (xi == (WIDTH - 1)) {
				axis_writer.last = 1;
			}else {
				axis_writer.last = 0;
			}

			axis_out << axis_writer;
		}

		// when WIDTH param set less than actual frame size
		// wait for the last signal to be asserted
		while (!eol) {
			#pragma HLS pipeline II=1
			#pragma HLS loop_tripcount avg=0 max=0
			axis_in >> axis_reader;
			eol = axis_reader.last.to_int();
		}
	}

}