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lp6m / pcam_ubuntu_zybo.cpp
Last active December 5, 2023 12:08
Get image from PCam 5C on Ubuntu running on ZYBO-Z7-20
/*
Target board: ZYBO Z7-20
Kernel&Circuit:https://github.com/Digilent/Petalinux-Zybo-Z7-20
Distribution: Ubuntu 16.04
https://rcn-ee.com/rootfs/eewiki/minfs/ubuntu-16.04.3-minimal-armhf-2017-10-07.tar.xz
Thanks to @hokim.
Xilinx Form: https://forums.xilinx.com/t5/Embedded-Linux/can-t-get-image-from-PCam-5C-on-Ubuntu-running-on-ZYBO-Z7-20/m-p/882879#M28057
Before run this code, you must run the following commands.
@lp6m
lp6m / darknet_inference.cpp
Created January 16, 2022 16:23
run darknet inference using libdarknet.so
//g++ -std=c++11 libdarknet.so test.cpp `pkg-config --libs --cflags opencv
#include "include/darknet.h"
#include <iostream>
#include <vector>
#include <opencv2/opencv.hpp>
#include <opencv2/core.hpp>
#include <opencv2/imgcodecs.hpp>
#include <opencv2/highgui.hpp>
using namespace std;
using namespace cv;
`timescale 1 ns / 1 ps
module MyRiscv_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
package vexriscv.demo
import vexriscv.plugin._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
import spinal.lib.bus.amba4.axi.Axi4ReadOnly
import vexriscv.ip.fpu.FpuParameter
import spinal.core._
import spinal.lib._
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "sleep.h"
#define GPIO_DIRM_5_OFFSET 0XFF0A0344
#define GPIO_OEN_5_OFFSET 0xFF0A0348
#define GPIO_DATA_5_OFFSET 0xFF0A0054
#define REG(address) *(volatile unsigned int*)(address)
@lp6m
lp6m / led.v
Created December 29, 2021 15:15
Lチカモジュール
module counter(
input RESET, CLK,
output [1:0] LED
);
reg [1:0] COUNT;
reg [31:0] inner_count;
always @(posedge CLK or negedge RESET) begin
if (RESET == 1'b0) begin
COUNT <= 1;
inner_count <= 0;
#include <bits/stdc++.h>
using namespace std;
float binarize(float x){
float xx = 0.5f * x + 0.5f;
xx = min(max(xx, 0.0f), 1.0f);
return (xx >= 0.5f) ? 1.0f : -1.0f;
}
[ 80.692879] fpga_manager fpga0: writing fpga.bin to Xilinx ZynqMP FPGA Manager
[ 81.067722] ------------[ cut here ]------------
[ 81.067749] WARNING: CPU: 3 PID: 3493 at /kernel-source//drivers/clk/clk.c:622 clk_core_disable+0x88/0x90
[ 81.067752] Modules linked in: fclkcfg(O) mali(O) uio_pdrv_genirq
[ 81.067770] CPU: 3 PID: 3493 Comm: cp Tainted: G O 4.14.0-xilinx-v2018.2 #1
[ 81.067772] Hardware name: ZynqMP ZCU100 RevC (DT)
[ 81.067774] task: ffffffc06d294180 task.stack: ffffff800e670000
[ 81.067779] PC is at clk_core_disable+0x88/0x90
[ 81.067784] LR is at clk_core_disable_lock+0x20/0x38
[ 81.067786] pc : [<ffffff80084b47c8>] lr : [<ffffff80084b47f0>] pstate: 800001c5
/dts-v1/;
/ {
compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "ZynqMP ZCU100 RevC";
cpus {
#address-cells = <0x1>;
/dts-v1/;
/ {
compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "ZynqMP ZCU100 RevC";
cpus {
#address-cells = <0x1>;