Very naïve DRAM speed test

dram_naive_speedtest.py

from migen import *

from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus

class DRAMNaiveSpeedtest(Module, AutoCSR):
    def __init__(self, port, csr_controlled=True):
        self.enable = Signal()
        self.cycle_count = Signal(64)
        self.bytes_written = Signal(64)

        if csr_controlled:
            self._enable = CSRStorage(1)
            self._cycle_count = CSRStatus(64)
            self._bytes_written = CSRStatus(64)

            self.sync += [
                If(self._enable.re,
                   self.enable.eq(self._enable.storage)
                ),
            ]

            self.comb += [
                self._cycle_count.status.eq(self.cycle_count),
                self._bytes_written.status.eq(self.bytes_written),
            ]


        # Internal state
        write_addr = Signal.like(port.cmd.addr)

        # We can assign a bunch of signals combinationally
        self.comb += [
            port.cmd.we.eq(1),
            port.cmd.addr.eq(write_addr),
            port.wdata.we.eq(
                Constant((1 << (len(port.wdata.data) // 8)) - 1)),
            port.wdata.data.eq(Replicate(0xDEADBEEF, len(port.wdata.data) // 32)),
            port.wdata.valid.eq(1),
        ]

        self.submodules.fsm = FSM(reset_state="RESET")

        # Provide an accurate busy-cycle count
        self.sync += \
            If((self.fsm.ongoing("RESET") & self.enable)
               | self.fsm.ongoing("WRITE"),
                self.cycle_count.eq(self.cycle_count + 1))

        self.fsm.act("RESET",
            If(self.enable,
                port.cmd.valid.eq(1),
                If(port.cmd.ready,
                    NextValue(write_addr, write_addr + 1),
                    NextState("WRITE"),
                )
            )
        )

        self.fsm.act("WRITE",
            If(port.wdata.ready,
                NextValue(self.bytes_written,
                          self.bytes_written + (len(port.wdata.data) // 8)),
                NextState("RESET"),
            )
        )