Last active
October 11, 2022 11:46
-
-
Save luismarques/2ab5950051a08be0fadfe78f0bf6489f to your computer and use it in GitHub Desktop.
OpenTitan shadow call stack size impact
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Format: (size differences include .text and read-only data, but not .bss) | |
| % size increase | byte size increase | file | |
| # Sorted by % size increase | |
| 0.68% 2112 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_wycheproof_prog_fpga_cw310.elf | |
| 0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_fpga_cw310.elf | |
| 0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_sim_dv.elf | |
| 0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_sim_verilator.elf | |
| 0.91% 2860 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_wycheproof_prog_fpga_cw310.elf | |
| 1.20% 2612 bin/sw/device/tests/crypto/rsa_3072_verify_functest_wycheproof_prog_fpga_cw310.elf | |
| 1.20% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_wycheproof_prog_sim_dv.elf | |
| 1.20% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_wycheproof_prog_sim_verilator.elf | |
| 4.02% 2760 bin/sw/device/tests/autogen/plic_all_irqs_test_prog_fpga_cw310.elf | |
| 4.05% 2776 bin/sw/device/tests/autogen/plic_all_irqs_test_prog_sim_dv.elf | |
| 4.05% 2776 bin/sw/device/tests/autogen/plic_all_irqs_test_prog_sim_verilator.elf | |
| 5.20% 2084 bin/sw/device/tests/autogen/alert_test_prog_fpga_cw310.elf | |
| 5.20% 2084 bin/sw/device/tests/autogen/alert_test_prog_sim_dv.elf | |
| 5.20% 2084 bin/sw/device/tests/autogen/alert_test_prog_sim_verilator.elf | |
| 6.30% 816 bin/sw/device/silicon_creator/rom/rom_epmp_test_rom_prog_sim_verilator.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_sim_dv.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.elf | |
| 7.78% 594 bin/sw/device/tests/example_test_from_rom_rom_prog_sim_dv.elf | |
| 7.78% 594 bin/sw/device/tests/example_test_from_rom_rom_prog_sim_verilator.elf | |
| 8.45% 3116 bin/sw/device/tests/rstmgr_alert_info_test_prog_fpga_cw310.elf | |
| 8.52% 3140 bin/sw/device/tests/rstmgr_alert_info_test_prog_sim_verilator.elf | |
| 8.52% 3140 bin/sw/device/tests/rstmgr_alert_info_test_prog_sim_dv.elf | |
| 9.05% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_fpga_cw310.elf | |
| 9.05% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_fpga_nexysvideo.elf | |
| 9.06% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_sim_verilator.elf | |
| 9.06% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_sim_dv.elf | |
| 9.25% 1742 bin/sw/device/tests/sim_dv/flash_rma_unlocked_test_rom_prog_sim_dv.elf | |
| 9.29% 1948 bin/sw/device/tests/sim_dv/flash_init_test_rom_prog_sim_dv.elf | |
| 9.42% 2504 bin/sw/device/tests/sim_dv/uart_tx_rx_test_prog_sim_dv.elf | |
| 9.72% 3656 bin/sw/device/tests/sim_dv/all_escalation_resets_test_prog_sim_dv.elf | |
| 9.75% 2252 bin/sw/device/tests/sim_dv/spi_tx_rx_test_prog_sim_dv.elf | |
| 9.83% 3600 bin/sw/device/tests/sim_dv/pwrmgr_deep_sleep_all_wake_ups_prog_sim_dv.elf | |
| 9.85% 3204 bin/sw/device/tests/sim_dv/pwrmgr_normal_sleep_all_wake_ups_prog_sim_dv.elf | |
| 9.89% 2368 bin/sw/device/tests/alert_handler_ping_timeout_test_prog_fpga_cw310.elf | |
| 9.93% 3428 bin/sw/device/tests/sim_dv/pwrmgr_deep_sleep_all_reset_reqs_test_prog_sim_dv.elf | |
| 9.98% 2384 bin/sw/device/tests/alert_handler_ping_timeout_test_prog_sim_dv.elf | |
| 9.98% 2384 bin/sw/device/tests/alert_handler_ping_timeout_test_prog_sim_verilator.elf | |
| 10.01% 3064 bin/sw/device/tests/flash_ctrl_idle_low_power_test_prog_fpga_cw310.elf | |
| 10.07% 3080 bin/sw/device/tests/flash_ctrl_idle_low_power_test_prog_sim_verilator.elf | |
| 10.07% 3080 bin/sw/device/tests/flash_ctrl_idle_low_power_test_prog_sim_dv.elf | |
| 10.12% 3608 bin/sw/device/tests/sim_dv/pwrmgr_random_sleep_all_reset_reqs_test_prog_sim_dv.elf | |
| 10.12% 3484 bin/sw/device/tests/sim_dv/pwrmgr_normal_sleep_all_reset_reqs_test_prog_sim_dv.elf | |
| 10.18% 2516 bin/sw/device/tests/sim_dv/i2c_host_tx_rx_test_prog_sim_dv.elf | |
| 10.20% 2360 bin/sw/device/tests/sensor_ctrl_wakeup_test_prog_fpga_cw310.elf | |
| 10.28% 2376 bin/sw/device/tests/sensor_ctrl_wakeup_test_prog_sim_dv.elf | |
| 10.28% 2376 bin/sw/device/tests/sensor_ctrl_wakeup_test_prog_sim_verilator.elf | |
| 10.30% 3116 bin/sw/device/tests/clkmgr_sleep_frequency_test_prog_fpga_cw310.elf | |
| 10.38% 3136 bin/sw/device/tests/clkmgr_sleep_frequency_test_prog_sim_dv.elf | |
| 10.38% 3136 bin/sw/device/tests/clkmgr_sleep_frequency_test_prog_sim_verilator.elf | |
| 10.60% 2436 bin/sw/device/tests/sim_dv/sleep_pin_wake_test_prog_sim_dv.elf | |
| 10.68% 3288 bin/sw/device/tests/flash_ctrl_ops_test_prog_fpga_cw310.elf | |
| 10.70% 2576 bin/sw/device/tests/hmac_enc_test_prog_fpga_cw310.elf | |
| 10.72% 1552 bin/sw/device/tests/sim_dv/sram_ctrl_execution_test_main_prog_sim_dv.elf | |
| 10.72% 1972 bin/sw/device/tests/rstmgr_cpu_info_test_prog_fpga_cw310.elf | |
| 10.74% 2872 bin/sw/device/tests/entropy_src_csrng_test_prog_fpga_cw310.elf | |
| 10.75% 1972 bin/sw/device/tests/rstmgr_cpu_info_test_prog_sim_dv.elf | |
| 10.75% 1972 bin/sw/device/tests/rstmgr_cpu_info_test_prog_sim_verilator.elf | |
| 10.75% 2872 bin/sw/device/tests/entropy_src_csrng_test_prog_sim_dv.elf | |
| 10.75% 2872 bin/sw/device/tests/entropy_src_csrng_test_prog_sim_verilator.elf | |
| 10.76% 2764 bin/sw/device/tests/usbdev_test_prog_sim_verilator.elf | |
| 10.76% 3308 bin/sw/device/tests/flash_ctrl_ops_test_prog_sim_verilator.elf | |
| 10.77% 3312 bin/sw/device/tests/flash_ctrl_ops_test_prog_sim_dv.elf | |
| 10.78% 2164 bin/sw/device/tests/sim_dv/gpio_test_prog_sim_dv.elf | |
| 10.78% 2592 bin/sw/device/tests/hmac_enc_test_prog_sim_dv.elf | |
| 10.78% 2592 bin/sw/device/tests/hmac_enc_test_prog_sim_verilator.elf | |
| 10.98% 3248 bin/sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test_prog_sim_dv.elf | |
| 11.07% 2980 bin/sw/device/tests/entropy_src_edn_reqs_test_prog_fpga_cw310.elf | |
| 11.08% 2980 bin/sw/device/tests/entropy_src_edn_reqs_test_prog_sim_dv.elf | |
| 11.08% 2980 bin/sw/device/tests/entropy_src_edn_reqs_test_prog_sim_verilator.elf | |
| 11.10% 2508 bin/sw/device/tests/rv_core_ibex_nmi_irq_test_prog_fpga_cw310.elf | |
| 11.13% 2112 bin/sw/device/tests/sim_dv/lc_walkthrough_test_prog_sim_dv.elf | |
| 11.15% 2516 bin/sw/device/tests/rv_core_ibex_nmi_irq_test_prog_sim_dv.elf | |
| 11.15% 2516 bin/sw/device/tests/rv_core_ibex_nmi_irq_test_prog_sim_verilator.elf | |
| 11.19% 2328 bin/sw/device/tests/sim_dv/sensor_ctrl_status_test_prog_sim_dv.elf | |
| 11.40% 2656 bin/sw/device/tests/sim_dv/sleep_pin_mio_dio_val_test_prog_sim_dv.elf | |
| 11.43% 2728 bin/sw/device/tests/sim_dv/clkmgr_escalation_reset_test_prog_sim_dv.elf | |
| 11.47% 2176 bin/sw/device/tests/sim_dv/sysrst_ctrl_reset_test_prog_sim_dv.elf | |
| 11.58% 2708 bin/sw/device/tests/aon_timer_wdog_lc_escalate_test_prog_fpga_cw310.elf | |
| 11.60% 1684 bin/sw/device/silicon_creator/rom/e2e/rom_e2e_static_critical_prog_fpga_cw310.elf | |
| 11.62% 1684 bin/sw/device/silicon_creator/rom/e2e/rom_e2e_static_critical_prog_sim_dv.elf | |
| 11.62% 1684 bin/sw/device/silicon_creator/rom/e2e/rom_e2e_static_critical_prog_sim_verilator.elf | |
| 11.69% 2732 bin/sw/device/tests/aon_timer_wdog_lc_escalate_test_prog_sim_dv.elf | |
| 11.69% 2732 bin/sw/device/tests/aon_timer_wdog_lc_escalate_test_prog_sim_verilator.elf | |
| 11.97% 2224 bin/sw/device/tests/pwrmgr_sleep_disabled_test_prog_fpga_cw310.elf | |
| 11.97% 2220 bin/sw/device/tests/pwrmgr_sleep_disabled_test_prog_sim_dv.elf | |
| 11.97% 2220 bin/sw/device/tests/pwrmgr_sleep_disabled_test_prog_sim_verilator.elf | |
| 12.07% 1944 bin/sw/device/tests/aes_idle_test_prog_fpga_cw310.elf | |
| 12.09% 2944 bin/sw/device/tests/alert_handler_reverse_ping_in_deep_sleep_test_prog_fpga_cw310.elf | |
| 12.10% 1944 bin/sw/device/tests/aes_idle_test_prog_sim_dv.elf | |
| 12.10% 1944 bin/sw/device/tests/aes_idle_test_prog_sim_verilator.elf | |
| 12.12% 1516 bin/sw/device/tests/rv_core_ibex_address_translation_test_prog_fpga_cw310.elf | |
| 12.12% 1808 bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf | |
| 12.14% 1812 bin/sw/device/examples/hello_world/hello_world_fpga_cw310.elf | |
| 12.14% 1812 bin/sw/device/examples/hello_world/hello_world_fpga_nexysvideo.elf | |
| 12.14% 1516 bin/sw/device/tests/rv_core_ibex_address_translation_test_prog_sim_dv.elf | |
| 12.14% 1516 bin/sw/device/tests/rv_core_ibex_address_translation_test_prog_sim_verilator.elf | |
| 12.15% 1812 bin/sw/device/examples/hello_world/hello_world_sim_dv.elf | |
| 12.19% 2964 bin/sw/device/tests/alert_handler_reverse_ping_in_deep_sleep_test_prog_sim_dv.elf | |
| 12.21% 3220 bin/sw/device/tests/clkmgr_off_peri_test_prog_sim_verilator.elf | |
| 12.21% 3220 bin/sw/device/tests/clkmgr_off_peri_test_prog_sim_dv.elf | |
| 12.21% 3224 bin/sw/device/tests/clkmgr_off_peri_test_prog_fpga_cw310.elf | |
| 12.27% 3576 bin/sw/device/tests/aes_sideload_test_prog_fpga_cw310.elf | |
| 12.28% 3576 bin/sw/device/tests/aes_sideload_test_prog_sim_verilator.elf | |
| 12.29% 3576 bin/sw/device/tests/aes_sideload_test_prog_sim_dv.elf | |
| 12.39% 2104 bin/sw/device/tests/kmac_smoketest_prog_fpga_cw310.elf | |
| 12.42% 2104 bin/sw/device/tests/kmac_smoketest_prog_sim_dv.elf | |
| 12.42% 2104 bin/sw/device/tests/kmac_smoketest_prog_sim_verilator.elf | |
| 12.42% 2856 bin/sw/device/tests/flash_ctrl_test_prog_fpga_cw310.elf | |
| 12.44% 2856 bin/sw/device/tests/flash_ctrl_test_prog_sim_dv.elf | |
| 12.46% 2860 bin/sw/device/tests/flash_ctrl_test_prog_sim_verilator.elf | |
| 12.52% 2964 bin/sw/device/tests/otbn_ecdsa_op_irq_test_prog_fpga_cw310.elf | |
| 12.54% 2812 bin/sw/device/tests/sim_dv/pwrmgr_b2b_sleep_reset_test_prog_sim_dv.elf | |
| 12.57% 2968 bin/sw/device/tests/otbn_ecdsa_op_irq_test_prog_sim_dv.elf | |
| 12.57% 2968 bin/sw/device/tests/otbn_ecdsa_op_irq_test_prog_sim_verilator.elf | |
| 12.61% 2748 bin/sw/device/tests/ast_clk_outs_test_prog_sim_verilator.elf | |
| 12.61% 2752 bin/sw/device/tests/ast_clk_outs_test_prog_fpga_cw310.elf | |
| 12.63% 2752 bin/sw/device/tests/ast_clk_outs_test_prog_sim_dv.elf | |
| 12.71% 1948 bin/sw/device/tests/aes_entropy_test_prog_fpga_cw310.elf | |
| 12.71% 2756 bin/sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test_prog_sim_dv.elf | |
| 12.71% 1944 bin/sw/device/tests/aes_entropy_test_prog_sim_dv.elf | |
| 12.71% 1944 bin/sw/device/tests/aes_entropy_test_prog_sim_verilator.elf | |
| 12.74% 2288 bin/sw/device/tests/hmac_enc_idle_test_prog_fpga_cw310.elf | |
| 12.74% 2284 bin/sw/device/tests/hmac_enc_idle_test_prog_sim_dv.elf | |
| 12.74% 2284 bin/sw/device/tests/hmac_enc_idle_test_prog_sim_verilator.elf | |
| 12.77% 2048 bin/sw/device/tests/kmac_mode_kmac_test_prog_fpga_cw310.elf | |
| 12.83% 2052 bin/sw/device/tests/kmac_mode_kmac_test_prog_sim_dv.elf | |
| 12.83% 2052 bin/sw/device/tests/kmac_mode_kmac_test_prog_sim_verilator.elf | |
| 12.91% 2236 bin/sw/device/tests/sim_dv/adc_ctrl_sleep_debug_cable_wakeup_test_prog_sim_dv.elf | |
| 12.92% 2636 bin/sw/device/tests/sleep_pwm_pulses_test_prog_fpga_cw310.elf | |
| 12.94% 2636 bin/sw/device/tests/sleep_pwm_pulses_test_prog_sim_dv.elf | |
| 12.94% 2636 bin/sw/device/tests/sleep_pwm_pulses_test_prog_sim_verilator.elf | |
| 12.98% 2120 bin/sw/device/tests/sim_dv/lc_walkthrough_testunlocks_test_prog_sim_dv.elf | |
| 13.02% 2660 bin/sw/device/tests/sensor_ctrl_alert_test_prog_fpga_cw310.elf | |
| 13.02% 2644 bin/sw/device/tests/aon_timer_irq_test_prog_fpga_cw310.elf | |
| 13.06% 2116 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_hardcoded_prog_fpga_cw310.elf | |
| 13.07% 2112 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_hardcoded_prog_sim_dv.elf | |
| 13.07% 2112 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_hardcoded_prog_sim_verilator.elf | |
| 13.12% 2660 bin/sw/device/tests/aon_timer_irq_test_prog_sim_dv.elf | |
| 13.12% 2660 bin/sw/device/tests/aon_timer_irq_test_prog_sim_verilator.elf | |
| 13.14% 2680 bin/sw/device/tests/sensor_ctrl_alert_test_prog_sim_dv.elf | |
| 13.14% 2680 bin/sw/device/tests/sensor_ctrl_alert_test_prog_sim_verilator.elf | |
| 13.38% 2292 bin/sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test_prog_sim_dv.elf | |
| 13.43% 2008 bin/sw/device/tests/rv_plic_smoketest_prog_sim_verilator.elf | |
| 13.43% 2008 bin/sw/device/tests/rv_plic_smoketest_prog_fpga_cw310.elf | |
| 13.45% 1940 bin/sw/device/tests/aes_smoketest_prog_fpga_cw310.elf | |
| 13.46% 2012 bin/sw/device/tests/rv_plic_smoketest_prog_sim_dv.elf | |
| 13.46% 1936 bin/sw/device/tests/aes_smoketest_prog_sim_dv.elf | |
| 13.46% 1936 bin/sw/device/tests/aes_smoketest_prog_sim_verilator.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_aes_trans_test_prog_fpga_cw310.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_hmac_trans_test_prog_fpga_cw310.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_kmac_trans_test_prog_fpga_cw310.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_otbn_trans_test_prog_fpga_cw310.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_aes_trans_test_prog_sim_verilator.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_hmac_trans_test_prog_sim_verilator.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_kmac_trans_test_prog_sim_verilator.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_otbn_trans_test_prog_sim_verilator.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_aes_trans_test_prog_sim_dv.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_hmac_trans_test_prog_sim_dv.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_kmac_trans_test_prog_sim_dv.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_otbn_trans_test_prog_sim_dv.elf | |
| 13.64% 2852 bin/sw/device/tests/sim_dv/inject_scramble_seed_prog_sim_dv.elf | |
| 13.73% 2408 bin/sw/device/tests/sram_ctrl_sleep_sram_ret_contents_test_prog_fpga_cw310.elf | |
| 13.76% 2408 bin/sw/device/tests/sram_ctrl_sleep_sram_ret_contents_test_prog_sim_dv.elf | |
| 13.76% 2408 bin/sw/device/tests/sram_ctrl_sleep_sram_ret_contents_test_prog_sim_verilator.elf | |
| 13.89% 1404 bin/sw/device/tests/sram_ctrl_execution_test_prog_fpga_cw310.elf | |
| 13.93% 1404 bin/sw/device/tests/sram_ctrl_execution_test_prog_sim_dv.elf | |
| 13.93% 1404 bin/sw/device/tests/sram_ctrl_execution_test_prog_sim_verilator.elf | |
| 14.00% 2804 bin/sw/device/tests/otbn_randomness_test_prog_sim_dv.elf | |
| 14.00% 2804 bin/sw/device/tests/otbn_randomness_test_prog_sim_verilator.elf | |
| 14.01% 2808 bin/sw/device/tests/otbn_randomness_test_prog_fpga_cw310.elf | |
| 14.24% 3736 bin/sw/device/sca/ecc384_serial_fpga_cw310.elf | |
| 14.24% 3736 bin/sw/device/sca/ecc384_serial_fpga_nexysvideo.elf | |
| 14.25% 3736 bin/sw/device/sca/ecc384_serial_sim_dv.elf | |
| 14.25% 3736 bin/sw/device/sca/ecc384_serial_sim_verilator.elf | |
| 14.26% 2924 bin/sw/device/tests/otbn_rsa_test_prog_fpga_cw310.elf | |
| 14.28% 2924 bin/sw/device/tests/otbn_rsa_test_prog_sim_dv.elf | |
| 14.28% 2924 bin/sw/device/tests/otbn_rsa_test_prog_sim_verilator.elf | |
| 14.31% 2352 bin/sw/device/tests/sim_dv/alert_handler_escalation_test_prog_sim_dv.elf | |
| 14.34% 2860 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_hardcoded_prog_fpga_cw310.elf | |
| 14.39% 2864 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_hardcoded_prog_sim_dv.elf | |
| 14.39% 2864 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_hardcoded_prog_sim_verilator.elf | |
| 14.43% 2528 bin/sw/device/tests/pwrmgr_smoketest_prog_fpga_cw310.elf | |
| 14.44% 2524 bin/sw/device/tests/pwrmgr_smoketest_prog_sim_dv.elf | |
| 14.44% 2524 bin/sw/device/tests/pwrmgr_smoketest_prog_sim_verilator.elf | |
| 14.45% 2404 bin/sw/device/tests/aon_timer_sleep_wdog_sleep_pause_test_prog_fpga_cw310.elf | |
| 14.48% 2404 bin/sw/device/tests/aon_timer_sleep_wdog_sleep_pause_test_prog_sim_verilator.elf | |
| 14.48% 2936 bin/sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test_prog_sim_dv.elf | |
| 14.48% 2528 bin/sw/device/tests/clkmgr_reset_frequency_test_prog_fpga_cw310.elf | |
| 14.51% 2528 bin/sw/device/tests/clkmgr_reset_frequency_test_prog_sim_verilator.elf | |
| 14.51% 2408 bin/sw/device/tests/aon_timer_sleep_wdog_sleep_pause_test_prog_sim_dv.elf | |
| 14.51% 2528 bin/sw/device/tests/clkmgr_reset_frequency_test_prog_sim_dv.elf | |
| 14.62% 3744 bin/sw/device/tests/sim_dv/keymgr_sideload_kmac_test_prog_sim_dv.elf | |
| 14.74% 2060 bin/sw/device/tests/kmac_idle_test_prog_fpga_cw310.elf | |
| 14.74% 2000 bin/sw/device/tests/sim_dv/alert_handler_entropy_test_prog_sim_dv.elf | |
| 14.74% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_hardcoded_prog_fpga_cw310.elf | |
| 14.76% 2512 bin/sw/device/tests/otbn_irq_test_prog_fpga_cw310.elf | |
| 14.77% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_hardcoded_prog_sim_dv.elf | |
| 14.77% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_hardcoded_prog_sim_verilator.elf | |
| 14.78% 2172 bin/sw/device/tests/aon_timer_smoketest_prog_fpga_cw310.elf | |
| 14.78% 2512 bin/sw/device/tests/otbn_irq_test_prog_sim_dv.elf | |
| 14.78% 2512 bin/sw/device/tests/otbn_irq_test_prog_sim_verilator.elf | |
| 14.81% 2172 bin/sw/device/tests/aon_timer_smoketest_prog_sim_dv.elf | |
| 14.81% 2064 bin/sw/device/tests/kmac_idle_test_prog_sim_dv.elf | |
| 14.81% 2064 bin/sw/device/tests/kmac_idle_test_prog_sim_verilator.elf | |
| 14.84% 2176 bin/sw/device/tests/aon_timer_smoketest_prog_sim_verilator.elf | |
| 14.88% 2588 bin/sw/device/tests/sim_dv/csrng_fuse_en_sw_app_read_prog_sim_dv.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_fast_test_prog_sim_dv.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_fast_test_prog_sim_verilator.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_slow_test_prog_sim_dv.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_slow_test_prog_sim_verilator.elf | |
| 14.89% 2468 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_fast_test_prog_fpga_cw310.elf | |
| 14.89% 2468 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_slow_test_prog_fpga_cw310.elf | |
| 14.96% 2180 bin/sw/device/tests/sim_dv/ast_usb_clk_calib_prog_sim_dv.elf | |
| 15.03% 2408 bin/sw/device/tests/aon_timer_wdog_bite_reset_test_prog_fpga_cw310.elf | |
| 15.03% 2404 bin/sw/device/tests/aon_timer_wdog_bite_reset_test_prog_sim_verilator.elf | |
| 15.06% 2408 bin/sw/device/tests/aon_timer_wdog_bite_reset_test_prog_sim_dv.elf | |
| 15.06% 3080 bin/sw/device/silicon_creator/rom/rom_sim_dv.elf | |
| 15.06% 3080 bin/sw/device/silicon_creator/rom/rom_sim_verilator.elf | |
| 15.07% 2764 bin/sw/device/tests/otbn_smoketest_prog_fpga_cw310.elf | |
| 15.08% 2760 bin/sw/device/tests/otbn_smoketest_prog_sim_dv.elf | |
| 15.08% 2760 bin/sw/device/tests/otbn_smoketest_prog_sim_verilator.elf | |
| 15.10% 1276 bin/sw/device/tests/crt_test_prog_fpga_cw310.elf | |
| 15.16% 1276 bin/sw/device/tests/crt_test_prog_sim_dv.elf | |
| 15.16% 1276 bin/sw/device/tests/crt_test_prog_sim_verilator.elf | |
| 15.23% 2352 bin/sw/device/tests/sim_dv/entropy_src_fuse_en_fw_read_test_prog_sim_dv.elf | |
| 15.24% 2076 bin/sw/device/tests/sim_dv/sram_ctrl_ret_scrambled_access_test_prog_sim_dv.elf | |
| 15.27% 4092 bin/sw/device/tests/sim_dv/keymgr_sideload_otbn_test_prog_sim_dv.elf | |
| 15.31% 2292 bin/sw/device/tests/pwrmgr_wdog_reset_reqs_test_prog_fpga_cw310.elf | |
| 15.34% 2292 bin/sw/device/tests/pwrmgr_wdog_reset_reqs_test_prog_sim_verilator.elf | |
| 15.35% 2292 bin/sw/device/tests/pwrmgr_wdog_reset_reqs_test_prog_sim_dv.elf | |
| 15.36% 2036 bin/sw/device/tests/rv_timer_smoketest_prog_fpga_cw310.elf | |
| 15.37% 2032 bin/sw/device/tests/rv_timer_smoketest_prog_sim_dv.elf | |
| 15.37% 2032 bin/sw/device/tests/rv_timer_smoketest_prog_sim_verilator.elf | |
| 15.40% 3624 bin/sw/device/tests/sim_dv/keymgr_key_derivation_test_prog_sim_dv.elf | |
| 15.43% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_hardcoded_prog_sim_dv.elf | |
| 15.43% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_hardcoded_prog_sim_verilator.elf | |
| 15.44% 3196 bin/sw/device/silicon_creator/rom/rom_fpga_cw310.elf | |
| 15.44% 3196 bin/sw/device/silicon_creator/rom/rom_fpga_nexysvideo.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_sim_verilator.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_sim_verilator.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_sim_verilator.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_sim_verilator.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_fpga_nexysvideo.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_fpga_nexysvideo.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_fpga_nexysvideo.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_fpga_nexysvideo.elf | |
| 15.55% 2024 bin/third_party/riscv-compliance/I-JALR-01_prog_fpga_cw310.elf | |
| 15.55% 2024 bin/third_party/riscv-compliance/I-JALR-01_prog_sim_dv.elf | |
| 15.55% 2024 bin/third_party/riscv-compliance/I-JALR-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGE-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGE-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGE-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGEU-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGEU-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGEU-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLT-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLT-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLT-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLTU-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLTU-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLTU-01_prog_sim_verilator.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BEQ-01_prog_fpga_cw310.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BEQ-01_prog_sim_dv.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BEQ-01_prog_sim_verilator.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BNE-01_prog_fpga_cw310.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BNE-01_prog_sim_dv.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BNE-01_prog_sim_verilator.elf | |
| 15.63% 2172 bin/sw/device/tests/entropy_src_kat_test_prog_fpga_cw310.elf | |
| 15.64% 3672 bin/sw/device/sca/ecc_serial_fpga_cw310.elf | |
| 15.64% 3672 bin/sw/device/sca/ecc_serial_fpga_nexysvideo.elf | |
| 15.66% 3672 bin/sw/device/sca/ecc_serial_sim_dv.elf | |
| 15.66% 3672 bin/sw/device/sca/ecc_serial_sim_verilator.elf | |
| 15.71% 2176 bin/sw/device/tests/entropy_src_kat_test_prog_sim_dv.elf | |
| 15.71% 2176 bin/sw/device/tests/entropy_src_kat_test_prog_sim_verilator.elf | |
| 15.72% 3084 bin/sw/device/tests/flash_ctrl_clock_freqs_test_prog_fpga_cw310.elf | |
| 15.77% 2796 bin/sw/device/tests/crypto/ecdsa_p256_functest_prog_fpga_cw310.elf | |
| 15.80% 3096 bin/sw/device/tests/flash_ctrl_clock_freqs_test_prog_sim_verilator.elf | |
| 15.81% 2796 bin/sw/device/tests/crypto/ecdsa_p256_functest_prog_sim_dv.elf | |
| 15.81% 2796 bin/sw/device/tests/crypto/ecdsa_p256_functest_prog_sim_verilator.elf | |
| 15.83% 3100 bin/sw/device/tests/flash_ctrl_clock_freqs_test_prog_sim_dv.elf | |
| 15.83% 2024 bin/third_party/riscv-compliance/I-SW-01_prog_fpga_cw310.elf | |
| 15.83% 2024 bin/third_party/riscv-compliance/I-SW-01_prog_sim_dv.elf | |
| 15.83% 2024 bin/third_party/riscv-compliance/I-SW-01_prog_sim_verilator.elf | |
| 15.84% 2020 bin/third_party/riscv-compliance/I-JAL-01_prog_fpga_cw310.elf | |
| 15.84% 2020 bin/third_party/riscv-compliance/I-JAL-01_prog_sim_dv.elf | |
| 15.84% 2020 bin/third_party/riscv-compliance/I-JAL-01_prog_sim_verilator.elf | |
| 15.92% 2024 bin/third_party/riscv-compliance/I-AUIPC-01_prog_fpga_cw310.elf | |
| 15.92% 2024 bin/third_party/riscv-compliance/I-AUIPC-01_prog_sim_dv.elf | |
| 15.92% 2024 bin/third_party/riscv-compliance/I-AUIPC-01_prog_sim_verilator.elf | |
| 15.99% 2116 bin/sw/device/tests/entropy_src_fw_ovr_test_prog_fpga_cw310.elf | |
| 15.99% 2000 bin/sw/device/tests/entropy_src_smoketest_prog_fpga_cw310.elf | |
| 16.00% 2160 bin/sw/device/tests/kmac_mode_cshake_test_prog_fpga_cw310.elf | |
| 16.00% 2112 bin/sw/device/tests/entropy_src_fw_ovr_test_prog_sim_dv.elf | |
| 16.00% 2112 bin/sw/device/tests/entropy_src_fw_ovr_test_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LB-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LB-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LB-01_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LBU-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LBU-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LBU-01_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LH-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LH-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LH-01_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LHU-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LHU-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LHU-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-AND-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-AND-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-AND-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-OR-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-OR-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-OR-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLT-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLT-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLT-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLTU-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLTU-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLTU-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SUB-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SUB-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SUB-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-XOR-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-XOR-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-XOR-01_prog_sim_verilator.elf | |
| 16.06% 2020 bin/third_party/riscv-compliance/I-ADD-01_prog_fpga_cw310.elf | |
| 16.06% 2020 bin/third_party/riscv-compliance/I-ADD-01_prog_sim_dv.elf | |
| 16.06% 2020 bin/third_party/riscv-compliance/I-ADD-01_prog_sim_verilator.elf | |
| 16.07% 2024 bin/third_party/riscv-compliance/I-LW-01_prog_fpga_cw310.elf | |
| 16.07% 2024 bin/third_party/riscv-compliance/I-LW-01_prog_sim_dv.elf | |
| 16.07% 2024 bin/third_party/riscv-compliance/I-LW-01_prog_sim_verilator.elf | |
| 16.08% 2004 bin/sw/device/tests/entropy_src_smoketest_prog_sim_dv.elf | |
| 16.08% 2004 bin/sw/device/tests/entropy_src_smoketest_prog_sim_verilator.elf | |
| 16.09% 2164 bin/sw/device/tests/kmac_mode_cshake_test_prog_sim_dv.elf | |
| 16.09% 2164 bin/sw/device/tests/kmac_mode_cshake_test_prog_sim_verilator.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SB-01_prog_fpga_cw310.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SB-01_prog_sim_dv.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SB-01_prog_sim_verilator.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SH-01_prog_fpga_cw310.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SH-01_prog_sim_dv.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SH-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-IO-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-IO-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-IO-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SLL-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SLL-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SLL-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRA-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRA-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRA-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRL-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRL-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRL-01_prog_sim_verilator.elf | |
| 16.15% 2020 bin/third_party/riscv-compliance/I-RF_width-01_prog_fpga_cw310.elf | |
| 16.15% 2020 bin/third_party/riscv-compliance/I-RF_width-01_prog_sim_dv.elf | |
| 16.15% 2020 bin/third_party/riscv-compliance/I-RF_width-01_prog_sim_verilator.elf | |
| 16.16% 2056 bin/sw/device/tests/sim_dv/pwrmgr_usbdev_smoketest_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ANDI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ANDI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ANDI-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ORI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ORI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ORI-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLLI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLLI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLLI-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTI-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTIU-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTIU-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTIU-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRAI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRAI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRAI-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRLI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRLI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRLI-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-XORI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-XORI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-XORI-01_prog_sim_verilator.elf | |
| 16.23% 2024 bin/third_party/riscv-compliance/I-RF_size-01_prog_fpga_cw310.elf | |
| 16.23% 2024 bin/third_party/riscv-compliance/I-RF_size-01_prog_sim_dv.elf | |
| 16.23% 2024 bin/third_party/riscv-compliance/I-RF_size-01_prog_sim_verilator.elf | |
| 16.25% 2560 bin/sw/device/tests/crypto/ecdsa_p256_verify_functest_hardcoded_prog_sim_dv.elf | |
| 16.25% 2560 bin/sw/device/tests/crypto/ecdsa_p256_verify_functest_hardcoded_prog_sim_verilator.elf | |
| 16.25% 2024 bin/third_party/riscv-compliance/I-ADDI-01_prog_fpga_cw310.elf | |
| 16.25% 2024 bin/third_party/riscv-compliance/I-ADDI-01_prog_sim_dv.elf | |
| 16.25% 2024 bin/third_party/riscv-compliance/I-ADDI-01_prog_sim_verilator.elf | |
| 16.28% 3664 bin/sw/device/silicon_creator/lib/drivers/keymgr_functest_prog_fpga_cw310.elf | |
| 16.29% 2332 bin/sw/device/tests/sim_dv/spi_host_tx_rx_test_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIVU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIVU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIVU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIV_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIV_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIV_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHSU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHSU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHSU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULH_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULH_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULH_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MUL_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MUL_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MUL_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REMU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REMU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REMU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REM_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REM_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REM_prog_sim_verilator.elf | |
| 16.31% 3668 bin/sw/device/silicon_creator/lib/drivers/keymgr_functest_prog_sim_verilator.elf | |
| 16.32% 3668 bin/sw/device/silicon_creator/lib/drivers/keymgr_functest_prog_sim_dv.elf | |
| 16.39% 2020 bin/third_party/riscv-compliance/I-LUI-01_prog_fpga_cw310.elf | |
| 16.39% 2020 bin/third_party/riscv-compliance/I-LUI-01_prog_sim_dv.elf | |
| 16.39% 2020 bin/third_party/riscv-compliance/I-LUI-01_prog_sim_verilator.elf | |
| 16.39% 2060 bin/sw/device/tests/sim_dv/clkmgr_external_clk_src_for_lc_test_prog_sim_dv.elf | |
| 16.41% 2060 bin/sw/device/tests/sim_dv/lc_ctrl_transition_test_prog_sim_dv.elf | |
| 16.49% 2292 bin/sw/device/tests/hmac_smoketest_prog_fpga_cw310.elf | |
| 16.55% 2060 bin/sw/device/tests/sim_dv/lc_ctrl_kmac_reset_test_prog_sim_dv.elf | |
| 16.55% 2356 bin/sw/device/tests/sim_dv/pwrmgr_sleep_power_glitch_test_prog_sim_dv.elf | |
| 16.57% 2000 bin/sw/device/tests/clkmgr_smoketest_prog_fpga_cw310.elf | |
| 16.57% 2296 bin/sw/device/tests/hmac_smoketest_prog_sim_dv.elf | |
| 16.57% 2296 bin/sw/device/tests/hmac_smoketest_prog_sim_verilator.elf | |
| 16.58% 2224 bin/sw/device/tests/sim_dv/sysrst_ctrl_outputs_test_prog_sim_dv.elf | |
| 16.60% 2020 bin/third_party/riscv-compliance/C-SW_prog_fpga_cw310.elf | |
| 16.60% 2020 bin/third_party/riscv-compliance/C-SW_prog_sim_dv.elf | |
| 16.60% 2020 bin/third_party/riscv-compliance/C-SW_prog_sim_verilator.elf | |
| 16.62% 2116 bin/sw/device/tests/sim_dv/lc_ctrl_program_error_prog_sim_dv.elf | |
| 16.62% 2000 bin/sw/device/tests/clkmgr_smoketest_prog_sim_dv.elf | |
| 16.62% 2000 bin/sw/device/tests/clkmgr_smoketest_prog_sim_verilator.elf | |
| 16.62% 2024 bin/third_party/riscv-compliance/C-SWSP_prog_fpga_cw310.elf | |
| 16.62% 2024 bin/third_party/riscv-compliance/C-SWSP_prog_sim_dv.elf | |
| 16.62% 2024 bin/third_party/riscv-compliance/C-SWSP_prog_sim_verilator.elf | |
| 16.63% 2356 bin/sw/device/tests/sim_dv/pwrmgr_deep_sleep_power_glitch_test_prog_sim_dv.elf | |
| 16.64% 2020 bin/third_party/riscv-compliance/I-CSRRC-01_prog_fpga_cw310.elf | |
| 16.64% 2020 bin/third_party/riscv-compliance/I-CSRRC-01_prog_sim_dv.elf | |
| 16.64% 2020 bin/third_party/riscv-compliance/I-CSRRC-01_prog_sim_verilator.elf | |
| 16.65% 2020 bin/third_party/riscv-compliance/I-CSRRS-01_prog_fpga_cw310.elf | |
| 16.65% 2020 bin/third_party/riscv-compliance/I-CSRRS-01_prog_sim_dv.elf | |
| 16.65% 2020 bin/third_party/riscv-compliance/I-CSRRS-01_prog_sim_verilator.elf | |
| 16.70% 3532 bin/sw/device/silicon_creator/lib/boot_data_functest_prog_fpga_cw310.elf | |
| 16.73% 3532 bin/sw/device/silicon_creator/lib/boot_data_functest_prog_sim_dv.elf | |
| 16.73% 3532 bin/sw/device/silicon_creator/lib/boot_data_functest_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-ADD_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-ADD_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-ADD_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-AND_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-AND_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-AND_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-MV_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-MV_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-MV_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-OR_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-OR_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-SUB_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-SUB_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-SUB_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-XOR_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-XOR_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-XOR_prog_sim_verilator.elf | |
| 16.81% 2024 bin/third_party/riscv-compliance/I-CSRRW-01_prog_fpga_cw310.elf | |
| 16.81% 2024 bin/third_party/riscv-compliance/I-CSRRW-01_prog_sim_dv.elf | |
| 16.81% 2024 bin/third_party/riscv-compliance/I-CSRRW-01_prog_sim_verilator.elf | |
| 16.82% 2000 bin/sw/device/lib/crypto/drivers/aes_test_prog_fpga_cw310.elf | |
| 16.83% 2112 bin/sw/device/tests/otp_ctrl_smoketest_prog_fpga_cw310.elf | |
| 16.83% 2024 bin/third_party/riscv-compliance/I-DELAY_SLOTS-01_prog_fpga_cw310.elf | |
| 16.83% 2024 bin/third_party/riscv-compliance/I-DELAY_SLOTS-01_prog_sim_dv.elf | |
| 16.83% 2024 bin/third_party/riscv-compliance/I-DELAY_SLOTS-01_prog_sim_verilator.elf | |
| 16.83% 1944 bin/sw/device/tests/sim_dv/sysrst_ctrl_inputs_test_prog_sim_dv.elf | |
| 16.84% 2116 bin/sw/device/tests/lc_ctrl_otp_hw_cfg_test_prog_fpga_cw310.elf | |
| 16.84% 1944 bin/sw/device/tests/entropy_src_ast_rng_req_test_prog_fpga_cw310.elf | |
| 16.84% 2032 bin/sw/device/tests/rv_core_ibex_rnd_test_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ADDI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ADDI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ADDI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ANDI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ANDI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ANDI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LUI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LUI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LUI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SLLI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SLLI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SLLI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRAI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRAI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRAI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRLI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRLI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRLI_prog_sim_verilator.elf | |
| 16.86% 2112 bin/sw/device/tests/lc_ctrl_otp_hw_cfg_test_prog_sim_dv.elf | |
| 16.86% 2112 bin/sw/device/tests/lc_ctrl_otp_hw_cfg_test_prog_sim_verilator.elf | |
| 16.87% 2020 bin/third_party/riscv-compliance/I-CSRRCI-01_prog_fpga_cw310.elf | |
| 16.87% 2020 bin/third_party/riscv-compliance/I-CSRRCI-01_prog_sim_dv.elf | |
| 16.87% 2020 bin/third_party/riscv-compliance/I-CSRRCI-01_prog_sim_verilator.elf | |
| 16.88% 2000 bin/sw/device/lib/crypto/drivers/aes_test_prog_sim_dv.elf | |
| 16.88% 2000 bin/sw/device/lib/crypto/drivers/aes_test_prog_sim_verilator.elf | |
| 16.90% 3040 bin/sw/device/silicon_creator/lib/sigverify/sigverify_functest_prog_fpga_cw310.elf | |
| 16.90% 1944 bin/sw/device/tests/entropy_src_ast_rng_req_test_prog_sim_dv.elf | |
| 16.90% 1944 bin/sw/device/tests/entropy_src_ast_rng_req_test_prog_sim_verilator.elf | |
| 16.91% 2024 bin/third_party/riscv-compliance/I-CSRRSI-01_prog_fpga_cw310.elf | |
| 16.91% 2024 bin/third_party/riscv-compliance/I-CSRRSI-01_prog_sim_dv.elf | |
| 16.91% 2024 bin/third_party/riscv-compliance/I-CSRRSI-01_prog_sim_verilator.elf | |
| 16.92% 2116 bin/sw/device/tests/otp_ctrl_smoketest_prog_sim_dv.elf | |
| 16.92% 2116 bin/sw/device/tests/otp_ctrl_smoketest_prog_sim_verilator.elf | |
| 16.93% 2172 bin/sw/device/tests/sim_dv/sram_ctrl_main_scrambled_access_test_prog_sim_dv.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JALR_prog_fpga_cw310.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JALR_prog_sim_dv.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JALR_prog_sim_verilator.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JR_prog_fpga_cw310.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JR_prog_sim_dv.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JR_prog_sim_verilator.elf | |
| 16.93% 2036 bin/sw/device/tests/rv_core_ibex_rnd_test_prog_sim_dv.elf | |
| 16.93% 2036 bin/sw/device/tests/rv_core_ibex_rnd_test_prog_sim_verilator.elf | |
| 16.93% 3040 bin/sw/device/silicon_creator/lib/sigverify/sigverify_functest_prog_sim_dv.elf | |
| 16.93% 3040 bin/sw/device/silicon_creator/lib/sigverify/sigverify_functest_prog_sim_verilator.elf | |
| 16.96% 2020 bin/third_party/riscv-compliance/I-ECALL-01_prog_fpga_cw310.elf | |
| 16.96% 2020 bin/third_party/riscv-compliance/I-ECALL-01_prog_sim_dv.elf | |
| 16.96% 2020 bin/third_party/riscv-compliance/I-ECALL-01_prog_sim_verilator.elf | |
| 16.97% 2020 bin/third_party/riscv-compliance/C-LWSP_prog_fpga_cw310.elf | |
| 16.97% 2020 bin/third_party/riscv-compliance/C-LWSP_prog_sim_dv.elf | |
| 16.97% 2020 bin/third_party/riscv-compliance/C-LWSP_prog_sim_verilator.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-JAL_prog_fpga_cw310.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-JAL_prog_sim_dv.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-JAL_prog_sim_verilator.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-J_prog_fpga_cw310.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-J_prog_sim_dv.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-J_prog_sim_verilator.elf | |
| 16.99% 2480 bin/sw/device/tests/csrng_kat_test_prog_fpga_cw310.elf | |
| 17.01% 2024 bin/third_party/riscv-compliance/C-BEQZ_prog_fpga_cw310.elf | |
| 17.01% 2024 bin/third_party/riscv-compliance/C-BEQZ_prog_sim_dv.elf | |
| 17.01% 2024 bin/third_party/riscv-compliance/C-BEQZ_prog_sim_verilator.elf | |
| 17.01% 2020 bin/third_party/riscv-compliance/C-BNEZ_prog_fpga_cw310.elf | |
| 17.01% 2020 bin/third_party/riscv-compliance/C-BNEZ_prog_sim_dv.elf | |
| 17.01% 2020 bin/third_party/riscv-compliance/C-BNEZ_prog_sim_verilator.elf | |
| 17.03% 2024 bin/third_party/riscv-compliance/C-LW_prog_fpga_cw310.elf | |
| 17.03% 2024 bin/third_party/riscv-compliance/C-LW_prog_sim_dv.elf | |
| 17.03% 2024 bin/third_party/riscv-compliance/C-LW_prog_sim_verilator.elf | |
| 17.03% 2480 bin/sw/device/tests/csrng_kat_test_prog_sim_dv.elf | |
| 17.03% 2480 bin/sw/device/tests/csrng_kat_test_prog_sim_verilator.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-CSRRWI-01_prog_fpga_cw310.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-CSRRWI-01_prog_sim_dv.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-CSRRWI-01_prog_sim_verilator.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-ENDIANESS-01_prog_fpga_cw310.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-ENDIANESS-01_prog_sim_dv.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-ENDIANESS-01_prog_sim_verilator.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI16SP_prog_fpga_cw310.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI16SP_prog_sim_dv.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI16SP_prog_sim_verilator.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI4SPN_prog_fpga_cw310.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI4SPN_prog_sim_dv.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI4SPN_prog_sim_verilator.elf | |
| 17.31% 2060 bin/sw/device/tests/sim_dv/rv_dm_ndm_reset_req_prog_sim_dv.elf | |
| 17.33% 1940 bin/sw/device/tests/uart_smoketest_prog_fpga_cw310.elf | |
| 17.33% 1940 bin/sw/device/tests/uart_smoketest_signed_prog_fpga_cw310.elf | |
| 17.34% 2100 bin/sw/device/tests/plic_sw_irq_test_prog_fpga_cw310.elf | |
| 17.37% 2100 bin/sw/device/tests/plic_sw_irq_test_prog_sim_verilator.elf | |
| 17.37% 2292 bin/sw/device/tests/csrng_smoketest_prog_fpga_cw310.elf | |
| 17.38% 2112 bin/sw/device/tests/spi_host_smoketest_prog_fpga_cw310.elf | |
| 17.38% 2644 bin/sw/device/tests/crypto/aes_gcm_timing_test_prog_fpga_cw310.elf | |
| 17.40% 2288 bin/sw/device/tests/csrng_smoketest_prog_sim_dv.elf | |
| 17.40% 2288 bin/sw/device/tests/csrng_smoketest_prog_sim_verilator.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_prog_sim_dv.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_prog_sim_verilator.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_signed_prog_sim_dv.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_signed_prog_sim_verilator.elf | |
| 17.41% 2000 bin/sw/device/tests/gpio_smoketest_prog_fpga_cw310.elf | |
| 17.41% 2104 bin/sw/device/tests/plic_sw_irq_test_prog_sim_dv.elf | |
| 17.43% 2644 bin/sw/device/tests/crypto/aes_gcm_timing_test_prog_sim_dv.elf | |
| 17.43% 2644 bin/sw/device/tests/crypto/aes_gcm_timing_test_prog_sim_verilator.elf | |
| 17.51% 2004 bin/sw/device/tests/gpio_smoketest_prog_sim_dv.elf | |
| 17.52% 2172 bin/sw/device/silicon_creator/lib/drivers/alert_functest_prog_fpga_cw310.elf | |
| 17.53% 1940 bin/sw/device/lib/crypto/drivers/kmac_test_prog_fpga_cw310.elf | |
| 17.54% 2080 bin/sw/device/tests/sim_dv/rom_ctrl_integrity_check_test_prog_sim_dv.elf | |
| 17.60% 1940 bin/sw/device/lib/crypto/drivers/kmac_test_prog_sim_dv.elf | |
| 17.60% 1940 bin/sw/device/lib/crypto/drivers/kmac_test_prog_sim_verilator.elf | |
| 17.61% 2768 bin/sw/device/tests/crypto/aes_gcm_functest_prog_fpga_cw310.elf | |
| 17.62% 2176 bin/sw/device/silicon_creator/lib/drivers/alert_functest_prog_sim_dv.elf | |
| 17.62% 2176 bin/sw/device/silicon_creator/lib/drivers/alert_functest_prog_sim_verilator.elf | |
| 17.63% 2000 bin/sw/device/tests/sram_ctrl_smoketest_prog_fpga_cw310.elf | |
| 17.66% 2768 bin/sw/device/tests/crypto/aes_gcm_functest_prog_sim_dv.elf | |
| 17.66% 2768 bin/sw/device/tests/crypto/aes_gcm_functest_prog_sim_verilator.elf | |
| 17.66% 2040 bin/sw/device/tests/example_concurrency_test_prog_fpga_cw310.elf | |
| 17.70% 2000 bin/sw/device/tests/sram_ctrl_smoketest_prog_sim_dv.elf | |
| 17.70% 2000 bin/sw/device/tests/sram_ctrl_smoketest_prog_sim_verilator.elf | |
| 17.70% 2060 bin/sw/device/lib/base/memory_perftest_prog_fpga_cw310.elf | |
| 17.71% 2000 bin/sw/device/silicon_creator/lib/drivers/retention_sram_functest_prog_fpga_cw310.elf | |
| 17.72% 2040 bin/sw/device/tests/example_concurrency_test_prog_sim_dv.elf | |
| 17.72% 2040 bin/sw/device/tests/example_concurrency_test_prog_sim_verilator.elf | |
| 17.77% 2000 bin/sw/device/silicon_creator/lib/drivers/retention_sram_functest_prog_sim_dv.elf | |
| 17.77% 2000 bin/sw/device/silicon_creator/lib/drivers/retention_sram_functest_prog_sim_verilator.elf | |
| 17.86% 1940 bin/sw/device/tests/sim_dv/exit_test_unlocked_bootstrap_prog_sim_dv.elf | |
| 17.92% 2232 bin/sw/device/tests/sim_dv/pwrmgr_main_power_glitch_test_prog_sim_dv.elf | |
| 17.97% 1944 bin/sw/device/tests/clkmgr_jitter_test_prog_fpga_cw310.elf | |
| 17.99% 2412 bin/sw/device/tests/otbn_mem_scramble_test_prog_fpga_cw310.elf | |
| 18.00% 1940 bin/sw/device/tests/clkmgr_jitter_test_prog_sim_dv.elf | |
| 18.00% 1940 bin/sw/device/tests/clkmgr_jitter_test_prog_sim_verilator.elf | |
| 18.11% 2420 bin/sw/device/tests/otbn_mem_scramble_test_prog_sim_dv.elf | |
| 18.11% 2420 bin/sw/device/tests/otbn_mem_scramble_test_prog_sim_verilator.elf | |
| 18.18% 3296 bin/sw/device/sca/sha3_serial_fpga_cw310.elf | |
| 18.18% 3296 bin/sw/device/sca/sha3_serial_fpga_nexysvideo.elf | |
| 18.18% 3292 bin/sw/device/sca/sha3_serial_sim_dv.elf | |
| 18.18% 3292 bin/sw/device/sca/sha3_serial_sim_verilator.elf | |
| 18.20% 2108 bin/sw/device/tests/pmp_smoketest_tor_prog_fpga_cw310.elf | |
| 18.27% 2108 bin/sw/device/tests/pmp_smoketest_napot_prog_fpga_cw310.elf | |
| 18.27% 2108 bin/sw/device/tests/pmp_smoketest_tor_prog_sim_dv.elf | |
| 18.27% 2108 bin/sw/device/tests/pmp_smoketest_tor_prog_sim_verilator.elf | |
| 18.34% 2108 bin/sw/device/tests/pmp_smoketest_napot_prog_sim_dv.elf | |
| 18.34% 2108 bin/sw/device/tests/pmp_smoketest_napot_prog_sim_verilator.elf | |
| 18.46% 2232 bin/sw/device/silicon_creator/lib/drivers/watchdog_functest_prog_fpga_cw310.elf | |
| 18.50% 2232 bin/sw/device/silicon_creator/lib/drivers/watchdog_functest_prog_sim_verilator.elf | |
| 18.50% 2232 bin/sw/device/silicon_creator/lib/drivers/watchdog_functest_prog_sim_dv.elf | |
| 18.54% 2000 bin/sw/device/silicon_creator/lib/drivers/hmac_functest_prog_fpga_cw310.elf | |
| 18.61% 2000 bin/sw/device/silicon_creator/lib/drivers/hmac_functest_prog_sim_dv.elf | |
| 18.61% 2000 bin/sw/device/silicon_creator/lib/drivers/hmac_functest_prog_sim_verilator.elf | |
| 19.16% 2576 bin/sw/device/tests/rstmgr_sw_rst_ctrl_test_prog_fpga_cw310.elf | |
| 19.20% 1888 bin/sw/device/lib/testing/test_rom/test_rom_test_prog_fpga_cw310.elf | |
| 19.20% 1888 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_fpga_cw310.elf | |
| 19.20% 1888 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_fpga_cw310.elf | |
| 19.20% 1888 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_fpga_nexysvideo.elf | |
| 19.20% 1888 bin/sw/device/tests/example_test_from_flash_prog_fpga_cw310.elf | |
| 19.24% 2116 bin/sw/device/tests/kmac_app_rom_test_prog_fpga_cw310.elf | |
| 19.24% 1884 bin/sw/device/lib/testing/test_rom/test_rom_test_prog_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/lib/testing/test_rom/test_rom_test_prog_sim_verilator.elf | |
| 19.24% 1884 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sim_verilator.elf | |
| 19.24% 1884 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_sim_verilator.elf | |
| 19.24% 1884 bin/sw/device/tests/example_test_from_flash_prog_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/tests/example_test_from_flash_prog_sim_verilator.elf | |
| 19.25% 2580 bin/sw/device/tests/rstmgr_sw_rst_ctrl_test_prog_sim_dv.elf | |
| 19.25% 2580 bin/sw/device/tests/rstmgr_sw_rst_ctrl_test_prog_sim_verilator.elf | |
| 19.31% 2116 bin/sw/device/tests/kmac_app_rom_test_prog_sim_dv.elf | |
| 19.31% 2116 bin/sw/device/tests/kmac_app_rom_test_prog_sim_verilator.elf | |
| 19.38% 2232 bin/sw/device/lib/crypto/drivers/entropy_test_prog_fpga_cw310.elf | |
| 19.44% 2060 bin/sw/device/silicon_creator/lib/irq_asm_functest_prog_fpga_cw310.elf | |
| 19.44% 2060 bin/sw/device/silicon_creator/lib/irq_asm_functest_prog_sim_dv.elf | |
| 19.44% 2060 bin/sw/device/silicon_creator/lib/irq_asm_functest_prog_sim_verilator.elf | |
| 19.44% 2232 bin/sw/device/lib/crypto/drivers/entropy_test_prog_sim_dv.elf | |
| 19.44% 2232 bin/sw/device/lib/crypto/drivers/entropy_test_prog_sim_verilator.elf | |
| 19.46% 2056 bin/sw/device/tests/rstmgr_sw_req_test_prog_fpga_cw310.elf | |
| 19.48% 2000 bin/sw/device/tests/rstmgr_smoketest_prog_fpga_cw310.elf | |
| 19.55% 2000 bin/sw/device/silicon_creator/lib/drivers/uart_functest_prog_fpga_cw310.elf | |
| 19.55% 2000 bin/sw/device/tests/rstmgr_smoketest_prog_sim_dv.elf | |
| 19.55% 2000 bin/sw/device/tests/rstmgr_smoketest_prog_sim_verilator.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sec_ver_0_fpga_cw310.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sec_ver_1_fpga_cw310.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_b_sec_ver_0_fpga_cw310.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_b_sec_ver_1_fpga_cw310.elf | |
| 19.56% 2060 bin/sw/device/silicon_creator/lib/drivers/rstmgr_functest_prog_fpga_cw310.elf | |
| 19.58% 2060 bin/sw/device/tests/rstmgr_sw_req_test_prog_sim_dv.elf | |
| 19.58% 2060 bin/sw/device/tests/rstmgr_sw_req_test_prog_sim_verilator.elf | |
| 19.60% 1944 bin/sw/device/tests/sim_dv/sleep_pin_retention_test_prog_sim_dv.elf | |
| 19.63% 2000 bin/sw/device/silicon_creator/lib/drivers/uart_functest_prog_sim_dv.elf | |
| 19.63% 2000 bin/sw/device/silicon_creator/lib/drivers/uart_functest_prog_sim_verilator.elf | |
| 19.63% 2060 bin/sw/device/silicon_creator/lib/drivers/rstmgr_functest_prog_sim_dv.elf | |
| 19.63% 2060 bin/sw/device/silicon_creator/lib/drivers/rstmgr_functest_prog_sim_verilator.elf | |
| 19.75% 2004 bin/sw/device/tests/coverage_test_prog_fpga_cw310.elf | |
| 19.75% 2116 bin/sw/device/silicon_creator/lib/drivers/rnd_functest_prog_fpga_cw310.elf | |
| 19.76% 2000 bin/sw/device/tests/coverage_test_prog_sim_verilator.elf | |
| 19.81% 2004 bin/sw/device/tests/coverage_test_prog_sim_dv.elf | |
| 19.87% 2120 bin/sw/device/silicon_creator/lib/drivers/rnd_functest_prog_sim_dv.elf | |
| 19.87% 2120 bin/sw/device/silicon_creator/lib/drivers/rnd_functest_prog_sim_verilator.elf | |
| 20.09% 2976 bin/sw/device/silicon_creator/rom/e2e/e2e_chip_specific_startup_prog_fpga_cw310.elf | |
| 20.12% 3620 bin/sw/device/sca/aes_serial_fpga_cw310.elf | |
| 20.12% 3620 bin/sw/device/sca/aes_serial_fpga_nexysvideo.elf | |
| 20.15% 3620 bin/sw/device/sca/aes_serial_sim_dv.elf | |
| 20.15% 3620 bin/sw/device/sca/aes_serial_sim_verilator.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_fpga_cw310.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_fpga_nexysvideo.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_sim_dv.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_sim_verilator.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_fpga_cw310.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_fpga_nexysvideo.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_sim_dv.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_sim_verilator.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_fpga_cw310.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_fpga_nexysvideo.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_sim_dv.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_sim_verilator.elf | |
| # Sorted by byte size increase | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_fpga_cw310.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_fpga_nexysvideo.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_sim_dv.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_a_sim_verilator.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_fpga_cw310.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_fpga_nexysvideo.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_sim_dv.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_b_sim_verilator.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_fpga_cw310.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_fpga_nexysvideo.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_sim_dv.elf | |
| 23.29% 68 bin/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_sim_verilator.elf | |
| 7.78% 594 bin/sw/device/tests/example_test_from_rom_rom_prog_sim_dv.elf | |
| 7.78% 594 bin/sw/device/tests/example_test_from_rom_rom_prog_sim_verilator.elf | |
| 6.30% 816 bin/sw/device/silicon_creator/rom/rom_epmp_test_rom_prog_sim_verilator.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_sim_dv.elf | |
| 7.36% 1268 bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.elf | |
| 15.10% 1276 bin/sw/device/tests/crt_test_prog_fpga_cw310.elf | |
| 15.16% 1276 bin/sw/device/tests/crt_test_prog_sim_dv.elf | |
| 15.16% 1276 bin/sw/device/tests/crt_test_prog_sim_verilator.elf | |
| 13.89% 1404 bin/sw/device/tests/sram_ctrl_execution_test_prog_fpga_cw310.elf | |
| 13.93% 1404 bin/sw/device/tests/sram_ctrl_execution_test_prog_sim_dv.elf | |
| 13.93% 1404 bin/sw/device/tests/sram_ctrl_execution_test_prog_sim_verilator.elf | |
| 12.12% 1516 bin/sw/device/tests/rv_core_ibex_address_translation_test_prog_fpga_cw310.elf | |
| 12.14% 1516 bin/sw/device/tests/rv_core_ibex_address_translation_test_prog_sim_dv.elf | |
| 12.14% 1516 bin/sw/device/tests/rv_core_ibex_address_translation_test_prog_sim_verilator.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_sim_verilator.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_sim_verilator.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_sim_verilator.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_sim_dv.elf | |
| 15.52% 1520 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_sim_verilator.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_bad_address_translation_fpga_nexysvideo.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_a_fpga_nexysvideo.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_b_fpga_nexysvideo.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_fpga_cw310.elf | |
| 15.55% 1524 bin/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_fpga_nexysvideo.elf | |
| 10.72% 1552 bin/sw/device/tests/sim_dv/sram_ctrl_execution_test_main_prog_sim_dv.elf | |
| 11.60% 1684 bin/sw/device/silicon_creator/rom/e2e/rom_e2e_static_critical_prog_fpga_cw310.elf | |
| 11.62% 1684 bin/sw/device/silicon_creator/rom/e2e/rom_e2e_static_critical_prog_sim_dv.elf | |
| 11.62% 1684 bin/sw/device/silicon_creator/rom/e2e/rom_e2e_static_critical_prog_sim_verilator.elf | |
| 9.25% 1742 bin/sw/device/tests/sim_dv/flash_rma_unlocked_test_rom_prog_sim_dv.elf | |
| 12.12% 1808 bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf | |
| 12.14% 1812 bin/sw/device/examples/hello_world/hello_world_fpga_cw310.elf | |
| 12.14% 1812 bin/sw/device/examples/hello_world/hello_world_fpga_nexysvideo.elf | |
| 12.15% 1812 bin/sw/device/examples/hello_world/hello_world_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/lib/testing/test_rom/test_rom_test_prog_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/lib/testing/test_rom/test_rom_test_prog_sim_verilator.elf | |
| 19.24% 1884 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sim_verilator.elf | |
| 19.24% 1884 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_sim_verilator.elf | |
| 19.24% 1884 bin/sw/device/tests/example_test_from_flash_prog_sim_dv.elf | |
| 19.24% 1884 bin/sw/device/tests/example_test_from_flash_prog_sim_verilator.elf | |
| 19.20% 1888 bin/sw/device/lib/testing/test_rom/test_rom_test_prog_fpga_cw310.elf | |
| 19.20% 1888 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_fpga_cw310.elf | |
| 19.20% 1888 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_fpga_cw310.elf | |
| 19.20% 1888 bin/sw/device/silicon_owner/bare_metal/ottf_test_bl0_slot_virtual_fpga_nexysvideo.elf | |
| 19.20% 1888 bin/sw/device/tests/example_test_from_flash_prog_fpga_cw310.elf | |
| 13.46% 1936 bin/sw/device/tests/aes_smoketest_prog_sim_dv.elf | |
| 13.46% 1936 bin/sw/device/tests/aes_smoketest_prog_sim_verilator.elf | |
| 17.53% 1940 bin/sw/device/lib/crypto/drivers/kmac_test_prog_fpga_cw310.elf | |
| 17.60% 1940 bin/sw/device/lib/crypto/drivers/kmac_test_prog_sim_dv.elf | |
| 17.60% 1940 bin/sw/device/lib/crypto/drivers/kmac_test_prog_sim_verilator.elf | |
| 13.45% 1940 bin/sw/device/tests/aes_smoketest_prog_fpga_cw310.elf | |
| 18.00% 1940 bin/sw/device/tests/clkmgr_jitter_test_prog_sim_dv.elf | |
| 18.00% 1940 bin/sw/device/tests/clkmgr_jitter_test_prog_sim_verilator.elf | |
| 17.86% 1940 bin/sw/device/tests/sim_dv/exit_test_unlocked_bootstrap_prog_sim_dv.elf | |
| 17.33% 1940 bin/sw/device/tests/uart_smoketest_prog_fpga_cw310.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_prog_sim_dv.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_prog_sim_verilator.elf | |
| 17.33% 1940 bin/sw/device/tests/uart_smoketest_signed_prog_fpga_cw310.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_signed_prog_sim_dv.elf | |
| 17.40% 1940 bin/sw/device/tests/uart_smoketest_signed_prog_sim_verilator.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sec_ver_0_fpga_cw310.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_a_sec_ver_1_fpga_cw310.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_b_sec_ver_0_fpga_cw310.elf | |
| 19.56% 1944 bin/sw/device/silicon_creator/rom/e2e/empty_test_slot_b_sec_ver_1_fpga_cw310.elf | |
| 12.71% 1944 bin/sw/device/tests/aes_entropy_test_prog_sim_dv.elf | |
| 12.71% 1944 bin/sw/device/tests/aes_entropy_test_prog_sim_verilator.elf | |
| 12.07% 1944 bin/sw/device/tests/aes_idle_test_prog_fpga_cw310.elf | |
| 12.10% 1944 bin/sw/device/tests/aes_idle_test_prog_sim_dv.elf | |
| 12.10% 1944 bin/sw/device/tests/aes_idle_test_prog_sim_verilator.elf | |
| 17.97% 1944 bin/sw/device/tests/clkmgr_jitter_test_prog_fpga_cw310.elf | |
| 16.84% 1944 bin/sw/device/tests/entropy_src_ast_rng_req_test_prog_fpga_cw310.elf | |
| 16.90% 1944 bin/sw/device/tests/entropy_src_ast_rng_req_test_prog_sim_dv.elf | |
| 16.90% 1944 bin/sw/device/tests/entropy_src_ast_rng_req_test_prog_sim_verilator.elf | |
| 19.60% 1944 bin/sw/device/tests/sim_dv/sleep_pin_retention_test_prog_sim_dv.elf | |
| 16.83% 1944 bin/sw/device/tests/sim_dv/sysrst_ctrl_inputs_test_prog_sim_dv.elf | |
| 12.71% 1948 bin/sw/device/tests/aes_entropy_test_prog_fpga_cw310.elf | |
| 9.29% 1948 bin/sw/device/tests/sim_dv/flash_init_test_rom_prog_sim_dv.elf | |
| 10.72% 1972 bin/sw/device/tests/rstmgr_cpu_info_test_prog_fpga_cw310.elf | |
| 10.75% 1972 bin/sw/device/tests/rstmgr_cpu_info_test_prog_sim_dv.elf | |
| 10.75% 1972 bin/sw/device/tests/rstmgr_cpu_info_test_prog_sim_verilator.elf | |
| 16.82% 2000 bin/sw/device/lib/crypto/drivers/aes_test_prog_fpga_cw310.elf | |
| 16.88% 2000 bin/sw/device/lib/crypto/drivers/aes_test_prog_sim_dv.elf | |
| 16.88% 2000 bin/sw/device/lib/crypto/drivers/aes_test_prog_sim_verilator.elf | |
| 18.54% 2000 bin/sw/device/silicon_creator/lib/drivers/hmac_functest_prog_fpga_cw310.elf | |
| 18.61% 2000 bin/sw/device/silicon_creator/lib/drivers/hmac_functest_prog_sim_dv.elf | |
| 18.61% 2000 bin/sw/device/silicon_creator/lib/drivers/hmac_functest_prog_sim_verilator.elf | |
| 17.71% 2000 bin/sw/device/silicon_creator/lib/drivers/retention_sram_functest_prog_fpga_cw310.elf | |
| 17.77% 2000 bin/sw/device/silicon_creator/lib/drivers/retention_sram_functest_prog_sim_dv.elf | |
| 17.77% 2000 bin/sw/device/silicon_creator/lib/drivers/retention_sram_functest_prog_sim_verilator.elf | |
| 19.55% 2000 bin/sw/device/silicon_creator/lib/drivers/uart_functest_prog_fpga_cw310.elf | |
| 19.63% 2000 bin/sw/device/silicon_creator/lib/drivers/uart_functest_prog_sim_dv.elf | |
| 19.63% 2000 bin/sw/device/silicon_creator/lib/drivers/uart_functest_prog_sim_verilator.elf | |
| 16.57% 2000 bin/sw/device/tests/clkmgr_smoketest_prog_fpga_cw310.elf | |
| 16.62% 2000 bin/sw/device/tests/clkmgr_smoketest_prog_sim_dv.elf | |
| 16.62% 2000 bin/sw/device/tests/clkmgr_smoketest_prog_sim_verilator.elf | |
| 19.76% 2000 bin/sw/device/tests/coverage_test_prog_sim_verilator.elf | |
| 15.99% 2000 bin/sw/device/tests/entropy_src_smoketest_prog_fpga_cw310.elf | |
| 17.41% 2000 bin/sw/device/tests/gpio_smoketest_prog_fpga_cw310.elf | |
| 19.48% 2000 bin/sw/device/tests/rstmgr_smoketest_prog_fpga_cw310.elf | |
| 19.55% 2000 bin/sw/device/tests/rstmgr_smoketest_prog_sim_dv.elf | |
| 19.55% 2000 bin/sw/device/tests/rstmgr_smoketest_prog_sim_verilator.elf | |
| 14.74% 2000 bin/sw/device/tests/sim_dv/alert_handler_entropy_test_prog_sim_dv.elf | |
| 17.63% 2000 bin/sw/device/tests/sram_ctrl_smoketest_prog_fpga_cw310.elf | |
| 17.70% 2000 bin/sw/device/tests/sram_ctrl_smoketest_prog_sim_dv.elf | |
| 17.70% 2000 bin/sw/device/tests/sram_ctrl_smoketest_prog_sim_verilator.elf | |
| 19.75% 2004 bin/sw/device/tests/coverage_test_prog_fpga_cw310.elf | |
| 19.81% 2004 bin/sw/device/tests/coverage_test_prog_sim_dv.elf | |
| 16.08% 2004 bin/sw/device/tests/entropy_src_smoketest_prog_sim_dv.elf | |
| 16.08% 2004 bin/sw/device/tests/entropy_src_smoketest_prog_sim_verilator.elf | |
| 17.51% 2004 bin/sw/device/tests/gpio_smoketest_prog_sim_dv.elf | |
| 13.43% 2008 bin/sw/device/tests/rv_plic_smoketest_prog_fpga_cw310.elf | |
| 13.43% 2008 bin/sw/device/tests/rv_plic_smoketest_prog_sim_verilator.elf | |
| 13.46% 2012 bin/sw/device/tests/rv_plic_smoketest_prog_sim_dv.elf | |
| 17.01% 2020 bin/third_party/riscv-compliance/C-BNEZ_prog_fpga_cw310.elf | |
| 17.01% 2020 bin/third_party/riscv-compliance/C-BNEZ_prog_sim_dv.elf | |
| 17.01% 2020 bin/third_party/riscv-compliance/C-BNEZ_prog_sim_verilator.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JALR_prog_fpga_cw310.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JALR_prog_sim_dv.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JALR_prog_sim_verilator.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-JAL_prog_fpga_cw310.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-JAL_prog_sim_dv.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-JAL_prog_sim_verilator.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JR_prog_fpga_cw310.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JR_prog_sim_dv.elf | |
| 16.93% 2020 bin/third_party/riscv-compliance/C-JR_prog_sim_verilator.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-J_prog_fpga_cw310.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-J_prog_sim_dv.elf | |
| 16.99% 2020 bin/third_party/riscv-compliance/C-J_prog_sim_verilator.elf | |
| 16.97% 2020 bin/third_party/riscv-compliance/C-LWSP_prog_fpga_cw310.elf | |
| 16.97% 2020 bin/third_party/riscv-compliance/C-LWSP_prog_sim_dv.elf | |
| 16.97% 2020 bin/third_party/riscv-compliance/C-LWSP_prog_sim_verilator.elf | |
| 16.60% 2020 bin/third_party/riscv-compliance/C-SW_prog_fpga_cw310.elf | |
| 16.60% 2020 bin/third_party/riscv-compliance/C-SW_prog_sim_dv.elf | |
| 16.60% 2020 bin/third_party/riscv-compliance/C-SW_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIVU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIVU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIVU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIV_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIV_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/DIV_prog_sim_verilator.elf | |
| 16.06% 2020 bin/third_party/riscv-compliance/I-ADD-01_prog_fpga_cw310.elf | |
| 16.06% 2020 bin/third_party/riscv-compliance/I-ADD-01_prog_sim_dv.elf | |
| 16.06% 2020 bin/third_party/riscv-compliance/I-ADD-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-AND-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-AND-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-AND-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ANDI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ANDI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ANDI-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGE-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGE-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGE-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGEU-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGEU-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BGEU-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLT-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLT-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLT-01_prog_sim_verilator.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLTU-01_prog_fpga_cw310.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLTU-01_prog_sim_dv.elf | |
| 15.56% 2020 bin/third_party/riscv-compliance/I-BLTU-01_prog_sim_verilator.elf | |
| 16.64% 2020 bin/third_party/riscv-compliance/I-CSRRC-01_prog_fpga_cw310.elf | |
| 16.64% 2020 bin/third_party/riscv-compliance/I-CSRRC-01_prog_sim_dv.elf | |
| 16.64% 2020 bin/third_party/riscv-compliance/I-CSRRC-01_prog_sim_verilator.elf | |
| 16.87% 2020 bin/third_party/riscv-compliance/I-CSRRCI-01_prog_fpga_cw310.elf | |
| 16.87% 2020 bin/third_party/riscv-compliance/I-CSRRCI-01_prog_sim_dv.elf | |
| 16.87% 2020 bin/third_party/riscv-compliance/I-CSRRCI-01_prog_sim_verilator.elf | |
| 16.65% 2020 bin/third_party/riscv-compliance/I-CSRRS-01_prog_fpga_cw310.elf | |
| 16.65% 2020 bin/third_party/riscv-compliance/I-CSRRS-01_prog_sim_dv.elf | |
| 16.65% 2020 bin/third_party/riscv-compliance/I-CSRRS-01_prog_sim_verilator.elf | |
| 16.96% 2020 bin/third_party/riscv-compliance/I-ECALL-01_prog_fpga_cw310.elf | |
| 16.96% 2020 bin/third_party/riscv-compliance/I-ECALL-01_prog_sim_dv.elf | |
| 16.96% 2020 bin/third_party/riscv-compliance/I-ECALL-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-IO-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-IO-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-IO-01_prog_sim_verilator.elf | |
| 15.84% 2020 bin/third_party/riscv-compliance/I-JAL-01_prog_fpga_cw310.elf | |
| 15.84% 2020 bin/third_party/riscv-compliance/I-JAL-01_prog_sim_dv.elf | |
| 15.84% 2020 bin/third_party/riscv-compliance/I-JAL-01_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LB-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LB-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LB-01_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LBU-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LBU-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LBU-01_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LH-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LH-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LH-01_prog_sim_verilator.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LHU-01_prog_fpga_cw310.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LHU-01_prog_sim_dv.elf | |
| 16.03% 2020 bin/third_party/riscv-compliance/I-LHU-01_prog_sim_verilator.elf | |
| 16.39% 2020 bin/third_party/riscv-compliance/I-LUI-01_prog_fpga_cw310.elf | |
| 16.39% 2020 bin/third_party/riscv-compliance/I-LUI-01_prog_sim_dv.elf | |
| 16.39% 2020 bin/third_party/riscv-compliance/I-LUI-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-OR-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-OR-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-OR-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ORI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ORI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-ORI-01_prog_sim_verilator.elf | |
| 16.15% 2020 bin/third_party/riscv-compliance/I-RF_width-01_prog_fpga_cw310.elf | |
| 16.15% 2020 bin/third_party/riscv-compliance/I-RF_width-01_prog_sim_dv.elf | |
| 16.15% 2020 bin/third_party/riscv-compliance/I-RF_width-01_prog_sim_verilator.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SB-01_prog_fpga_cw310.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SB-01_prog_sim_dv.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SB-01_prog_sim_verilator.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SH-01_prog_fpga_cw310.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SH-01_prog_sim_dv.elf | |
| 16.10% 2020 bin/third_party/riscv-compliance/I-SH-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SLL-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SLL-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SLL-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLLI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLLI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLLI-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLT-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLT-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLT-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTI-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTIU-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTIU-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SLTIU-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLTU-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLTU-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SLTU-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRA-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRA-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRA-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRAI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRAI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRAI-01_prog_sim_verilator.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRL-01_prog_fpga_cw310.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRL-01_prog_sim_dv.elf | |
| 16.12% 2020 bin/third_party/riscv-compliance/I-SRL-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRLI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRLI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-SRLI-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SUB-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SUB-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-SUB-01_prog_sim_verilator.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-XOR-01_prog_fpga_cw310.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-XOR-01_prog_sim_dv.elf | |
| 16.05% 2020 bin/third_party/riscv-compliance/I-XOR-01_prog_sim_verilator.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-XORI-01_prog_fpga_cw310.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-XORI-01_prog_sim_dv.elf | |
| 16.21% 2020 bin/third_party/riscv-compliance/I-XORI-01_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHSU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHSU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHSU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULHU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULH_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULH_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MULH_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MUL_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MUL_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/MUL_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REMU_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REMU_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REMU_prog_sim_verilator.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REM_prog_fpga_cw310.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REM_prog_sim_dv.elf | |
| 16.30% 2020 bin/third_party/riscv-compliance/REM_prog_sim_verilator.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI16SP_prog_fpga_cw310.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI16SP_prog_sim_dv.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI16SP_prog_sim_verilator.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI4SPN_prog_fpga_cw310.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI4SPN_prog_sim_dv.elf | |
| 17.07% 2024 bin/third_party/riscv-compliance/C-ADDI4SPN_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ADDI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ADDI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ADDI_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-ADD_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-ADD_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-ADD_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ANDI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ANDI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-ANDI_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-AND_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-AND_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-AND_prog_sim_verilator.elf | |
| 17.01% 2024 bin/third_party/riscv-compliance/C-BEQZ_prog_fpga_cw310.elf | |
| 17.01% 2024 bin/third_party/riscv-compliance/C-BEQZ_prog_sim_dv.elf | |
| 17.01% 2024 bin/third_party/riscv-compliance/C-BEQZ_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LUI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LUI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-LUI_prog_sim_verilator.elf | |
| 17.03% 2024 bin/third_party/riscv-compliance/C-LW_prog_fpga_cw310.elf | |
| 17.03% 2024 bin/third_party/riscv-compliance/C-LW_prog_sim_dv.elf | |
| 17.03% 2024 bin/third_party/riscv-compliance/C-LW_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-MV_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-MV_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-MV_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-OR_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-OR_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SLLI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SLLI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SLLI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRAI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRAI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRAI_prog_sim_verilator.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRLI_prog_fpga_cw310.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRLI_prog_sim_dv.elf | |
| 16.86% 2024 bin/third_party/riscv-compliance/C-SRLI_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-SUB_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-SUB_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-SUB_prog_sim_verilator.elf | |
| 16.62% 2024 bin/third_party/riscv-compliance/C-SWSP_prog_fpga_cw310.elf | |
| 16.62% 2024 bin/third_party/riscv-compliance/C-SWSP_prog_sim_dv.elf | |
| 16.62% 2024 bin/third_party/riscv-compliance/C-SWSP_prog_sim_verilator.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-XOR_prog_fpga_cw310.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-XOR_prog_sim_dv.elf | |
| 16.80% 2024 bin/third_party/riscv-compliance/C-XOR_prog_sim_verilator.elf | |
| 16.25% 2024 bin/third_party/riscv-compliance/I-ADDI-01_prog_fpga_cw310.elf | |
| 16.25% 2024 bin/third_party/riscv-compliance/I-ADDI-01_prog_sim_dv.elf | |
| 16.25% 2024 bin/third_party/riscv-compliance/I-ADDI-01_prog_sim_verilator.elf | |
| 15.92% 2024 bin/third_party/riscv-compliance/I-AUIPC-01_prog_fpga_cw310.elf | |
| 15.92% 2024 bin/third_party/riscv-compliance/I-AUIPC-01_prog_sim_dv.elf | |
| 15.92% 2024 bin/third_party/riscv-compliance/I-AUIPC-01_prog_sim_verilator.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BEQ-01_prog_fpga_cw310.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BEQ-01_prog_sim_dv.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BEQ-01_prog_sim_verilator.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BNE-01_prog_fpga_cw310.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BNE-01_prog_sim_dv.elf | |
| 15.59% 2024 bin/third_party/riscv-compliance/I-BNE-01_prog_sim_verilator.elf | |
| 16.91% 2024 bin/third_party/riscv-compliance/I-CSRRSI-01_prog_fpga_cw310.elf | |
| 16.91% 2024 bin/third_party/riscv-compliance/I-CSRRSI-01_prog_sim_dv.elf | |
| 16.91% 2024 bin/third_party/riscv-compliance/I-CSRRSI-01_prog_sim_verilator.elf | |
| 16.81% 2024 bin/third_party/riscv-compliance/I-CSRRW-01_prog_fpga_cw310.elf | |
| 16.81% 2024 bin/third_party/riscv-compliance/I-CSRRW-01_prog_sim_dv.elf | |
| 16.81% 2024 bin/third_party/riscv-compliance/I-CSRRW-01_prog_sim_verilator.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-CSRRWI-01_prog_fpga_cw310.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-CSRRWI-01_prog_sim_dv.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-CSRRWI-01_prog_sim_verilator.elf | |
| 16.83% 2024 bin/third_party/riscv-compliance/I-DELAY_SLOTS-01_prog_fpga_cw310.elf | |
| 16.83% 2024 bin/third_party/riscv-compliance/I-DELAY_SLOTS-01_prog_sim_dv.elf | |
| 16.83% 2024 bin/third_party/riscv-compliance/I-DELAY_SLOTS-01_prog_sim_verilator.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-ENDIANESS-01_prog_fpga_cw310.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-ENDIANESS-01_prog_sim_dv.elf | |
| 17.05% 2024 bin/third_party/riscv-compliance/I-ENDIANESS-01_prog_sim_verilator.elf | |
| 15.55% 2024 bin/third_party/riscv-compliance/I-JALR-01_prog_fpga_cw310.elf | |
| 15.55% 2024 bin/third_party/riscv-compliance/I-JALR-01_prog_sim_dv.elf | |
| 15.55% 2024 bin/third_party/riscv-compliance/I-JALR-01_prog_sim_verilator.elf | |
| 16.07% 2024 bin/third_party/riscv-compliance/I-LW-01_prog_fpga_cw310.elf | |
| 16.07% 2024 bin/third_party/riscv-compliance/I-LW-01_prog_sim_dv.elf | |
| 16.07% 2024 bin/third_party/riscv-compliance/I-LW-01_prog_sim_verilator.elf | |
| 16.23% 2024 bin/third_party/riscv-compliance/I-RF_size-01_prog_fpga_cw310.elf | |
| 16.23% 2024 bin/third_party/riscv-compliance/I-RF_size-01_prog_sim_dv.elf | |
| 16.23% 2024 bin/third_party/riscv-compliance/I-RF_size-01_prog_sim_verilator.elf | |
| 15.83% 2024 bin/third_party/riscv-compliance/I-SW-01_prog_fpga_cw310.elf | |
| 15.83% 2024 bin/third_party/riscv-compliance/I-SW-01_prog_sim_dv.elf | |
| 15.83% 2024 bin/third_party/riscv-compliance/I-SW-01_prog_sim_verilator.elf | |
| 16.84% 2032 bin/sw/device/tests/rv_core_ibex_rnd_test_prog_fpga_cw310.elf | |
| 15.37% 2032 bin/sw/device/tests/rv_timer_smoketest_prog_sim_dv.elf | |
| 15.37% 2032 bin/sw/device/tests/rv_timer_smoketest_prog_sim_verilator.elf | |
| 16.93% 2036 bin/sw/device/tests/rv_core_ibex_rnd_test_prog_sim_dv.elf | |
| 16.93% 2036 bin/sw/device/tests/rv_core_ibex_rnd_test_prog_sim_verilator.elf | |
| 15.36% 2036 bin/sw/device/tests/rv_timer_smoketest_prog_fpga_cw310.elf | |
| 17.66% 2040 bin/sw/device/tests/example_concurrency_test_prog_fpga_cw310.elf | |
| 17.72% 2040 bin/sw/device/tests/example_concurrency_test_prog_sim_dv.elf | |
| 17.72% 2040 bin/sw/device/tests/example_concurrency_test_prog_sim_verilator.elf | |
| 12.77% 2048 bin/sw/device/tests/kmac_mode_kmac_test_prog_fpga_cw310.elf | |
| 12.83% 2052 bin/sw/device/tests/kmac_mode_kmac_test_prog_sim_dv.elf | |
| 12.83% 2052 bin/sw/device/tests/kmac_mode_kmac_test_prog_sim_verilator.elf | |
| 19.46% 2056 bin/sw/device/tests/rstmgr_sw_req_test_prog_fpga_cw310.elf | |
| 16.16% 2056 bin/sw/device/tests/sim_dv/pwrmgr_usbdev_smoketest_prog_sim_dv.elf | |
| 17.70% 2060 bin/sw/device/lib/base/memory_perftest_prog_fpga_cw310.elf | |
| 19.56% 2060 bin/sw/device/silicon_creator/lib/drivers/rstmgr_functest_prog_fpga_cw310.elf | |
| 19.63% 2060 bin/sw/device/silicon_creator/lib/drivers/rstmgr_functest_prog_sim_dv.elf | |
| 19.63% 2060 bin/sw/device/silicon_creator/lib/drivers/rstmgr_functest_prog_sim_verilator.elf | |
| 19.44% 2060 bin/sw/device/silicon_creator/lib/irq_asm_functest_prog_fpga_cw310.elf | |
| 19.44% 2060 bin/sw/device/silicon_creator/lib/irq_asm_functest_prog_sim_dv.elf | |
| 19.44% 2060 bin/sw/device/silicon_creator/lib/irq_asm_functest_prog_sim_verilator.elf | |
| 14.74% 2060 bin/sw/device/tests/kmac_idle_test_prog_fpga_cw310.elf | |
| 19.58% 2060 bin/sw/device/tests/rstmgr_sw_req_test_prog_sim_dv.elf | |
| 19.58% 2060 bin/sw/device/tests/rstmgr_sw_req_test_prog_sim_verilator.elf | |
| 16.39% 2060 bin/sw/device/tests/sim_dv/clkmgr_external_clk_src_for_lc_test_prog_sim_dv.elf | |
| 16.55% 2060 bin/sw/device/tests/sim_dv/lc_ctrl_kmac_reset_test_prog_sim_dv.elf | |
| 16.41% 2060 bin/sw/device/tests/sim_dv/lc_ctrl_transition_test_prog_sim_dv.elf | |
| 17.31% 2060 bin/sw/device/tests/sim_dv/rv_dm_ndm_reset_req_prog_sim_dv.elf | |
| 14.81% 2064 bin/sw/device/tests/kmac_idle_test_prog_sim_dv.elf | |
| 14.81% 2064 bin/sw/device/tests/kmac_idle_test_prog_sim_verilator.elf | |
| 15.24% 2076 bin/sw/device/tests/sim_dv/sram_ctrl_ret_scrambled_access_test_prog_sim_dv.elf | |
| 17.54% 2080 bin/sw/device/tests/sim_dv/rom_ctrl_integrity_check_test_prog_sim_dv.elf | |
| 5.20% 2084 bin/sw/device/tests/autogen/alert_test_prog_fpga_cw310.elf | |
| 5.20% 2084 bin/sw/device/tests/autogen/alert_test_prog_sim_dv.elf | |
| 5.20% 2084 bin/sw/device/tests/autogen/alert_test_prog_sim_verilator.elf | |
| 17.34% 2100 bin/sw/device/tests/plic_sw_irq_test_prog_fpga_cw310.elf | |
| 17.37% 2100 bin/sw/device/tests/plic_sw_irq_test_prog_sim_verilator.elf | |
| 12.39% 2104 bin/sw/device/tests/kmac_smoketest_prog_fpga_cw310.elf | |
| 12.42% 2104 bin/sw/device/tests/kmac_smoketest_prog_sim_dv.elf | |
| 12.42% 2104 bin/sw/device/tests/kmac_smoketest_prog_sim_verilator.elf | |
| 17.41% 2104 bin/sw/device/tests/plic_sw_irq_test_prog_sim_dv.elf | |
| 18.27% 2108 bin/sw/device/tests/pmp_smoketest_napot_prog_fpga_cw310.elf | |
| 18.34% 2108 bin/sw/device/tests/pmp_smoketest_napot_prog_sim_dv.elf | |
| 18.34% 2108 bin/sw/device/tests/pmp_smoketest_napot_prog_sim_verilator.elf | |
| 18.20% 2108 bin/sw/device/tests/pmp_smoketest_tor_prog_fpga_cw310.elf | |
| 18.27% 2108 bin/sw/device/tests/pmp_smoketest_tor_prog_sim_dv.elf | |
| 18.27% 2108 bin/sw/device/tests/pmp_smoketest_tor_prog_sim_verilator.elf | |
| 13.07% 2112 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_hardcoded_prog_sim_dv.elf | |
| 13.07% 2112 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_hardcoded_prog_sim_verilator.elf | |
| 0.68% 2112 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_wycheproof_prog_fpga_cw310.elf | |
| 16.00% 2112 bin/sw/device/tests/entropy_src_fw_ovr_test_prog_sim_dv.elf | |
| 16.00% 2112 bin/sw/device/tests/entropy_src_fw_ovr_test_prog_sim_verilator.elf | |
| 16.86% 2112 bin/sw/device/tests/lc_ctrl_otp_hw_cfg_test_prog_sim_dv.elf | |
| 16.86% 2112 bin/sw/device/tests/lc_ctrl_otp_hw_cfg_test_prog_sim_verilator.elf | |
| 16.83% 2112 bin/sw/device/tests/otp_ctrl_smoketest_prog_fpga_cw310.elf | |
| 11.13% 2112 bin/sw/device/tests/sim_dv/lc_walkthrough_test_prog_sim_dv.elf | |
| 17.38% 2112 bin/sw/device/tests/spi_host_smoketest_prog_fpga_cw310.elf | |
| 19.75% 2116 bin/sw/device/silicon_creator/lib/drivers/rnd_functest_prog_fpga_cw310.elf | |
| 13.06% 2116 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_hardcoded_prog_fpga_cw310.elf | |
| 15.99% 2116 bin/sw/device/tests/entropy_src_fw_ovr_test_prog_fpga_cw310.elf | |
| 19.24% 2116 bin/sw/device/tests/kmac_app_rom_test_prog_fpga_cw310.elf | |
| 19.31% 2116 bin/sw/device/tests/kmac_app_rom_test_prog_sim_dv.elf | |
| 19.31% 2116 bin/sw/device/tests/kmac_app_rom_test_prog_sim_verilator.elf | |
| 16.84% 2116 bin/sw/device/tests/lc_ctrl_otp_hw_cfg_test_prog_fpga_cw310.elf | |
| 16.92% 2116 bin/sw/device/tests/otp_ctrl_smoketest_prog_sim_dv.elf | |
| 16.92% 2116 bin/sw/device/tests/otp_ctrl_smoketest_prog_sim_verilator.elf | |
| 16.62% 2116 bin/sw/device/tests/sim_dv/lc_ctrl_program_error_prog_sim_dv.elf | |
| 19.87% 2120 bin/sw/device/silicon_creator/lib/drivers/rnd_functest_prog_sim_dv.elf | |
| 19.87% 2120 bin/sw/device/silicon_creator/lib/drivers/rnd_functest_prog_sim_verilator.elf | |
| 12.98% 2120 bin/sw/device/tests/sim_dv/lc_walkthrough_testunlocks_test_prog_sim_dv.elf | |
| 16.00% 2160 bin/sw/device/tests/kmac_mode_cshake_test_prog_fpga_cw310.elf | |
| 16.09% 2164 bin/sw/device/tests/kmac_mode_cshake_test_prog_sim_dv.elf | |
| 16.09% 2164 bin/sw/device/tests/kmac_mode_cshake_test_prog_sim_verilator.elf | |
| 10.78% 2164 bin/sw/device/tests/sim_dv/gpio_test_prog_sim_dv.elf | |
| 17.52% 2172 bin/sw/device/silicon_creator/lib/drivers/alert_functest_prog_fpga_cw310.elf | |
| 14.78% 2172 bin/sw/device/tests/aon_timer_smoketest_prog_fpga_cw310.elf | |
| 14.81% 2172 bin/sw/device/tests/aon_timer_smoketest_prog_sim_dv.elf | |
| 15.63% 2172 bin/sw/device/tests/entropy_src_kat_test_prog_fpga_cw310.elf | |
| 16.93% 2172 bin/sw/device/tests/sim_dv/sram_ctrl_main_scrambled_access_test_prog_sim_dv.elf | |
| 17.62% 2176 bin/sw/device/silicon_creator/lib/drivers/alert_functest_prog_sim_dv.elf | |
| 17.62% 2176 bin/sw/device/silicon_creator/lib/drivers/alert_functest_prog_sim_verilator.elf | |
| 14.84% 2176 bin/sw/device/tests/aon_timer_smoketest_prog_sim_verilator.elf | |
| 15.71% 2176 bin/sw/device/tests/entropy_src_kat_test_prog_sim_dv.elf | |
| 15.71% 2176 bin/sw/device/tests/entropy_src_kat_test_prog_sim_verilator.elf | |
| 11.47% 2176 bin/sw/device/tests/sim_dv/sysrst_ctrl_reset_test_prog_sim_dv.elf | |
| 14.96% 2180 bin/sw/device/tests/sim_dv/ast_usb_clk_calib_prog_sim_dv.elf | |
| 11.97% 2220 bin/sw/device/tests/pwrmgr_sleep_disabled_test_prog_sim_dv.elf | |
| 11.97% 2220 bin/sw/device/tests/pwrmgr_sleep_disabled_test_prog_sim_verilator.elf | |
| 11.97% 2224 bin/sw/device/tests/pwrmgr_sleep_disabled_test_prog_fpga_cw310.elf | |
| 16.58% 2224 bin/sw/device/tests/sim_dv/sysrst_ctrl_outputs_test_prog_sim_dv.elf | |
| 19.38% 2232 bin/sw/device/lib/crypto/drivers/entropy_test_prog_fpga_cw310.elf | |
| 19.44% 2232 bin/sw/device/lib/crypto/drivers/entropy_test_prog_sim_dv.elf | |
| 19.44% 2232 bin/sw/device/lib/crypto/drivers/entropy_test_prog_sim_verilator.elf | |
| 18.46% 2232 bin/sw/device/silicon_creator/lib/drivers/watchdog_functest_prog_fpga_cw310.elf | |
| 18.50% 2232 bin/sw/device/silicon_creator/lib/drivers/watchdog_functest_prog_sim_dv.elf | |
| 18.50% 2232 bin/sw/device/silicon_creator/lib/drivers/watchdog_functest_prog_sim_verilator.elf | |
| 17.92% 2232 bin/sw/device/tests/sim_dv/pwrmgr_main_power_glitch_test_prog_sim_dv.elf | |
| 12.91% 2236 bin/sw/device/tests/sim_dv/adc_ctrl_sleep_debug_cable_wakeup_test_prog_sim_dv.elf | |
| 9.75% 2252 bin/sw/device/tests/sim_dv/spi_tx_rx_test_prog_sim_dv.elf | |
| 12.74% 2284 bin/sw/device/tests/hmac_enc_idle_test_prog_sim_dv.elf | |
| 12.74% 2284 bin/sw/device/tests/hmac_enc_idle_test_prog_sim_verilator.elf | |
| 17.40% 2288 bin/sw/device/tests/csrng_smoketest_prog_sim_dv.elf | |
| 17.40% 2288 bin/sw/device/tests/csrng_smoketest_prog_sim_verilator.elf | |
| 12.74% 2288 bin/sw/device/tests/hmac_enc_idle_test_prog_fpga_cw310.elf | |
| 17.37% 2292 bin/sw/device/tests/csrng_smoketest_prog_fpga_cw310.elf | |
| 16.49% 2292 bin/sw/device/tests/hmac_smoketest_prog_fpga_cw310.elf | |
| 15.31% 2292 bin/sw/device/tests/pwrmgr_wdog_reset_reqs_test_prog_fpga_cw310.elf | |
| 15.35% 2292 bin/sw/device/tests/pwrmgr_wdog_reset_reqs_test_prog_sim_dv.elf | |
| 15.34% 2292 bin/sw/device/tests/pwrmgr_wdog_reset_reqs_test_prog_sim_verilator.elf | |
| 13.38% 2292 bin/sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test_prog_sim_dv.elf | |
| 16.57% 2296 bin/sw/device/tests/hmac_smoketest_prog_sim_dv.elf | |
| 16.57% 2296 bin/sw/device/tests/hmac_smoketest_prog_sim_verilator.elf | |
| 11.19% 2328 bin/sw/device/tests/sim_dv/sensor_ctrl_status_test_prog_sim_dv.elf | |
| 16.29% 2332 bin/sw/device/tests/sim_dv/spi_host_tx_rx_test_prog_sim_dv.elf | |
| 14.31% 2352 bin/sw/device/tests/sim_dv/alert_handler_escalation_test_prog_sim_dv.elf | |
| 15.23% 2352 bin/sw/device/tests/sim_dv/entropy_src_fuse_en_fw_read_test_prog_sim_dv.elf | |
| 16.63% 2356 bin/sw/device/tests/sim_dv/pwrmgr_deep_sleep_power_glitch_test_prog_sim_dv.elf | |
| 16.55% 2356 bin/sw/device/tests/sim_dv/pwrmgr_sleep_power_glitch_test_prog_sim_dv.elf | |
| 10.20% 2360 bin/sw/device/tests/sensor_ctrl_wakeup_test_prog_fpga_cw310.elf | |
| 9.89% 2368 bin/sw/device/tests/alert_handler_ping_timeout_test_prog_fpga_cw310.elf | |
| 10.28% 2376 bin/sw/device/tests/sensor_ctrl_wakeup_test_prog_sim_dv.elf | |
| 10.28% 2376 bin/sw/device/tests/sensor_ctrl_wakeup_test_prog_sim_verilator.elf | |
| 9.98% 2384 bin/sw/device/tests/alert_handler_ping_timeout_test_prog_sim_dv.elf | |
| 9.98% 2384 bin/sw/device/tests/alert_handler_ping_timeout_test_prog_sim_verilator.elf | |
| 14.45% 2404 bin/sw/device/tests/aon_timer_sleep_wdog_sleep_pause_test_prog_fpga_cw310.elf | |
| 14.48% 2404 bin/sw/device/tests/aon_timer_sleep_wdog_sleep_pause_test_prog_sim_verilator.elf | |
| 15.03% 2404 bin/sw/device/tests/aon_timer_wdog_bite_reset_test_prog_sim_verilator.elf | |
| 14.51% 2408 bin/sw/device/tests/aon_timer_sleep_wdog_sleep_pause_test_prog_sim_dv.elf | |
| 15.03% 2408 bin/sw/device/tests/aon_timer_wdog_bite_reset_test_prog_fpga_cw310.elf | |
| 15.06% 2408 bin/sw/device/tests/aon_timer_wdog_bite_reset_test_prog_sim_dv.elf | |
| 13.73% 2408 bin/sw/device/tests/sram_ctrl_sleep_sram_ret_contents_test_prog_fpga_cw310.elf | |
| 13.76% 2408 bin/sw/device/tests/sram_ctrl_sleep_sram_ret_contents_test_prog_sim_dv.elf | |
| 13.76% 2408 bin/sw/device/tests/sram_ctrl_sleep_sram_ret_contents_test_prog_sim_verilator.elf | |
| 17.99% 2412 bin/sw/device/tests/otbn_mem_scramble_test_prog_fpga_cw310.elf | |
| 18.11% 2420 bin/sw/device/tests/otbn_mem_scramble_test_prog_sim_dv.elf | |
| 18.11% 2420 bin/sw/device/tests/otbn_mem_scramble_test_prog_sim_verilator.elf | |
| 10.60% 2436 bin/sw/device/tests/sim_dv/sleep_pin_wake_test_prog_sim_dv.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_aes_trans_test_prog_fpga_cw310.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_aes_trans_test_prog_sim_dv.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_aes_trans_test_prog_sim_verilator.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_hmac_trans_test_prog_fpga_cw310.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_hmac_trans_test_prog_sim_dv.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_hmac_trans_test_prog_sim_verilator.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_kmac_trans_test_prog_fpga_cw310.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_kmac_trans_test_prog_sim_dv.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_kmac_trans_test_prog_sim_verilator.elf | |
| 13.48% 2460 bin/sw/device/tests/clkmgr_off_otbn_trans_test_prog_fpga_cw310.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_otbn_trans_test_prog_sim_dv.elf | |
| 13.50% 2460 bin/sw/device/tests/clkmgr_off_otbn_trans_test_prog_sim_verilator.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_fast_test_prog_sim_dv.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_fast_test_prog_sim_verilator.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_slow_test_prog_sim_dv.elf | |
| 14.88% 2464 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_slow_test_prog_sim_verilator.elf | |
| 14.89% 2468 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_fast_test_prog_fpga_cw310.elf | |
| 14.89% 2468 bin/sw/device/tests/clkmgr_external_clk_src_for_sw_slow_test_prog_fpga_cw310.elf | |
| 16.99% 2480 bin/sw/device/tests/csrng_kat_test_prog_fpga_cw310.elf | |
| 17.03% 2480 bin/sw/device/tests/csrng_kat_test_prog_sim_dv.elf | |
| 17.03% 2480 bin/sw/device/tests/csrng_kat_test_prog_sim_verilator.elf | |
| 9.42% 2504 bin/sw/device/tests/sim_dv/uart_tx_rx_test_prog_sim_dv.elf | |
| 11.10% 2508 bin/sw/device/tests/rv_core_ibex_nmi_irq_test_prog_fpga_cw310.elf | |
| 14.76% 2512 bin/sw/device/tests/otbn_irq_test_prog_fpga_cw310.elf | |
| 14.78% 2512 bin/sw/device/tests/otbn_irq_test_prog_sim_dv.elf | |
| 14.78% 2512 bin/sw/device/tests/otbn_irq_test_prog_sim_verilator.elf | |
| 11.15% 2516 bin/sw/device/tests/rv_core_ibex_nmi_irq_test_prog_sim_dv.elf | |
| 11.15% 2516 bin/sw/device/tests/rv_core_ibex_nmi_irq_test_prog_sim_verilator.elf | |
| 10.18% 2516 bin/sw/device/tests/sim_dv/i2c_host_tx_rx_test_prog_sim_dv.elf | |
| 14.44% 2524 bin/sw/device/tests/pwrmgr_smoketest_prog_sim_dv.elf | |
| 14.44% 2524 bin/sw/device/tests/pwrmgr_smoketest_prog_sim_verilator.elf | |
| 14.48% 2528 bin/sw/device/tests/clkmgr_reset_frequency_test_prog_fpga_cw310.elf | |
| 14.51% 2528 bin/sw/device/tests/clkmgr_reset_frequency_test_prog_sim_dv.elf | |
| 14.51% 2528 bin/sw/device/tests/clkmgr_reset_frequency_test_prog_sim_verilator.elf | |
| 14.43% 2528 bin/sw/device/tests/pwrmgr_smoketest_prog_fpga_cw310.elf | |
| 9.05% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_fpga_cw310.elf | |
| 9.05% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_fpga_nexysvideo.elf | |
| 9.06% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_sim_dv.elf | |
| 9.06% 2536 bin/sw/device/examples/hello_usbdev/hello_usbdev_sim_verilator.elf | |
| 16.25% 2560 bin/sw/device/tests/crypto/ecdsa_p256_verify_functest_hardcoded_prog_sim_dv.elf | |
| 16.25% 2560 bin/sw/device/tests/crypto/ecdsa_p256_verify_functest_hardcoded_prog_sim_verilator.elf | |
| 10.70% 2576 bin/sw/device/tests/hmac_enc_test_prog_fpga_cw310.elf | |
| 19.16% 2576 bin/sw/device/tests/rstmgr_sw_rst_ctrl_test_prog_fpga_cw310.elf | |
| 19.25% 2580 bin/sw/device/tests/rstmgr_sw_rst_ctrl_test_prog_sim_dv.elf | |
| 19.25% 2580 bin/sw/device/tests/rstmgr_sw_rst_ctrl_test_prog_sim_verilator.elf | |
| 14.88% 2588 bin/sw/device/tests/sim_dv/csrng_fuse_en_sw_app_read_prog_sim_dv.elf | |
| 10.78% 2592 bin/sw/device/tests/hmac_enc_test_prog_sim_dv.elf | |
| 10.78% 2592 bin/sw/device/tests/hmac_enc_test_prog_sim_verilator.elf | |
| 1.20% 2612 bin/sw/device/tests/crypto/rsa_3072_verify_functest_wycheproof_prog_fpga_cw310.elf | |
| 15.43% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_hardcoded_prog_sim_dv.elf | |
| 15.43% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_hardcoded_prog_sim_verilator.elf | |
| 1.20% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_wycheproof_prog_sim_dv.elf | |
| 1.20% 2616 bin/sw/device/tests/crypto/rsa_3072_verify_functest_wycheproof_prog_sim_verilator.elf | |
| 12.92% 2636 bin/sw/device/tests/sleep_pwm_pulses_test_prog_fpga_cw310.elf | |
| 12.94% 2636 bin/sw/device/tests/sleep_pwm_pulses_test_prog_sim_dv.elf | |
| 12.94% 2636 bin/sw/device/tests/sleep_pwm_pulses_test_prog_sim_verilator.elf | |
| 13.02% 2644 bin/sw/device/tests/aon_timer_irq_test_prog_fpga_cw310.elf | |
| 17.38% 2644 bin/sw/device/tests/crypto/aes_gcm_timing_test_prog_fpga_cw310.elf | |
| 17.43% 2644 bin/sw/device/tests/crypto/aes_gcm_timing_test_prog_sim_dv.elf | |
| 17.43% 2644 bin/sw/device/tests/crypto/aes_gcm_timing_test_prog_sim_verilator.elf | |
| 11.40% 2656 bin/sw/device/tests/sim_dv/sleep_pin_mio_dio_val_test_prog_sim_dv.elf | |
| 13.12% 2660 bin/sw/device/tests/aon_timer_irq_test_prog_sim_dv.elf | |
| 13.12% 2660 bin/sw/device/tests/aon_timer_irq_test_prog_sim_verilator.elf | |
| 13.02% 2660 bin/sw/device/tests/sensor_ctrl_alert_test_prog_fpga_cw310.elf | |
| 13.14% 2680 bin/sw/device/tests/sensor_ctrl_alert_test_prog_sim_dv.elf | |
| 13.14% 2680 bin/sw/device/tests/sensor_ctrl_alert_test_prog_sim_verilator.elf | |
| 14.74% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_hardcoded_prog_fpga_cw310.elf | |
| 14.77% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_hardcoded_prog_sim_dv.elf | |
| 14.77% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_hardcoded_prog_sim_verilator.elf | |
| 0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_fpga_cw310.elf | |
| 0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_sim_dv.elf | |
| 0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_sim_verilator.elf | |
| 11.58% 2708 bin/sw/device/tests/aon_timer_wdog_lc_escalate_test_prog_fpga_cw310.elf | |
| 11.43% 2728 bin/sw/device/tests/sim_dv/clkmgr_escalation_reset_test_prog_sim_dv.elf | |
| 11.69% 2732 bin/sw/device/tests/aon_timer_wdog_lc_escalate_test_prog_sim_dv.elf | |
| 11.69% 2732 bin/sw/device/tests/aon_timer_wdog_lc_escalate_test_prog_sim_verilator.elf | |
| 12.61% 2748 bin/sw/device/tests/ast_clk_outs_test_prog_sim_verilator.elf | |
| 12.61% 2752 bin/sw/device/tests/ast_clk_outs_test_prog_fpga_cw310.elf | |
| 12.63% 2752 bin/sw/device/tests/ast_clk_outs_test_prog_sim_dv.elf | |
| 12.71% 2756 bin/sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test_prog_sim_dv.elf | |
| 4.02% 2760 bin/sw/device/tests/autogen/plic_all_irqs_test_prog_fpga_cw310.elf | |
| 15.08% 2760 bin/sw/device/tests/otbn_smoketest_prog_sim_dv.elf | |
| 15.08% 2760 bin/sw/device/tests/otbn_smoketest_prog_sim_verilator.elf | |
| 15.07% 2764 bin/sw/device/tests/otbn_smoketest_prog_fpga_cw310.elf | |
| 10.76% 2764 bin/sw/device/tests/usbdev_test_prog_sim_verilator.elf | |
| 17.61% 2768 bin/sw/device/tests/crypto/aes_gcm_functest_prog_fpga_cw310.elf | |
| 17.66% 2768 bin/sw/device/tests/crypto/aes_gcm_functest_prog_sim_dv.elf | |
| 17.66% 2768 bin/sw/device/tests/crypto/aes_gcm_functest_prog_sim_verilator.elf | |
| 4.05% 2776 bin/sw/device/tests/autogen/plic_all_irqs_test_prog_sim_dv.elf | |
| 4.05% 2776 bin/sw/device/tests/autogen/plic_all_irqs_test_prog_sim_verilator.elf | |
| 15.77% 2796 bin/sw/device/tests/crypto/ecdsa_p256_functest_prog_fpga_cw310.elf | |
| 15.81% 2796 bin/sw/device/tests/crypto/ecdsa_p256_functest_prog_sim_dv.elf | |
| 15.81% 2796 bin/sw/device/tests/crypto/ecdsa_p256_functest_prog_sim_verilator.elf | |
| 14.00% 2804 bin/sw/device/tests/otbn_randomness_test_prog_sim_dv.elf | |
| 14.00% 2804 bin/sw/device/tests/otbn_randomness_test_prog_sim_verilator.elf | |
| 14.01% 2808 bin/sw/device/tests/otbn_randomness_test_prog_fpga_cw310.elf | |
| 12.54% 2812 bin/sw/device/tests/sim_dv/pwrmgr_b2b_sleep_reset_test_prog_sim_dv.elf | |
| 13.64% 2852 bin/sw/device/tests/sim_dv/inject_scramble_seed_prog_sim_dv.elf | |
| 12.42% 2856 bin/sw/device/tests/flash_ctrl_test_prog_fpga_cw310.elf | |
| 12.44% 2856 bin/sw/device/tests/flash_ctrl_test_prog_sim_dv.elf | |
| 14.34% 2860 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_hardcoded_prog_fpga_cw310.elf | |
| 0.91% 2860 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_wycheproof_prog_fpga_cw310.elf | |
| 12.46% 2860 bin/sw/device/tests/flash_ctrl_test_prog_sim_verilator.elf | |
| 14.39% 2864 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_hardcoded_prog_sim_dv.elf | |
| 14.39% 2864 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_hardcoded_prog_sim_verilator.elf | |
| 10.74% 2872 bin/sw/device/tests/entropy_src_csrng_test_prog_fpga_cw310.elf | |
| 10.75% 2872 bin/sw/device/tests/entropy_src_csrng_test_prog_sim_dv.elf | |
| 10.75% 2872 bin/sw/device/tests/entropy_src_csrng_test_prog_sim_verilator.elf | |
| 14.26% 2924 bin/sw/device/tests/otbn_rsa_test_prog_fpga_cw310.elf | |
| 14.28% 2924 bin/sw/device/tests/otbn_rsa_test_prog_sim_dv.elf | |
| 14.28% 2924 bin/sw/device/tests/otbn_rsa_test_prog_sim_verilator.elf | |
| 14.48% 2936 bin/sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test_prog_sim_dv.elf | |
| 12.09% 2944 bin/sw/device/tests/alert_handler_reverse_ping_in_deep_sleep_test_prog_fpga_cw310.elf | |
| 12.19% 2964 bin/sw/device/tests/alert_handler_reverse_ping_in_deep_sleep_test_prog_sim_dv.elf | |
| 12.52% 2964 bin/sw/device/tests/otbn_ecdsa_op_irq_test_prog_fpga_cw310.elf | |
| 12.57% 2968 bin/sw/device/tests/otbn_ecdsa_op_irq_test_prog_sim_dv.elf | |
| 12.57% 2968 bin/sw/device/tests/otbn_ecdsa_op_irq_test_prog_sim_verilator.elf | |
| 20.09% 2976 bin/sw/device/silicon_creator/rom/e2e/e2e_chip_specific_startup_prog_fpga_cw310.elf | |
| 11.07% 2980 bin/sw/device/tests/entropy_src_edn_reqs_test_prog_fpga_cw310.elf | |
| 11.08% 2980 bin/sw/device/tests/entropy_src_edn_reqs_test_prog_sim_dv.elf | |
| 11.08% 2980 bin/sw/device/tests/entropy_src_edn_reqs_test_prog_sim_verilator.elf | |
| 16.90% 3040 bin/sw/device/silicon_creator/lib/sigverify/sigverify_functest_prog_fpga_cw310.elf | |
| 16.93% 3040 bin/sw/device/silicon_creator/lib/sigverify/sigverify_functest_prog_sim_dv.elf | |
| 16.93% 3040 bin/sw/device/silicon_creator/lib/sigverify/sigverify_functest_prog_sim_verilator.elf | |
| 10.01% 3064 bin/sw/device/tests/flash_ctrl_idle_low_power_test_prog_fpga_cw310.elf | |
| 15.06% 3080 bin/sw/device/silicon_creator/rom/rom_sim_dv.elf | |
| 15.06% 3080 bin/sw/device/silicon_creator/rom/rom_sim_verilator.elf | |
| 10.07% 3080 bin/sw/device/tests/flash_ctrl_idle_low_power_test_prog_sim_dv.elf | |
| 10.07% 3080 bin/sw/device/tests/flash_ctrl_idle_low_power_test_prog_sim_verilator.elf | |
| 15.72% 3084 bin/sw/device/tests/flash_ctrl_clock_freqs_test_prog_fpga_cw310.elf | |
| 15.80% 3096 bin/sw/device/tests/flash_ctrl_clock_freqs_test_prog_sim_verilator.elf | |
| 15.83% 3100 bin/sw/device/tests/flash_ctrl_clock_freqs_test_prog_sim_dv.elf | |
| 10.30% 3116 bin/sw/device/tests/clkmgr_sleep_frequency_test_prog_fpga_cw310.elf | |
| 8.45% 3116 bin/sw/device/tests/rstmgr_alert_info_test_prog_fpga_cw310.elf | |
| 10.38% 3136 bin/sw/device/tests/clkmgr_sleep_frequency_test_prog_sim_dv.elf | |
| 10.38% 3136 bin/sw/device/tests/clkmgr_sleep_frequency_test_prog_sim_verilator.elf | |
| 8.52% 3140 bin/sw/device/tests/rstmgr_alert_info_test_prog_sim_dv.elf | |
| 8.52% 3140 bin/sw/device/tests/rstmgr_alert_info_test_prog_sim_verilator.elf | |
| 15.44% 3196 bin/sw/device/silicon_creator/rom/rom_fpga_cw310.elf | |
| 15.44% 3196 bin/sw/device/silicon_creator/rom/rom_fpga_nexysvideo.elf | |
| 9.85% 3204 bin/sw/device/tests/sim_dv/pwrmgr_normal_sleep_all_wake_ups_prog_sim_dv.elf | |
| 12.21% 3220 bin/sw/device/tests/clkmgr_off_peri_test_prog_sim_dv.elf | |
| 12.21% 3220 bin/sw/device/tests/clkmgr_off_peri_test_prog_sim_verilator.elf | |
| 12.21% 3224 bin/sw/device/tests/clkmgr_off_peri_test_prog_fpga_cw310.elf | |
| 10.98% 3248 bin/sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test_prog_sim_dv.elf | |
| 10.68% 3288 bin/sw/device/tests/flash_ctrl_ops_test_prog_fpga_cw310.elf | |
| 18.18% 3292 bin/sw/device/sca/sha3_serial_sim_dv.elf | |
| 18.18% 3292 bin/sw/device/sca/sha3_serial_sim_verilator.elf | |
| 18.18% 3296 bin/sw/device/sca/sha3_serial_fpga_cw310.elf | |
| 18.18% 3296 bin/sw/device/sca/sha3_serial_fpga_nexysvideo.elf | |
| 10.76% 3308 bin/sw/device/tests/flash_ctrl_ops_test_prog_sim_verilator.elf | |
| 10.77% 3312 bin/sw/device/tests/flash_ctrl_ops_test_prog_sim_dv.elf | |
| 9.93% 3428 bin/sw/device/tests/sim_dv/pwrmgr_deep_sleep_all_reset_reqs_test_prog_sim_dv.elf | |
| 10.12% 3484 bin/sw/device/tests/sim_dv/pwrmgr_normal_sleep_all_reset_reqs_test_prog_sim_dv.elf | |
| 16.70% 3532 bin/sw/device/silicon_creator/lib/boot_data_functest_prog_fpga_cw310.elf | |
| 16.73% 3532 bin/sw/device/silicon_creator/lib/boot_data_functest_prog_sim_dv.elf | |
| 16.73% 3532 bin/sw/device/silicon_creator/lib/boot_data_functest_prog_sim_verilator.elf | |
| 12.27% 3576 bin/sw/device/tests/aes_sideload_test_prog_fpga_cw310.elf | |
| 12.29% 3576 bin/sw/device/tests/aes_sideload_test_prog_sim_dv.elf | |
| 12.28% 3576 bin/sw/device/tests/aes_sideload_test_prog_sim_verilator.elf | |
| 9.83% 3600 bin/sw/device/tests/sim_dv/pwrmgr_deep_sleep_all_wake_ups_prog_sim_dv.elf | |
| 10.12% 3608 bin/sw/device/tests/sim_dv/pwrmgr_random_sleep_all_reset_reqs_test_prog_sim_dv.elf | |
| 20.12% 3620 bin/sw/device/sca/aes_serial_fpga_cw310.elf | |
| 20.12% 3620 bin/sw/device/sca/aes_serial_fpga_nexysvideo.elf | |
| 20.15% 3620 bin/sw/device/sca/aes_serial_sim_dv.elf | |
| 20.15% 3620 bin/sw/device/sca/aes_serial_sim_verilator.elf | |
| 15.40% 3624 bin/sw/device/tests/sim_dv/keymgr_key_derivation_test_prog_sim_dv.elf | |
| 9.72% 3656 bin/sw/device/tests/sim_dv/all_escalation_resets_test_prog_sim_dv.elf | |
| 16.28% 3664 bin/sw/device/silicon_creator/lib/drivers/keymgr_functest_prog_fpga_cw310.elf | |
| 16.32% 3668 bin/sw/device/silicon_creator/lib/drivers/keymgr_functest_prog_sim_dv.elf | |
| 16.31% 3668 bin/sw/device/silicon_creator/lib/drivers/keymgr_functest_prog_sim_verilator.elf | |
| 15.64% 3672 bin/sw/device/sca/ecc_serial_fpga_cw310.elf | |
| 15.64% 3672 bin/sw/device/sca/ecc_serial_fpga_nexysvideo.elf | |
| 15.66% 3672 bin/sw/device/sca/ecc_serial_sim_dv.elf | |
| 15.66% 3672 bin/sw/device/sca/ecc_serial_sim_verilator.elf | |
| 14.24% 3736 bin/sw/device/sca/ecc384_serial_fpga_cw310.elf | |
| 14.24% 3736 bin/sw/device/sca/ecc384_serial_fpga_nexysvideo.elf | |
| 14.25% 3736 bin/sw/device/sca/ecc384_serial_sim_dv.elf | |
| 14.25% 3736 bin/sw/device/sca/ecc384_serial_sim_verilator.elf | |
| 14.62% 3744 bin/sw/device/tests/sim_dv/keymgr_sideload_kmac_test_prog_sim_dv.elf | |
| 15.27% 4092 bin/sw/device/tests/sim_dv/keymgr_sideload_otbn_test_prog_sim_dv.elf |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment