vector-table.c

vector_table_t vector_table = {
  .initial_sp_value = &_stack,              //  Stack starts here and grows downwards.
  .reset            = reset_handler,        //  Entry point for the user program.
  .nmi              = nmi_handler,          //  Default: null_handler
  .hard_fault       = hard_fault_handler,   //  Default: blocking_handler

  .memory_manage_fault = mem_manage_handler,     //  Default: blocking_handler
  .bus_fault           = bus_fault_handler,      //  Default: blocking_handler
  .usage_fault         = usage_fault_handler,    //  Default: blocking_handler
  .debug_monitor       = debug_monitor_handler,  //  Default: null_handler

  .sv_call = sv_call_handler,   //  Default: null_handler
  .pend_sv = pend_sv_handler,   //  Default: null_handler
  .systick = sys_tick_handler,  //  Default: null_handler
  .irq = {
    //  IRQ_HANDLERS from ~/.platformio/packages/framework-libopencm3/lib/stm32/f1/vector_nvic.c
    //  The "*_isr" Interrupt Service Routines below default to blocking_handler() unless overridden in the user program.
    [NVIC_WWDG_IRQ]           = wwdg_isr, 
    [NVIC_PVD_IRQ]            = pvd_isr, 
    [NVIC_TAMPER_IRQ]         = tamper_isr, 
    [NVIC_RTC_IRQ]            = rtc_isr, 
    [NVIC_FLASH_IRQ]          = flash_isr, 
    [NVIC_RCC_IRQ]            = rcc_isr, 
    [NVIC_EXTI0_IRQ]          = exti0_isr, 
    [NVIC_EXTI1_IRQ]          = exti1_isr, 
    [NVIC_EXTI2_IRQ]          = exti2_isr, 
    [NVIC_EXTI3_IRQ]          = exti3_isr, 
    [NVIC_EXTI4_IRQ]          = exti4_isr, 
    [NVIC_DMA1_CHANNEL1_IRQ]  = dma1_channel1_isr, 
    [NVIC_DMA1_CHANNEL2_IRQ]  = dma1_channel2_isr, 
    [NVIC_DMA1_CHANNEL3_IRQ]  = dma1_channel3_isr, 
    [NVIC_DMA1_CHANNEL4_IRQ]  = dma1_channel4_isr, 
    [NVIC_DMA1_CHANNEL5_IRQ]  = dma1_channel5_isr, 
    [NVIC_DMA1_CHANNEL6_IRQ]  = dma1_channel6_isr, 
    [NVIC_DMA1_CHANNEL7_IRQ]  = dma1_channel7_isr, 
    [NVIC_ADC1_2_IRQ]         = adc1_2_isr, 
    [NVIC_USB_HP_CAN_TX_IRQ]  = usb_hp_can_tx_isr, 
    [NVIC_USB_LP_CAN_RX0_IRQ] = usb_lp_can_rx0_isr, 
    [NVIC_CAN_RX1_IRQ]        = can_rx1_isr, 
    [NVIC_CAN_SCE_IRQ]        = can_sce_isr, 
    [NVIC_EXTI9_5_IRQ]        = exti9_5_isr, 
    [NVIC_TIM1_BRK_IRQ]       = tim1_brk_isr, 
    [NVIC_TIM1_UP_IRQ]        = tim1_up_isr, 
    [NVIC_TIM1_TRG_COM_IRQ]   = tim1_trg_com_isr, 
    [NVIC_TIM1_CC_IRQ]        = tim1_cc_isr, 
    [NVIC_TIM2_IRQ]           = tim2_isr, 
    [NVIC_TIM3_IRQ]           = tim3_isr, 
    [NVIC_TIM4_IRQ]           = tim4_isr, 
    [NVIC_I2C1_EV_IRQ]        = i2c1_ev_isr, 
    [NVIC_I2C1_ER_IRQ]        = i2c1_er_isr, 
    [NVIC_I2C2_EV_IRQ]        = i2c2_ev_isr, 
    [NVIC_I2C2_ER_IRQ]        = i2c2_er_isr, 
    [NVIC_SPI1_IRQ]           = spi1_isr, 
    [NVIC_SPI2_IRQ]           = spi2_isr, 
    [NVIC_USART1_IRQ]         = usart1_isr, 
    [NVIC_USART2_IRQ]         = usart2_isr, 
    [NVIC_USART3_IRQ]         = usart3_isr, 
    [NVIC_EXTI15_10_IRQ]      = exti15_10_isr, 
    [NVIC_RTC_ALARM_IRQ]      = rtc_alarm_isr, 
    [NVIC_USB_WAKEUP_IRQ]     = usb_wakeup_isr, 
    [NVIC_TIM8_BRK_IRQ]       = tim8_brk_isr, 
    [NVIC_TIM8_UP_IRQ]        = tim8_up_isr, 
    [NVIC_TIM8_TRG_COM_IRQ]   = tim8_trg_com_isr, 
    [NVIC_TIM8_CC_IRQ]        = tim8_cc_isr, 
    [NVIC_ADC3_IRQ]           = adc3_isr, 
    [NVIC_FSMC_IRQ]           = fsmc_isr, 
    [NVIC_SDIO_IRQ]           = sdio_isr, 
    [NVIC_TIM5_IRQ]           = tim5_isr, 
    [NVIC_SPI3_IRQ]           = spi3_isr, 
    [NVIC_UART4_IRQ]          = uart4_isr, 
    [NVIC_UART5_IRQ]          = uart5_isr, 
    [NVIC_TIM6_IRQ]           = tim6_isr, 
    [NVIC_TIM7_IRQ]           = tim7_isr, 
    [NVIC_DMA2_CHANNEL1_IRQ]  = dma2_channel1_isr, 
    [NVIC_DMA2_CHANNEL2_IRQ]  = dma2_channel2_isr, 
    [NVIC_DMA2_CHANNEL3_IRQ]  = dma2_channel3_isr, 
    [NVIC_DMA2_CHANNEL4_5_IRQ]= dma2_channel4_5_isr, 
    [NVIC_DMA2_CHANNEL5_IRQ]  = dma2_channel5_isr, 
    [NVIC_ETH_IRQ]            = eth_isr, 
    [NVIC_ETH_WKUP_IRQ]       = eth_wkup_isr, 
    [NVIC_CAN2_TX_IRQ]        = can2_tx_isr, 
    [NVIC_CAN2_RX0_IRQ]       = can2_rx0_isr, 
    [NVIC_CAN2_RX1_IRQ]       = can2_rx1_isr, 
    [NVIC_CAN2_SCE_IRQ]       = can2_sce_isr, 
    [NVIC_OTG_FS_IRQ]         = otg_fs_isr
  }
};