arch/arm64: Add support for Generic Interrupt Controller Version 2

sample-nuttx-pull-request.md

Summary

Currently NuttX on Arm64 supports Generic Interrupt Controller (GIC) Versions 3 and 4: arm64_gicv3.c, arm64_gic.h. This PR adds support for GIC Version 2, which is needed by Pine64 PinePhone based on Allwinner A64 SoC.

This 64-bit implementation of GIC v2 is mostly identical to the existing GIC v2 for 32-bit Armv7-A (armv7-a/arm_gicv2.c, armv7-a/gic.h), with minor modifications to support 64-bit Registers (Interrupt Context).

• arch/arm64/Kconfig: Under "ARM64 Options", we added an integer option ARM_GIC_VERSION ("GIC version") that selects the GIC Version. Valid values are 2, 3 and 4, default is 3.

• arch/arm64/src/common/arm64_gicv2.c: Implements 64-bit GIC v2 based on 32-bit armv7-a/arm_gicv2.c and armv7-a/gic.h, modified to support 64-bit Registers (Interrupt Context).

  Function and Macro Names have not been changed, for easier cross-referencing between the 32-bit and 64-bit implementations of GIC v2.

• arch/arm64/src/common/arm64_gicv3.c: Added Conditional Compilation for GIC v3. This file will not be compiled if ARM_GIC_VERSION is 2.

• arch/arm64/src/common/arm64_gic.h: Added the Version Identifier for GIC v2. At startup we read the GIC Version from hardware and verify that it matches ARM_GIC_VERSION.

• arch/arm64/include/qemu/chip.h: Added the QEMU Base Addresses for GIC v2.

• arch/arm64/src/common/Make.defs: Added the source file that implements GIC v2.

• boards/arm64/qemu/qemu-armv8a/README.txt: Added the documentation for testing GIC v2 with QEMU.

• boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig: Added the Board Configuration qemu-armv8a:nsh_gicv2 for testing GIC v2 with QEMU. Identical to qemu-armv8a:nsh, except that ARM_GIC_VERSION is 2.

Impact

With this PR, NuttX now supports GIC v2 on Arm64. We select GIC v2 through the new Board Configuration qemu-armv8a:nsh_gicv2 (that sets ARM_GIC_VERSION to 2):

./tools/configure.sh -l qemu-armv8a:nsh_gicv2

GIC v2 on Arm64 is needed for the upcoming port of NuttX to Pine64 PinePhone based on Allwinner A64 SoC.

There is no impact on the existing implementation of GIC v3, as tested below.

Testing

We tested with QEMU our implementation of GIC v2:

./tools/configure.sh -l qemu-armv8a:nsh_gicv2
make
qemu-system-aarch64 \
  -cpu cortex-a53 \
  -nographic \
  -machine virt,virtualization=on,gic-version=2 \
  -net none \
  -chardev stdio,id=con,mux=on \
  -serial chardev:con \
  -mon chardev=con,mode=readline \
  -kernel ./nuttx

(See the NuttX QEMU Log)

The NuttX QEMU Log shows that NuttX responds correctly to UART Input (in NSH). This means that GIC v2 has correctly handled UART Input Interrupts.

For Regression Testing: We tested the existing implementation of GIC v3 for Single Core:

./tools/configure.sh -l qemu-armv8a:nsh
make
qemu-system-aarch64 \
  -cpu cortex-a53 \
  -nographic \
  -machine virt,virtualization=on,gic-version=3 \
  -net none \
  -chardev stdio,id=con,mux=on \
  -serial chardev:con \
  -mon chardev=con,mode=readline \
  -kernel ./nuttx

(See the NuttX QEMU Log)

And we tested GIC v3 for Multiple Cores (SMP):

./tools/configure.sh -l qemu-armv8a:nsh_smp
make
qemu-system-aarch64 \
  -smp 4 \
  -cpu cortex-a53 \
  -nographic \
  -machine virt,virtualization=on,gic-version=3 \
  -net none \
  -chardev stdio,id=con,mux=on \
  -serial chardev:con \
  -mon chardev=con,mode=readline \
  -kernel ./nuttx

(See the NuttX QEMU Log)

For Single and Multiple Cores, GIC v3 responds correctly to UART Input (in NSH). This means that GIC v3 has correctly handled UART Input Interrupts.