Created
January 20, 2024 09:39
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Emulate Ox64 BL808 SBC with TinyEMU RISC-V Emulator. See https://github.com/lupyuen/nuttx-tinyemu
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| * Executing task: cd nuttx && ../run.sh | |
| + cd /Users/Luppy/riscv/ox64-tinyemu | |
| + sleep 20 | |
| ++ brew --prefix | |
| ++ brew --prefix | |
| + make CFLAGS=-I/usr/local/opt/openssl/include LDFLAGS=-L/usr/local/opt/openssl/lib CONFIG_MACOS=y | |
| make: Nothing to be done for 'all'. | |
| + cd /Users/Luppy/riscv/nuttx-tinyemu/docs/smode | |
| + /Users/Luppy/riscv/ox64-tinyemu/temu root-riscv64.cfg | |
| TinyEMU Emulator for Ox64 BL808 RISC-V SBC | |
| virtio_console_init | |
| Patched RDTTIME (Read System Timer) at 0x5020bad6 | |
| virtio_console_resize_event | |
| ABCplic_write: offset=0x2080, val=0x0 | |
| plic_write: offset=0x2084, val=0x0 | |
| plic_read: offset=0x201004 | |
| plic_write: offset=0x201004, val=0x0 | |
| plic_write: offset=0x4, val=0x1 | |
| plic_write: offset=0x8, val=0x1 | |
| plic_write: offset=0xc, val=0x1 | |
| plic_write: offset=0x10, val=0x1 | |
| plic_write: offset=0x14, val=0x1 | |
| plic_write: offset=0x18, val=0x1 | |
| plic_write: offset=0x1c, val=0x1 | |
| plic_write: offset=0x20, val=0x1 | |
| plic_write: offset=0x24, val=0x1 | |
| plic_write: offset=0x28, val=0x1 | |
| plic_write: offset=0x2c, val=0x1 | |
| plic_write: offset=0x30, val=0x1 | |
| plic_write: offset=0x34, val=0x1 | |
| plic_write: offset=0x38, val=0x1 | |
| plic_write: offset=0x3c, val=0x1 | |
| plic_write: offset=0x40, val=0x1 | |
| plic_write: offset=0x44, val=0x1 | |
| plic_write: offset=0x48, val=0x1 | |
| plic_write: offset=0x4c, val=0x1 | |
| plic_write: offset=0x50, val=0x1 | |
| plic_write: offset=0x54, val=0x1 | |
| plic_write: offset=0x58, val=0x1 | |
| plic_write: offset=0x5c, val=0x1 | |
| plic_write: offset=0x60, val=0x1 | |
| plic_write: offset=0x64, val=0x1 | |
| plic_write: offset=0x68, val=0x1 | |
| plic_write: offset=0x6c, val=0x1 | |
| plic_write: offset=0x70, val=0x1 | |
| plic_write: offset=0x74, val=0x1 | |
| plic_write: offset=0x78, val=0x1 | |
| plic_write: offset=0x7c, val=0x1 | |
| plic_write: offset=0x80, val=0x1 | |
| plic_write: offset=0x84, val=0x1 | |
| plic_write: offset=0x88, val=0x1 | |
| plic_write: offset=0x8c, val=0x1 | |
| plic_write: offset=0x90, val=0x1 | |
| plic_write: offset=0x94, val=0x1 | |
| plic_write: offset=0x98, val=0x1 | |
| plic_write: offset=0x9c, val=0x1 | |
| plicplic_write: offset=0xe8, val=0x1 | |
| plic_write: offset=0xec, val=0x1 | |
| plic_write: offset=0xf0, val=0x1 | |
| plic_write: offset=0xf4, val=0x1 | |
| plic_write: offset=0xf8, val=0x1 | |
| plic_write: offset=0xfc, val=0x1 | |
| plic_write: offset=0x100, val=0x1 | |
| plic_write: offset=0x104, val=0x1 | |
| plic_write: offset=0x108, val=0x1 | |
| plic_write: offset=0x10c, val=0x1 | |
| plic_write: offset=0x110, val=0x1 | |
| plic_write: offset=0x114, val=0x1 | |
| plic_write: offset=0x118, val=0x1 | |
| plic_write: offset=0x11c, val=0x1 | |
| plic_write: offset=0x120, val=0x1 | |
| plic_write: offset=0x124, val=0x1 | |
| plic_write: offset=0x128, val=0x1 | |
| plic_write: offset=0x12c, val=0x1 | |
| plic_write: offset=0x130, val=0x1 | |
| plic_write: offset=0x134, val=0x1 | |
| plic_write: offset=0x138, val=0x1 | |
| plic_write: offset=0x13c, val=0x1 | |
| plic_write: offset=0x140, val=0x1 | |
| plic_write: offset=0x144, val=0x1 | |
| plic_write: offset=0x148, val=0x1 | |
| plic_write: offset=0x201000, val=0x0 | |
| raise_exception2: cause=9, tval=0x0 | |
| TODO: Emulate OpenSBI for System Timer | |
| raise_exception2: cause=9, tval=0x0 | |
| TODO: Emulate OpenSBI for System Timer | |
| plic_read: offset=0x2080 | |
| plic_write: offset=0x2080, val=0x100000 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| NuttShell (NSH) NuttX-12.4.0-RC0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| nsh> read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| ] | |
| plic_set_irq: irq_num=20, state=1 | |
| plic_update_mip: set_mip, pending=0x80000, served=0x0 | |
| raise_exception: cause=-2147483639 | |
| raise_exception2: cause=-2147483639, tval=0x0 | |
| plic_read: offset=0x201004 | |
| plic_update_mip: reset_mip, pending=0x80000, served=0x80000 | |
| read BL808_UART_INT_STS | |
| read BL808_UART_INT_MASK | |
| write BL808_UART_INT_CLEAR: 0x2 | |
| virtio_ack_irq | |
| plic_set_irq: irq_num=20, state=0 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x80000 | |
| plic_write: offset=0x201004, val=0x14 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| nsh> read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| [l] | |
| plic_set_irq: irq_num=20, state=1 | |
| plic_update_mip: set_mip, pending=0x80000, served=0x0 | |
| raise_exception: cause=-2147483639 | |
| raise_exception2: cause=-2147483639, tval=0x0 | |
| plic_read: offset=0x201004 | |
| plic_update_mip: reset_mip, pending=0x80000, served=0x80000 | |
| read BL808_UART_INT_STS | |
| read BL808_UART_INT_MASK | |
| write BL808_UART_INT_CLEAR: 0x2 | |
| virtio_ack_irq | |
| plic_set_irq: irq_num=20, state=0 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x80000 | |
| plic_write: offset=0x201004, val=0x14 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| lread BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x000[s] | |
| plic_set_irq: irq_num=20, state=1 | |
| plic_update_mip: set_mip, pending=0x80000, served=0x0 | |
| raise_exception: cause=-2147483639 | |
| raise_exception2: cause=-2147483639, tval=0x0 | |
| plic_read: offset=0x201004 | |
| plic_update_mip: reset_mip, pending=0x80000, served=0x80000 | |
| read BL808_UART_INT_STS | |
| read BL808_UART_INT_MASK | |
| write BL808_UART_INT_CLEAR: 0x2 | |
| virtio_ack_irq | |
| plic_set_irq: irq_num=20, state=0 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x80000 | |
| plic_write: offset=0x201004, val=0x14 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| sread BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| ]arget_write_slow: invalid physical address 0x000[ | |
| plic_set_irq: irq_num=20, state=1 | |
| plic_update_mip: set_mip, pending=0x80000, served=0x0 | |
| raise_exception: cause=-2147483639 | |
| raise_exception2: cause=-2147483639, tval=0x0 | |
| plic_read: offset=0x201004 | |
| plic_update_mip: reset_mip, pending=0x80000, served=0x80000 | |
| read BL808_UART_INT_STS | |
| read BL808_UART_INT_MASK | |
| write BL808_UART_INT_CLEAR: 0x2 | |
| virtio_ack_irq | |
| plic_set_irq: irq_num=20, state=0 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x80000 | |
| plic_write: offset=0x201004, val=0x14 | |
| plic_update_mip: reset_mip, pending=0x0, served=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| /: | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| devread BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| / | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| procread BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| / | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| systemread BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| / | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| nsh> read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| raise_exception2: cause=8, tval=0x0 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| read BL808_UART_INT_MASK | |
| target_write_slow: invalid physical address 0x0000000030002024 |
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