Created
January 18, 2024 03:54
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Emulate Ox64 BL808 SBC with TinyEMU RISC-V Emulator. See https://github.com/lupyuen/nuttx-tinyemu
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| $ temu root-riscv64.cfg | |
| TinyEMU Emulator for Ox64 BL808 RISC-V SBC | |
| virtio_console_init | |
| ABCnx_start: Entry | |
| plic_write: offset=0x2080, val=0x0 | |
| plic_write: offset=0x2084, val=0x0 | |
| plic_read: offset=0x201004 | |
| plic_write: offset=0x201004, val=0x0 | |
| plic_write: offset=0x4, val=0x1 | |
| plic_write: offset=0x8, val=0x1 | |
| plic_write: offset=0xc, val=0x1 | |
| plic_write: offset=0x10, val=0x1 | |
| plic_write: offset=0x14, val=0x1 | |
| plic_write: offset=0x18, val=0x1 | |
| plic_write: offset=0x1c, val=0x1 | |
| plic_write: offset=0x20, val=0x1 | |
| plic_write: offset=0x24, val=0x1 | |
| plic_write: offset=0x28, val=0x1 | |
| plic_write: offset=0x2c, val=0x1 | |
| plic_write: offset=0x30, val=0x1 | |
| plic_write: offset=0x34, val=0x1 | |
| plic_write: offset=0x38, val=0x1 | |
| plic_write: offset=0x3c, val=0x1 | |
| plic_write: offset=0x40, val=0x1 | |
| plic_write: offset=0x44, val=0x1 | |
| plic_write: offset=0x48, val=0x1 | |
| plic_write: offset=0x4c, val=0x1 | |
| plic_write: offset=0x50, val=0x1 | |
| plic_write: offset=0x54, val=0x1 | |
| plic_write: offset=0x58, val=0x1 | |
| plic_write: offset=0x5c, val=0x1 | |
| plic_write: offset=0x60, val=0x1 | |
| plic_write: offset=0x64, val=0x1 | |
| plic_write: offset=0x68, val=0x1 | |
| plic_lic_write: offset=0x70, val=0x1 | |
| plic_write: offset=0x74, val=0x1 | |
| plic_write: offset=0x78, val=0x1 | |
| plic_write: offset=0x7c, val=0x1 | |
| plic_write: offset=0x80, val=0x1 | |
| plic_write: offset=0x84, val=0x1 | |
| plic_write: offset=0x88, val=0x1 | |
| plic_write: offset=0x8c, val=0x1 | |
| plic_write: offset=0x90, val=0x1 | |
| plic_write: offset=0x94, val=0x1 | |
| plic_write: offset=0x98, val=0x1 | |
| plic_write: offset=0x9c, val=0x1 | |
| plic_write: offset=0xa0, val=0x1 | |
| plic_write: offset=0xa4, val=0x1 | |
| plic_write: offset=0xa8, val=0x1 | |
| plic_write: offset=0xac, val=0x1 | |
| plic_write: offset=0xb0, val=0x1 | |
| plic_write: offset=0xb4, val=0x1 | |
| plic_write: offset=0xb8, val=0x1 | |
| plic_write: offset=0xbc, val=0x1 | |
| plic_write: offset=0xc0, val=0x1 | |
| plic_write: offset=0xc4, val=0x1 | |
| plic_write: offset=0xc8, val=0x1 | |
| plic_write: offset=0xcc, val=0x1 | |
| plic_write: offset=0xd0, val=0x1 | |
| plic_write: offset=0xd4, val=0x1 | |
| plic_write: offset=0xd8, val=0x1 | |
| plic_write: offset=0xdc, val=0x1 | |
| plic_write: offset=0xe0, val=0x1 | |
| plic_write: offset=0xe4, val=0x1 | |
| plic_write: offset=0xe8, val=0x1 | |
| plic_write: offset=0xec, val=0x1 | |
| plic_write: offset=0xf0, val=0x1 | |
| plic_write: offset=0xf4, val=0x1 | |
| plic_write: offset=0xf8, val=0x1 | |
| plic_write: offset=0xfc, val=0x1 | |
| plic_write: offset=0x100, val=0x1 | |
| plic_write: offset=0x104, val=0x1 | |
| plic_write: offset=0x108, val=0x1 | |
| plic_write: offset=0x10c, val=0x1 | |
| plic_write: offset=0x110, val=0x1 | |
| plic_write: offset=0x114, val=0x1 | |
| plic_write: offset=0x118, val=0x1 | |
| plic_write: offset=0x11c, val=0x1 | |
| plic_write: offset=0x120, val=0x1 | |
| plic_write: offset=0x124, val=0x1 | |
| plic_write: offset=0x128, val=0x1 | |
| plic_write: offset=0x12c, val=0x1 | |
| plic_write: offset=0x130, val=0x1 | |
| plic_write: offset=0x134, val=0x1 | |
| plic_write: offset=0x138, val=0x1 | |
| plic_write: offset=0x13c, val=0x1 | |
| plic_write: offset=0x140, val=0x1 | |
| plic_write: offset=0x144, val=0x1 | |
| plic_write: offset=0x148, val=0x1 | |
| plic_write: offset=0x201000, val=0x0 | |
| uart_register: Registering /dev/console | |
| plic_read: offset=0x2080 | |
| plic_write: offset=0x2080, val=0x100000 | |
| target_read_slow: invalid physical address 0x0000000030002024 | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| work_start_lowpri: Starting low-priority kernel worker thread(s) | |
| riscv_swint: Entry: regs: 0x50407950 cmd: 2 | |
| up_dump_register: EPC: 00000000502027bc | |
| up_dump_register: A0: 0000000000000002 A1: 0000000050400d08 A2: 00000000504098d0 A3: 00000000504098d0 | |
| up_dump_register: A4: 00000000504092c0 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000003 | |
| up_dump_register: T0: 000000000000002e T1: 0000000000000000 T2: 00000000000001ff T3: 000000005040c030 | |
| up_dump_register: T4: 000000005040c028 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000050400d08 S1: 8000000200046002 S2: 0000000050400e90 S3: 0000000050400cf8 | |
| up_dump_register: S4: fffffffffffffff3 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000050407b60 FP: 0000000050400d08 TP: 0000000000000000 RA: 00000000502027bc | |
| riscv_swint: SWInt Return: Context switch! | |
| up_dump_register: EPC: 0000000050203612 | |
| up_dump_register: A0: 0000000000000000 A1: 0000000000000000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| plic_write: offset=0xdc, val=0x1 | |
| plic_write: offset=0xe0, val=0x1 | |
| plic_write: offset=0xe4, val=0x1 | |
| plic_write: offset=0xe8, val=0x1 | |
| plic_write: offset=0xec, val=0x1 | |
| plic_write: offset=0xf0, val=0x1 | |
| plic_write: offset=0xf4, val=0x1 | |
| plic_write: offset=0xf8, val=0x1 | |
| plic_write: offset=0xfc, val=0x1 | |
| plic_write: offset=0x100, val=0x1 | |
| plic_write: offset=0x104, val=0x1 | |
| plic_write: offset=0x108, val=0x1 | |
| plic_write: offset=0x10c, val=0x1 | |
| plic_write: offset=0x110, val=0x1 | |
| plic_write: offset=0x114, val=0x1 | |
| plic_write: offset=0x118, val=0x1 | |
| plic_write: offset=0x11c, val=0x1 | |
| plic_write: offset=0x120, val=0x1 | |
| plic_write: offset=0x124, val=0x1 | |
| plic_write: offset=0x128, val=0x1 | |
| plic_write: offset=0x12c, val=0x1 | |
| plic_write: offset=0x130, val=0x1 | |
| plic_write: offset=0x134, val=0x1 | |
| plic_write: offset=0x138, val=0x1 | |
| plic_write: offset=0x13c, val=0x1 | |
| plic_write: offset=0x140, val=0x1 | |
| plic_write: offset=0x144, val=0x1 | |
| plic_write: offset=0x148, val=0x1 | |
| plic_write: offset=0x201000, val=0x0 | |
| uart_register: Registering /dev/console | |
| plic_read: offset=0x2080 | |
| plic_write: offset=0x2080, val=0x100000 | |
| target_read_slow: invalid physical address 0x0000000030002024 | |
| target_write_slow: invalid physical address 0x0000000030002024 | |
| work_start_lowpri: Starting low-priority kernel worker thread(s) | |
| riscv_swint: Entry: regs: 0x50407950 cmd: 2 | |
| up_dump_register: EPC: 00000000502027bc | |
| up_dump_register: A0: 0000000000000002 A1: 0000000050400d08 A2: 00000000504098d0 A3: 00000000504098d0 | |
| up_dump_register: A4: 00000000504092c0 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000003 | |
| up_dump_register: T0: 000000000000002e T1: 0000000000000000 T2: 00000000000001ff T3: 000000005040c030 | |
| up_dump_register: T4: 000000005040c028 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000050400d08 S1: 8000000200046002 S2: 0000000050400e90 S3: 0000000050400cf8 | |
| up_dump_register: S4: fffffffffffffff3 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000050407b60 FP: 0000000050400d08 TP: 0000000000000000 RA: 00000000502027bc | |
| riscv_swint: SWInt Return: Context switch! | |
| up_dump_register: EPC: 0000000050203612 | |
| up_dump_register: A0: 0000000000000000 A1: 0000000000000000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040c800 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000000000000 | |
| nx_start_application: Starting init task: /system/bin/init | |
| elf_symname: Symbol has no name | |
| elf_symvalue: SHN_UNDEF: Failed to get symbol name: -3 | |
| elf_relocateadd: Section 2 reloc 2: Undefined symbol[0] has no name: -3 | |
| up_exit: TCB=0x504098d0 exiting | |
| riscv_swint: Entry: regs: 0x5040c5a0 cmd: 1 | |
| up_dump_register: EPC: 000000005020b198 | |
| up_dump_register: A0: 0000000000000001 A1: 00000000504092c0 A2: 0000000000000000 A3: 0000000000000002 | |
| up_dump_register: A4: 000000005040c000 A5: 0000000000000000 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000050400e90 S1: 00000000504098d0 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040c7b0 FP: 0000000050400e90 TP: 0000000000000000 RA: 000000005020b198 | |
| riscv_swint: SWInt Return: Context switch! | |
| up_dump_register: EPC: 0000000050203612 | |
| up_dump_register: A0: 0000000000000000 A1: 0000000000000000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040a800 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000000000000 | |
| riscv_swint: Entry: regs: 0x5040a540 cmd: 2 | |
| up_dump_register: EPC: 0000000050204dbe | |
| up_dump_register: A0: 0000000000000002 A1: 00000000504092c0 A2: 000000005040b8b0 A3: 0000000050400e90 | |
| up_dump_register: A4: 0000000000000064 A5: 0000000000000000 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 00000000504092c0 S1: 0000000050401aa0 S2: 0000000200042020 S3: 0000000000000001 | |
| up_dump_register: S4: 0000000050400e90 S5: 0000000000000002 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040a750 FP: 00000000504092c0 TP: 0000000000000000 RA: 0000000050204dbe | |
| riscv_swint: SWInt Return: Context switch! | |
| up_dump_register: EPC: 0000000050203612 | |
| up_dump_register: A0: 0000000000000000 A1: 0000000000000000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040b6a0 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000000000000 | |
| riscv_swint: Entry: regs: 0x5040b470 cmd: 4 | |
| up_dump_register: EPC: 000000005020b58a | |
| up_dump_register: A0: 0000000000000004 A1: 000000008000004a A2: 0000000000000001 A3: 0000000080202010 | |
| up_dump_register: A4: 0000000000000000 A5: 000000008000004a A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040b680 FP: 0000000000000000 TP: 0000000000000000 RA: 000000005020b58a | |
| riscv_swint: SWInt Return: 1 | |
| raise_exception2: cause=8, tval=0x0 | |
| pc =00000000800019c6 ra =0000000080000086 sp =0000000080202bc0 gp =0000000000000000 | |
| tp =0000000000000000 t0 =0000000000000000 t1 =0000000000000000 t2 =0000000000000000 | |
| s0 =0000000000000001 s1 =0000000080202010 a0 =000000000000000d a1 =0000000000000000 | |
| a2 =0000000080202bc8 a3 =0000000080202010 a4 =0000000080000030 a5 =0000000000000000 | |
| a6 =0000000000000101 a7 =0000000000000000 s2 =0000000000000000 s3 =0000000000000000 | |
| s4 =0000000000000000 s5 =0000000000000000 s6 =0000000000000000 s7 =0000000000000000 | |
| s8 =0000000000000000 s9 =0000000000000000 s10=0000000000000000 s11=0000000000000000 | |
| t3 =0000000000000000 t4 =0000000000000000 t5 =0000000000000000 t6 =0000000 | |
| 000000000 | |
| priv=U mstatus=0000000a00040021 cycles=80272195 | |
| mideleg=0000000000000000 mie=0000000000000000 mip=0000000000000080 | |
| raise_exception2: cause=2, tval=0x0 | |
| tinyemu: Unknown mcause 2, quitting |
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