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NuttX Kernel PinePhone MIPI DSI Test Log. See https://lupyuen.github.io/articles/dsi3
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| DRAM: 2048 MiB | |
| Trying to boot from MMC1 | |
| NOTICE: BL31: v2.2(release):v2.2-904-gf9ea3a629 | |
| NOTICE: BL31: Built : 15:32:12, Apr 9 2020 | |
| NOTICE: BL31: Detected Allwinner A64/H64/R18 SoC (1689) | |
| NOTICE: BL31: Found U-Boot DTB at 0x4064410, model: PinePhone | |
| NOTICE: PSCI: System suspend is unavailable | |
| U-Boot 2020.07 (Nov 08 2020 - 00:15:12 +0100) | |
| DRAM: 2 GiB | |
| MMC: Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c10000' | |
| mmc@1c0f000: 0, mmc@1c10000: 2, mmc@1c11000: 1 | |
| Loading Environment from FAT... *** Warning - bad CRC, using default environment | |
| starting USB... | |
| No working controllers found | |
| Hit any key to stop autoboot: 0 | |
| switch to partitions #0, OK | |
| mmc0 is current device | |
| Scanning mmc 0:1... | |
| Found U-Boot script /boot.scr | |
| 653 bytes read in 3 ms (211.9 KiB/s) | |
| ## Executing script at 4fc00000 | |
| gpio: pin 114 (gpio 114) value is 1 | |
| 173701 bytes read in 11 ms (15.1 MiB/s) | |
| Uncompressed size: 10326016 = 0x9D9000 | |
| 36162 bytes read in 5 ms (6.9 MiB/s) | |
| 1078500 bytes read in 50 ms (20.6 MiB/s) | |
| ## Flattened Device Tree blob at 4fa00000 | |
| Booting using the fdt blob at 0x4fa00000 | |
| Loading Ramdisk to 49ef8000, end 49fff4e4 ... OK | |
| Loading Device Tree to 0000000049eec000, end 0000000049ef7d41 ... OK | |
| Starting kernel ... | |
| - Ready to Boot CPU | |
| - Boot from EL2 | |
| - Boot from EL1 | |
| - Boot to C runtime for OS Initialize | |
| psci_detect: Detected PSCI v1.1 | |
| nx_start: Entry | |
| up_allocate_heap: heap_start=0x0x40a59000, heap_size=0x75a7000 | |
| gic_validate_dist_version: GICv2 detected | |
| up_timer_initialize: up_timer_initialize: cp15 timer(s) running at 24.00MHz, cycle 24000 | |
| uart_register: Registering /dev/console | |
| uart_register: Registering /dev/ttyS0 | |
| work_start_highpri: Starting high-priority kernel worker thread(s) | |
| nx_start_application: Starting init thread | |
| lib_cxx_initialize: _sinit: 0x400e9000 _einit: 0x400e9000 | |
| nsh: sysinit: fopen failed: 2 | |
| nshn:x _msktfaarttf:s :C PcUo0m:m aBnedg innonti nfgo uInddl | |
| e | |
| L | |
| oNoupt | |
| t | |
| Shell (NSH) NuttX-11.0.0-pinephone | |
| nsh> | |
| nsh> | |
| nsh> uname -a | |
| NuttX 11.0.0-pinephone 2a1577a-dirty Dec 9 2022 13:57:47 arm64 pinephone | |
| nsh> | |
| nsh> hello 0 | |
| task_spawn: name=hello entry=0x400a0a20 file_actions=0x40a5ea40 attr=0x40a5ea48 argv=0x40a5eb90 | |
| spawn_execattrs: Setting policy=2 priority=100 for pid=3 | |
| pinephone-nuttx/render.zig: hello_main | |
| backlight_enable: start, percent=90 | |
| Configure PL10 for PWM | |
| *0x1f02c04: clear 0x700, set 0x200 | |
| *0x1f02c04 = 0x77277 | |
| Disable R_PWM | |
| *0x1f03800: clear 0x40, set 0x0 | |
| *0x1f03800 = 0x0 | |
| Configure R_PWM Period | |
| *0x1f03804 = 0x4af0437 | |
| Enable R_PWM | |
| *0x1f03800 = 0x5f | |
| Configure PH10 for Output | |
| *0x1c20900: clear 0x700, set 0x100 | |
| *0x1c20900 = 0x7177 | |
| Set PH10 to High | |
| *0x1c2090c: clear 0x400, set 0x400 | |
| *0x1c2090c = 0x400 | |
| backlight_enable: end | |
| tcon0_init: start | |
| Configure PLL_VIDEO0 | |
| *0x1c20010 = 0x81006207 | |
| Enable LDO1 and LDO2 | |
| *0x1c20040 = 0xc00000 | |
| Configure MIPI PLL | |
| *0x1c20040 = 0x80c0071a | |
| Set TCON0 Clock Source to MIPI PLL | |
| *0x1c20118 = 0x80000000 | |
| Enable TCON0 Clock | |
| *0x1c20064 = 0x8 | |
| Deassert TCON0 Reset | |
| *0x1c202c4 = 0x8 | |
| Disable TCON0 and Interrupts | |
| *0x1c0c000 = 0x0 | |
| *0x1c0c004 = 0x0 | |
| *0x1c0c008 = 0x0 | |
| Enable Tristate Output | |
| *0x1c0c08c = 0xffffffff | |
| *0x1c0c0f4 = 0xffffffff | |
| Set DCLK to MIPI PLL / 6 | |
| *0x1c0c044 = 0x80000006 | |
| *0x1c0c040 = 0x81000000 | |
| *0x1c0c048 = 0x2cf059f | |
| *0x1c0c0f8 = 0x8 | |
| *0x1c0c060 = 0x10010005 | |
| Set CPU Panel Trigger | |
| *0x1c0c160 = 0x2f02cf | |
| *0x1c0c164 = 0x59f | |
| *0x1c0c168 = 0x1bc2000a | |
| Set Safe Period | |
| *0x1c0c1f0 = 0xbb80003 | |
| Enable Output Triggers | |
| *0x1c0c08c = 0xe0000000 | |
| Enable TCON0 | |
| *0x1c0c000: clear 0x80000000, set 0x80000000 | |
| *0x1c0c000 = 0x80000000 | |
| tcon0_init: end | |
| display_board_init: start | |
| Configure PD23 for Output | |
| *0x1c20874: clear 0x70000000, set 0x10000000 | |
| *0x1c20874 = 0x17711177 | |
| Set PD23 to Low | |
| *0x1c2087c: clear 0x800000, set 0x0 | |
| *0x1c2087c = 0x0 | |
| Set DLDO1 Voltage to 3.3V | |
| pmic_write: reg=0x15, val=0x1a | |
| rsb_write: rt_addr=0x2d, reg_addr=0x15, value=0x1a | |
| *0x1f0342c = 0x4e | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x15 | |
| *0x1f0341c = 0x1a | |
| *0x1f03400 = 0x80 | |
| pmic_clrsetbits: reg=0x12, clr_mask=0x0, set_mask=0x8 | |
| rsb_read: rt_addr=0x2d, reg_addr=0x12 | |
| *0x1f0342c = 0x8b | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x12 | |
| *0x1f03400 = 0x80 | |
| rsb_write: rt_addr=0x2d, reg_addr=0x12, value=0xd9 | |
| *0x1f0342c = 0x4e | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x12 | |
| *0x1f0341c = 0xd9 | |
| *0x1f03400 = 0x80 | |
| Set LDO Voltage to 3.3V | |
| pmic_write: reg=0x91, val=0x1a | |
| rsb_write: rt_addr=0x2d, reg_addr=0x91, value=0x1a | |
| *0x1f0342c = 0x4e | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x91 | |
| *0x1f0341c = 0x1a | |
| *0x1f03400 = 0x80 | |
| Enable LDO mode on GPIO0 | |
| pmic_write: reg=0x90, val=0x3 | |
| rsb_write: rt_addr=0x2d, reg_addr=0x90, value=0x3 | |
| *0x1f0342c = 0x4e | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x90 | |
| *0x1f0341c = 0x3 | |
| *0x1f03400 = 0x80 | |
| Set DLDO2 Voltage to 1.8V | |
| pmic_write: reg=0x16, val=0xb | |
| rsb_write: rt_addr=0x2d, reg_addr=0x16, value=0xb | |
| *0x1f0342c = 0x4e | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x16 | |
| *0x1f0341c = 0xb | |
| *0x1f03400 = 0x80 | |
| pmic_clrsetbits: reg=0x12, clr_mask=0x0, set_mask=0x10 | |
| rsb_read: rt_addr=0x2d, reg_addr=0x12 | |
| *0x1f0342c = 0x8b | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x12 | |
| *0x1f03400 = 0x80 | |
| rsb_write: rt_addr=0x2d, reg_addr=0x12, value=0xd9 | |
| *0x1f0342c = 0x4e | |
| *0x1f03430 = 0x2d0000 | |
| *0x1f03410 = 0x12 | |
| *0x1af6043_4m1icp i=_ d0sxid_9e | |
| n | |
| a b l*e0:x 1Efn0a3b4l0e0 M=I P0Ix 8D0S | |
| I | |
| WBauist | |
| fao6r4 _pmoiwpeir_ dssuip_pelnya balned: pEonwaebrl-eo nD SiIn iBtl | |
| o | |
| cdki | |
| s | |
| pal6a4y__mbiopair_dd_siin_ietn:a belned: | |
| Set Instructions | |
| a64_mipi_dsi_enable: Configure Jump Instructions | |
| a64_mipi_dsi_enable: Set Video Start Delay | |
| a64_mipi_dsi_enable: Set Burst | |
| a64_mipi_dsi_enable: Set Instruction Loop | |
| a64_mipi_dsi_enable: Set Pixel Format | |
| a64_mipi_dsi_enable: Set Sync Timings | |
| a64_mipi_dsi_enable: Set Basic Size | |
| a64_mipi_dsi_enable: Set Horizontal Blanking | |
| a64_mipi_dsi_enable: Set Vertical Blanking | |
| a64_mipi_dphy_enable: Set DSI Clock to 150 MHz | |
| a64_mipi_dphy_enable: Power on DPHY Tx | |
| a64_mipi_dphy_enable: Enable DPHY | |
| a64_mipi_dphy_enable: Enable LDOR, LDOC, LDOD | |
| panel_reset: start | |
| Configure PD23 for Output | |
| *0x1c20874: clear 0x70000000, set 0x10000000 | |
| *0x1c20874 = 0x17711177 | |
| Set PD23 to High | |
| *0x1c2087c: clear 0x800000, set 0x8000p0i0n | |
| e | |
| p h o*n0ex_1pca2n0e8l7_ci n=i t0:x 8p0a0n0e0l0_ | |
| i | |
| nwiati:t sftoarr ti | |
| n | |
| iwtriiatlei_zdactsi:o nw | |
| r | |
| iptaenDecls_:r elseent=:4 | |
| e | |
| nbdu | |
| f | |
| (0x40ae17d0): | |
| 0000 b9 f1 12 83 .... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=4 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=4 | |
| a64_mipi_dsi_write: pktlen=10 | |
| pkt (0x40ae16e0): | |
| 0000 39 04 00 2c b9 f1 12 83 84 5d 9..,.....] | |
| write_dcs: ret=4 | |
| write_dcs: writeDcs: len=28 | |
| buf (0x40ae1838): | |
| 0000 ba 33 81 05 f9 0e 0e 20 00 00 00 00 00 00 00 44 .3..... .......D | |
| 0010 25 00 91 0a 00 00 02 4f 11 00 00 37 %......O...7 | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=28 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=28 | |
| a64_mipi_dsi_write: pktlen=34 | |
| pkt (0x40ae16e0): | |
| 0000 39 1c 00 2f ba 33 81 05 f9 0e 0e 20 00 00 00 00 9../.3..... .... | |
| 0010 00 00 00 44 25 00 91 0a 00 00 02 4f 11 00 00 37 ...D%......O...7 | |
| 0020 2c e2 ,. | |
| write_dcs: ret=28 | |
| write_dcs: writeDcs: len=5 | |
| buf (0x40ae17e8): | |
| 0000 b8 25 22 20 03 .%" . | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=5 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=5 | |
| a64_mipi_dsi_write: pktlen=11 | |
| pkt (0x40ae16e0): | |
| 0000 39 05 00 36 b8 25 22 20 03 03 72 9..6.%" ..r | |
| write_dcs: ret=5 | |
| write_dcs: writeDcs: len=11 | |
| buf (0x40ae1808): | |
| 0000 b3 10 10 05 05 03 ff 00 00 00 00 ........... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=11 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=11 | |
| a64_mipi_dsi_write: pktlen=17 | |
| pkt (0x40ae16e0): | |
| 0000 39 0b 00 2c b3 10 10 05 05 03 ff 00 00 00 00 6f 9..,...........o | |
| 0010 bc . | |
| write_dcs: ret=11 | |
| write_dcs: writeDcs: len=10 | |
| buf (0x40ae17f8): | |
| 0000 c0 73 73 50 50 00 c0 08 70 00 .ssPP...p. | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=10 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=10 | |
| a64_mipi_dsi_write: pktlen=16 | |
| pkt (0x40ae16e0): | |
| 0000 39 0a 00 36 c0 73 73 50 50 00 c0 08 70 00 1b 6a 9..6.ssPP...p..j | |
| write_dcs: ret=10 | |
| write_dcs: writeDcs: len=2 | |
| buf (0x40ae17a8): | |
| 0000 bc 4e .N | |
| a64_mipi_dsi_write: channel=0, cmd=0x15, txlen=2 | |
| mipi_dsi_short_packet: channel=0, cmd=0x15, txlen=2 | |
| a64_mipi_dsi_write: pktlen=4 | |
| pkt (0x40ae16e0): | |
| 0000 15 bc 4e 35 ..N5 | |
| write_dcs: ret=2 | |
| write_dcs: writeDcs: len=2 | |
| buf (0x40ae17b0): | |
| 0000 cc 0b .. | |
| a64_mipi_dsi_write: channel=0, cmd=0x15, txlen=2 | |
| mipi_dsi_short_packet: channel=0, cmd=0x15, txlen=2 | |
| a64_mipi_dsi_write: pktlen=4 | |
| pkt (0x40ae16e0): | |
| 0000 15 cc 0b 22 ..." | |
| write_dcs: ret=2 | |
| write_dcs: writeDcs: len=2 | |
| buf (0x40ae17b8): | |
| 0000 b4 80 .. | |
| a64_mipi_dsi_write: channel=0, cmd=0x15, txlen=2 | |
| mipi_dsi_short_packet: channel=0, cmd=0x15, txlen=2 | |
| a64_mipi_dsi_write: pktlen=4 | |
| pkt (0x40ae16e0): | |
| 0000 15 b4 80 22 ..." | |
| write_dcs: ret=2 | |
| write_dcs: writeDcs: len=4 | |
| buf (0x40ae17d8): | |
| 0000 b2 f0 12 f0 .... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=4 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=4 | |
| a64_mipi_dsi_write: pktlen=10 | |
| pkt (0x40ae16e0): | |
| 0000 39 04 00 2c b2 f0 12 f0 51 86 9..,....Q. | |
| write_dcs: ret=4 | |
| write_dcs: writeDcs: len=15 | |
| buf (0x40ae1828): | |
| 0000 e3 00 00 0b 0b 10 10 00 00 00 00 ff 00 c0 10 ............... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=15 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=15 | |
| a64_mipi_dsi_write: pktlen=21 | |
| pkt (0x40ae16e0): | |
| 0000 39 0f 00 0f e3 00 00 0b 0b 10 10 00 00 00 00 ff 9............... | |
| 0010 00 c0 10 36 0f ...6. | |
| write_dcs: ret=15 | |
| write_dcs: writeDcs: len=6 | |
| buf (0x40ae17f0): | |
| 0000 c6 01 00 ff ff 00 ...... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=6 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=6 | |
| a64_mipi_dsi_write: pktlen=12 | |
| pkt (0x40ae16e0): | |
| 0000 39 06 00 30 c6 01 00 ff ff 00 8e 25 9..0.......% | |
| write_dcs: ret=6 | |
| write_dcs: writeDcs: len=13 | |
| buf (0x40ae1818): | |
| 0000 c1 74 00 32 32 77 f1 ff ff cc cc 77 77 .t.22w.....ww | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=13 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=13 | |
| a64_mipi_dsi_write: pktlen=19 | |
| pkt (0x40ae16e0): | |
| 0000 39 0d 00 13 c1 74 00 32 32 77 f1 ff ff cc cc 77 9....t.22w.....w | |
| 0010 77 69 e4 wi. | |
| write_dcs: ret=13 | |
| write_dcs: writeDcs: len=3 | |
| buf (0x40ae17c0): | |
| 0000 b5 07 07 ... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=3 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=3 | |
| a64_mipi_dsi_write: pktlen=9 | |
| pkt (0x40ae16e0): | |
| 0000 39 03 00 09 b5 07 07 7b b3 9......{. | |
| write_dcs: ret=3 | |
| write_dcs: writeDcs: len=3 | |
| buf (0x40ae17c8): | |
| 0000 b6 2c 2c .,, | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=3 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=3 | |
| a64_mipi_dsi_write: pktlen=9 | |
| pkt (0x40ae16e0): | |
| 0000 39 03 00 09 b6 2c 2c 55 04 9....,,U. | |
| write_dcs: ret=3 | |
| write_dcs: writeDcs: len=4 | |
| buf (0x40ae17e0): | |
| 0000 bf 02 11 00 .... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=4 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=4 | |
| a64_mipi_dsi_write: pktlen=10 | |
| pkt (0x40ae16e0): | |
| 0000 39 04 00 2c bf 02 11 00 b5 e9 9..,...... | |
| write_dcs: ret=4 | |
| write_dcs: writeDcs: len=64 | |
| buf (0x40ae18c0): | |
| 0000 e9 82 10 06 05 a2 0a a5 12 31 23 37 83 04 bc 27 .........1#7...' | |
| 0010 38 0c 00 03 00 00 00 0c 00 03 00 00 00 75 75 31 8............uu1 | |
| 0020 88 88 88 88 88 88 13 88 64 64 20 88 88 88 88 88 ........dd ..... | |
| 0030 88 02 88 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=64 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=64 | |
| a64_mipi_dsi_write: pktlen=70 | |
| pkt (0x40ae16e0): | |
| 0000 39 40 00 25 e9 82 10 06 05 a2 0a a5 12 31 23 37 9@.%.........1#7 | |
| 0010 83 04 bc 27 38 0c 00 03 00 00 00 0c 00 03 00 00 ...'8........... | |
| 0020 00 75 75 31 88 88 88 88 88 88 13 88 64 64 20 88 .uu1........dd . | |
| 0030 88 88 88 88 88 02 88 00 00 00 00 00 00 00 00 00 ................ | |
| 0040 00 00 00 00 65 03 ....e. | |
| write_dcs: ret=64 | |
| write_dcs: writeDcs: len=62 | |
| buf (0x40ae1880): | |
| 0000 ea 02 21 00 00 00 00 00 00 00 00 00 00 02 46 02 ..!...........F. | |
| 0010 88 88 88 88 88 88 64 88 13 57 13 88 88 88 88 88 ......d..W...... | |
| 0020 88 75 88 23 14 00 00 02 00 00 00 00 00 00 00 00 .u.#............ | |
| 0030 00 00 00 00 00 00 00 03 0a a5 00 00 00 00 .............. | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=62 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=62 | |
| a64_mipi_dsi_write: pktlen=68 | |
| pkt (0x40ae16e0): | |
| 0000 39 3e 00 1a ea 02 21 00 00 00 00 00 00 00 00 00 9>....!......... | |
| 0010 00 02 46 02 88 88 88 88 88 88 64 88 13 57 13 88 ..F.......d..W.. | |
| 0020 88 88 88 88 88 75 88 23 14 00 00 02 00 00 00 00 .....u.#........ | |
| 0030 00 00 00 00 00 00 00 00 00 00 00 03 0a a5 00 00 ................ | |
| 0040 00 00 24 1b ..$. | |
| write_dcs: ret=62 | |
| write_dcs: writeDcs: len=35 | |
| buf (0x40ae1858): | |
| 0000 e0 00 09 0d 23 27 3c 41 35 07 0d 0e 12 13 10 12 ....#'<A5....... | |
| 0010 12 18 00 09 0d 23 27 3c 41 35 07 0d 0e 12 13 10 .....#'<A5...... | |
| 0020 12 12 18 ... | |
| a64_mipi_dsi_write: channel=0, cmd=0x39, txlen=35 | |
| mipi_dsi_long_packet: channel=0, cmd=0x39, txlen=35 | |
| a64_mipi_dsi_write: pktlen=41 | |
| pkt (0x40ae16e0): | |
| 0000 39 23 00 20 e0 00 09 0d 23 27 3c 41 35 07 0d 0e 9#. ....#'<A5... | |
| 0010 12 13 10 12 12 18 00 09 0d 23 27 3c 41 35 07 0d .........#'<A5.. | |
| 0020 0e 12 13 10 12 12 18 93 bf ......... | |
| write_dcs: ret=35 | |
| write_dcs: writeDcs: len=1 | |
| buf (0x40ae1798): | |
| 0000 11 . | |
| a64_mipi_dsi_write: channel=0, cmd=0x5, txlen=1 | |
| mipi_dsi_short_packet: channel=0, cmd=0x5, txlen=1 | |
| a64_mipi_dsi_write: pktlen=4 | |
| pkt (0x40ae16e0): | |
| 0000 05 11 00 36 ...6 | |
| write_dcs: ret=1 | |
| write_dcs: writeDcs: len=1 | |
| buf (0x40ae17a0): | |
| 0000 29 ) | |
| a64_mipi_dsi_write: channel=0, cmd=0x5, txlen=1 | |
| mipi_dsi_short_packet: channel=0, cmd=0x5, txlen=1 | |
| a64_mipi_dsi_write: pktlen=4 | |
| pkt (0x40ae16e0): | |
| 0000 05 29 00 1c .).. | |
| write_dcs: ret=1 | |
| pinephone_panel_init: panel_init: end | |
| a64_mipi_dsi_start: Start HSC | |
| a64_mipi_dsi_start: Commit | |
| a64_mipi_dsi_start: Instruction Function Lane | |
| a64_mipi_dsi_start: Start HSD | |
| a64_mipi_dsi_start: Commit | |
| de2_init: start | |
| Set High Speed SRAM to DMA Mode | |
| *0x1c00004 = 0x0 | |
| Set Display Engine PLL to 297 MHz | |
| *0x1c20048 = 0x81001701 | |
| Wait for Display Engine PLL to be stable | |
| Set Special Clock to Display Engine PLL | |
| *0x1c20104: clear 0x87000000, set 0x81000000 | |
| *0x1c20104 = 0x81000000 | |
| Enable AHB for Display Engine: De-Assert Display Engine | |
| *0x1c202c4: clear 0x1000, set 0x1000 | |
| *0x1c202c4 = 0x1008 | |
| Enable AHB for Display Engine: Pass Display Engine | |
| *0x1c20064: clear 0x1000, set 0x1000 | |
| *0x1c20064 = 0x1008 | |
| Enable Clock for MIXER0: SCLK Clock Pass | |
| *0x1000000: clear 0x1, set 0x1 | |
| *0x1000000 = 0x1 | |
| Enable Clock for MIXER0: HCLK Clock Reset Off | |
| *0x1000008: clear 0x1, set 0x1 | |
| *0x1000008 = 0x1 | |
| Enable Clock for MIXER0: HCLK Clock Pass | |
| *0x1000004: clear 0x1, set 0x1 | |
| *0x1000004 = 0x1 | |
| Route MIXER0 to TCON0 | |
| *0x1000010: clear 0x1, set 0x0 | |
| *0x1000010 = 0x0 | |
| Clear MIXER0 Registers: GLB, BLD, OVL_V, OVL_UI | |
| *0x1100000 = 0x0 | |
| to *0x1105fff = 0x0 | |
| Disable MIXER0 VSU | |
| *0x1120000 = 0x0 | |
| Disable MIXER0 Undocumented | |
| *0x1130000 = 0x0 | |
| Disable MIXER0 UI_SCALER1 | |
| *0x1140000 = 0x0 | |
| Disable MIXER0 UI_SCALER2 | |
| *0x1150000 = 0x0 | |
| Disable MIXER0 FCE | |
| *0x11a0000 = 0x0 | |
| Disable MIXER0 BWS | |
| *0x11a2000 = 0x0 | |
| Disable MIXER0 LTI | |
| *0x11a4000 = 0x0 | |
| Disable MIXER0 PEAKING | |
| *0x11a6000 = 0x0 | |
| Disable MIXER0 ASE | |
| *0x11a8000 = 0x0 | |
| Disable MIXER0 FCC | |
| *0x11aa000 = 0x0 | |
| Disable MIXER0 DRC | |
| *0x11b0000 = 0x0 | |
| Enable MIXER0 | |
| *0x1100000 = 0x1 | |
| de2_init: end | |
| renderGraphics: start | |
| initUiBlender: start | |
| Set Blender Background | |
| *0x1101088 = 0xff000000 | |
| Set Blender Pre-Multiply | |
| *0x1101084 = 0x0 | |
| initUiBlender: end | |
| initUiChannel: start | |
| Channel 1: Set Overlay (720 x 1440) | |
| *0x1103000 = 0xff000405 | |
| *0x1103010 = 0x4010b000 | |
| *0x110300c = 0xb40 | |
| *0x1103004 = 0x59f02cf | |
| *0x1103088 = 0x59f02cf | |
| *0x1103008 = 0x0 | |
| Channel 1: Set Blender Output | |
| *0x110108c = 0x59f02cf | |
| *0x110000c = 0x59f02cf | |
| Channel 1: Set Blender Input Pipe 0 (720 x 1440) | |
| *0x1101008 = 0x59f02cf | |
| *0x1101004 = 0xff000000 | |
| *0x110100c = 0x0 | |
| *0x1101090 = 0x3010301 | |
| Channel 1: Disable Scaler | |
| *0x1140000 = 0x0 | |
| initUiChannel: end | |
| initUiChannel: start | |
| Channel 2: Set Overlay (600 x 600) | |
| *0x1104000 = 0xff000005 | |
| *0x1104010 = 0x40500000 | |
| *0x110400c = 0x960 | |
| *0x1104004 = 0x2570257 | |
| *0x1104088 = 0x2570257 | |
| *0x1104008 = 0x0 | |
| Channel 2: Set Blender Input Pipe 1 (600 x 600) | |
| *0x1101018 = 0x2570257 | |
| *0x1101014 = 0xff000000 | |
| *0x110101c = 0x340034 | |
| *0x1101094 = 0x3010301 | |
| Channel 2: Disable Scaler | |
| *0x1150000 = 0x0 | |
| initUiChannel: end | |
| initUiChannel: start | |
| Channel 3: Set Overlay (720 x 1440) | |
| *0x1105000 = 0x7f000005 | |
| *0x1105010 = 0x40660000 | |
| *0x110500c = 0xb40 | |
| *0x1105004 = 0x59f02cf | |
| *0x1105088 = 0x59f02cf | |
| *0x1105008 = 0x0 | |
| Channel 3: Set Blender Input Pipe 2 (720 x 1440) | |
| *0x1101028 = 0x59f02cf | |
| *0x1101024 = 0xff000000 | |
| *0x110102c = 0x0 | |
| *0x1101098 = 0x3010301 | |
| Channel 3: Disable Scaler | |
| *0x1160000 = 0x0 | |
| initUiChannel: end | |
| applySettings: start | |
| Set Blender Route | |
| *0x1101080 = 0x321 | |
| Enable Blender Pipes | |
| *0x1101000 = 0x701 | |
| Apply Settings | |
| *0x1100008 = 0x1 | |
| applySettings: end | |
| renderGraphics: end | |
| nsh> | |
| nsh> |
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