x86_simd_check.c

#include <stdio.h>

#define SIMD_SSE     0x1
#define SIMD_SSE2    0x2
#define SIMD_SSE3    0x4
#define SIMD_SSE4_1  0x8
#define SIMD_SSE4_2  0x10
#define SIMD_AVX     0x20
#define SIMD_AVX2    0x40
#define SIMD_AVX512F 0x80

unsigned x86_simd_check(void){
	register unsigned eax, ebx, ecx, edx, flag = 0;
	__asm volatile("cpuid":"=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx):"a"(1));
	if(edx >> 25 & 1)flag |= SIMD_SSE;
	if(edx >> 26 & 1)flag |= SIMD_SSE2;
	if(ecx >> 0  & 1)flag |= SIMD_SSE3;
	if(ecx >> 19 & 1)flag |= SIMD_SSE4_1;
	if(ecx >> 20 & 1)flag |= SIMD_SSE4_2;
	if(ecx >> 28 & 1)flag |= SIMD_AVX;
	if(ebx >> 5  & 1)flag |= SIMD_AVX2;
	if(ebx >> 16 & 1)flag |= SIMD_AVX512F;
	return flag;
}

#define memcpy_helper(x, y) __builtin_memcpy(x, y, sizeof(y))

int main(){
	char array[40] = "Highest supported SIMD ISA is: ";
	char *s = &array[31];
	unsigned x = x86_simd_check();
	switch(__builtin_clz((x << 1) | 1) - 23){
	case 0: memcpy_helper(s, "AVX 512"); break;
	case 1: memcpy_helper(s, "AVX 2"); break;
	case 2: memcpy_helper(s, "AVX"); break;
	case 3: memcpy_helper(s, "SSE 4.2"); break;
	case 4: memcpy_helper(s, "SSE 4.1"); break;
	case 5: memcpy_helper(s, "SSE 3"); break;
	case 6: memcpy_helper(s, "SSE 2"); break;
	case 7: memcpy_helper(s, "SSE"); break;
	case 8: memcpy_helper(s, "None"); break;
	default:__builtin_unreachable();
	}
	puts(array);
}